Machine Vision using Portenta H7 2
This project aims to develop a face recognition-based access control system using the Arduino Portenta H7 and Vision Shield, leveraging Edge Impulse for machine learning. The system captures facial images, processes them locally using an AI model deployed on the Portenta H7 and determines access based on authorised personnel.
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ethosu65_interface.h
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1
2/*
3 * Copyright (c) 2020-2021 Arm Limited. All rights reserved.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Licensed under the Apache License, Version 2.0 (the License); you may
8 * not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 */
19
20#ifndef ETHOSU65_INTERFACE_H
21#define ETHOSU65_INTERFACE_H
22
23#ifdef __KERNEL__
24#include <linux/types.h>
25#else
26#include <stdint.h>
27#endif
28
29#if !defined(__cplusplus) || __cplusplus < 201402L
30#define CONSTEXPR
31#else
32#define CONSTEXPR constexpr
33#endif
34
35#ifndef __cplusplus
36#define STRUCT struct
37#else
38#define STRUCT
39#endif
40
41#if defined(__cplusplus) && defined(NPU_DISASSEMBLE)
42#include <iomanip>
43#include <sstream>
44#include <vector>
45#endif
46
47#if defined(__cplusplus) && !defined(NPU_NAMESPACE)
48#define NPU_NAMESPACE npu
49#endif
50
51#ifdef __cplusplus
52#include <cstring>
53#include <limits>
54#endif
55
56#ifdef __cplusplus
57namespace NPU_NAMESPACE
58{
59#endif
60#define NNX_ARCH_VERSION_MAJOR 1
61#define NNX_ARCH_VERSION_MINOR 0
62#define NNX_ARCH_VERSION_PATCH 6
63
64// Register offsets
65//
66// Register subpage BASE
67//
68#define NPU_REG_ID 0x0000
69#define NPU_REG_STATUS 0x0004
70#define NPU_REG_CMD 0x0008
71#define NPU_REG_RESET 0x000C
72#define NPU_REG_QBASE 0x0010
73#define NPU_REG_QBASE_HI 0x0014
74#define NPU_REG_QREAD 0x0018
75#define NPU_REG_QCONFIG 0x001C
76#define NPU_REG_QSIZE 0x0020
77#define NPU_REG_PROT 0x0024
78#define NPU_REG_CONFIG 0x0028
79#define NPU_REG_LOCK 0x002C
80#define NPU_REG_REGIONCFG 0x003C
81#define NPU_REG_AXI_LIMIT0 0x0040
82#define NPU_REG_AXI_LIMIT1 0x0044
83#define NPU_REG_AXI_LIMIT2 0x0048
84#define NPU_REG_AXI_LIMIT3 0x004C
85#define BASE_REGISTERS_SIZE 0x0080
86
87//
88// Register subpage BASE_POINTERS
89//
90#define NPU_REG_BASEP_BASE 0x0080
91#define NPU_REG_BASEP_ARRLEN 0x0008
92#define BASE_POINTERS_REGISTERS_SIZE 0x0100
93
94//
95// Register subpage DEBUG
96//
97#define NPU_REG_WD_STATUS 0x0100
98#define NPU_REG_MAC_STATUS 0x0104
99#define NPU_REG_AO_STATUS 0x0108
100#define NPU_REG_DMA_STATUS0 0x0110
101#define NPU_REG_DMA_STATUS1 0x0114
102#define NPU_REG_CLKFORCE 0x0140
103#define NPU_REG_DEBUG_ADDRESS 0x0144
104#define NPU_REG_DEBUG_MISC 0x0148
105#define NPU_REG_DEBUGCORE 0x014C
106#define NPU_REG_DEBUG_BLOCK 0x0150
107#define DEBUG_REGISTERS_SIZE 0x0180
108
109//
110// Register subpage PMU
111//
112#define NPU_REG_PMCR 0x0180
113#define NPU_REG_PMCNTENSET 0x0184
114#define NPU_REG_PMCNTENCLR 0x0188
115#define NPU_REG_PMOVSSET 0x018C
116#define NPU_REG_PMOVSCLR 0x0190
117#define NPU_REG_PMINTSET 0x0194
118#define NPU_REG_PMINTCLR 0x0198
119#define NPU_REG_PMCCNTR 0x01A0
120#define NPU_REG_PMCCNTR_HI 0x01A4
121#define NPU_REG_PMCCNTR_CFG 0x01A8
122#define NPU_REG_PMCAXI_CHAN 0x01AC
123#define PMU_REGISTERS_SIZE 0x0200
124
125//
126// Register subpage TSU_DEBUG
127//
128#define NPU_REG_KERNEL_X 0x0200
129#define NPU_REG_KERNEL_Y 0x0204
130#define NPU_REG_KERNEL_W_M1 0x0208
131#define NPU_REG_KERNEL_H_M1 0x020C
132#define NPU_REG_OFM_CBLK_WIDTH_M1 0x0210
133#define NPU_REG_OFM_CBLK_HEIGHT_M1 0x0214
134#define NPU_REG_OFM_CBLK_DEPTH_M1 0x0218
135#define NPU_REG_IFM_CBLK_DEPTH_M1 0x021C
136#define NPU_REG_OFM_X 0x0220
137#define NPU_REG_OFM_Y 0x0224
138#define NPU_REG_OFM_Z 0x0228
139#define NPU_REG_IFM_Z 0x022C
140#define NPU_REG_PAD_TOP 0x0230
141#define NPU_REG_PAD_LEFT 0x0234
142#define NPU_REG_IFM_CBLK_WIDTH 0x0238
143#define NPU_REG_IFM_CBLK_HEIGHT 0x023C
144#define NPU_REG_DMA_IFM_SRC 0x0240
145#define NPU_REG_DMA_IFM_SRC_HI 0x0244
146#define NPU_REG_DMA_IFM_DST 0x0248
147#define NPU_REG_DMA_OFM_SRC 0x024C
148#define NPU_REG_DMA_OFM_DST 0x0250
149#define NPU_REG_DMA_OFM_DST_HI 0x0254
150#define NPU_REG_DMA_WEIGHT_SRC 0x0258
151#define NPU_REG_DMA_WEIGHT_SRC_HI 0x025C
152#define NPU_REG_DMA_CMD_SRC 0x0260
153#define NPU_REG_DMA_CMD_SRC_HI 0x0264
154#define NPU_REG_DMA_CMD_SIZE 0x0268
155#define NPU_REG_DMA_M2M_SRC 0x026C
156#define NPU_REG_DMA_M2M_SRC_HI 0x0270
157#define NPU_REG_DMA_M2M_DST 0x0274
158#define NPU_REG_DMA_M2M_DST_HI 0x0278
159#define NPU_REG_CURRENT_QREAD 0x027C
160#define NPU_REG_DMA_SCALE_SRC 0x0280
161#define NPU_REG_DMA_SCALE_SRC_HI 0x0284
162#define NPU_REG_CURRENT_BLOCK 0x02B4
163#define NPU_REG_CURRENT_OP 0x02B8
164#define NPU_REG_CURRENT_CMD 0x02BC
165#define TSU_DEBUG_REGISTERS_SIZE 0x02C0
166
167//
168// Register subpage PMU_COUNTERS
169//
170#define NPU_REG_PMEVCNTR_BASE 0x0300
171#define NPU_REG_PMEVCNTR_ARRLEN 0x0004
172#define NPU_REG_PMEVTYPER_BASE 0x0380
173#define NPU_REG_PMEVTYPER_ARRLEN 0x0004
174#define PMU_COUNTERS_REGISTERS_SIZE 0x0400
175
176//
177// Register subpage SHARED_BUFFER
178//
179#define NPU_REG_SHARED_BUFFER_BASE 0x0400
180#define NPU_REG_SHARED_BUFFER_ARRLEN 0x0100
181#define SHARED_BUFFER_REGISTERS_SIZE 0x0800
182
183//
184// Register subpage TSU_IFM
185//
186#define NPU_REG_IFM_PAD_TOP 0x0800
187#define NPU_REG_IFM_PAD_LEFT 0x0804
188#define NPU_REG_IFM_PAD_RIGHT 0x0808
189#define NPU_REG_IFM_PAD_BOTTOM 0x080C
190#define NPU_REG_IFM_DEPTH_M1 0x0810
191#define NPU_REG_IFM_PRECISION 0x0814
192#define NPU_REG_IFM_UPSCALE 0x081C
193#define NPU_REG_IFM_ZERO_POINT 0x0824
194#define NPU_REG_IFM_WIDTH0_M1 0x0828
195#define NPU_REG_IFM_HEIGHT0_M1 0x082C
196#define NPU_REG_IFM_HEIGHT1_M1 0x0830
197#define NPU_REG_IFM_IB_END 0x0834
198#define NPU_REG_IFM_REGION 0x083C
199#define TSU_IFM_REGISTERS_SIZE 0x0840
200
201//
202// Register subpage TSU_OFM
203//
204#define NPU_REG_OFM_WIDTH_M1 0x0844
205#define NPU_REG_OFM_HEIGHT_M1 0x0848
206#define NPU_REG_OFM_DEPTH_M1 0x084C
207#define NPU_REG_OFM_PRECISION 0x0850
208#define NPU_REG_OFM_BLK_WIDTH_M1 0x0854
209#define NPU_REG_OFM_BLK_HEIGHT_M1 0x0858
210#define NPU_REG_OFM_BLK_DEPTH_M1 0x085C
211#define NPU_REG_OFM_ZERO_POINT 0x0860
212#define NPU_REG_OFM_WIDTH0_M1 0x0868
213#define NPU_REG_OFM_HEIGHT0_M1 0x086C
214#define NPU_REG_OFM_HEIGHT1_M1 0x0870
215#define NPU_REG_OFM_REGION 0x087C
216#define TSU_OFM_REGISTERS_SIZE 0x0880
217
218//
219// Register subpage TSU_KERNEL
220//
221#define NPU_REG_KERNEL_WIDTH_M1 0x0880
222#define NPU_REG_KERNEL_HEIGHT_M1 0x0884
223#define NPU_REG_KERNEL_STRIDE 0x0888
224#define NPU_REG_PARALLEL_MODE 0x088C
225#define NPU_REG_ACC_FORMAT 0x0890
226#define NPU_REG_ACTIVATION 0x0894
227#define NPU_REG_ACTIVATION_MIN 0x0898
228#define NPU_REG_ACTIVATION_MAX 0x089C
229#define NPU_REG_WEIGHT_REGION 0x08A0
230#define NPU_REG_SCALE_REGION 0x08A4
231#define NPU_REG_AB_START 0x08B4
232#define NPU_REG_BLOCKDEP 0x08BC
233#define TSU_KERNEL_REGISTERS_SIZE 0x08C0
234
235//
236// Register subpage TSU_DMA
237//
238#define NPU_REG_DMA0_SRC_REGION 0x08C0
239#define NPU_REG_DMA0_DST_REGION 0x08C4
240#define NPU_REG_DMA0_SIZE0 0x08C8
241#define NPU_REG_DMA0_SIZE1 0x08CC
242#define TSU_DMA_REGISTERS_SIZE 0x0900
243
244//
245// Register subpage TSU_IFM2
246//
247#define NPU_REG_IFM2_BROADCAST 0x0900
248#define NPU_REG_IFM2_SCALAR 0x0904
249#define NPU_REG_IFM2_PRECISION 0x0914
250#define NPU_REG_IFM2_ZERO_POINT 0x0924
251#define NPU_REG_IFM2_WIDTH0_M1 0x0928
252#define NPU_REG_IFM2_HEIGHT0_M1 0x092C
253#define NPU_REG_IFM2_HEIGHT1_M1 0x0930
254#define NPU_REG_IFM2_IB_START 0x0934
255#define NPU_REG_IFM2_REGION 0x093C
256#define TSU_IFM2_REGISTERS_SIZE 0x0940
257
258//
259// Register subpage TSU_IFM_BASE
260//
261#define NPU_REG_IFM_BASE0 0x0A00
262#define NPU_REG_IFM_BASE0_HI 0x0A04
263#define NPU_REG_IFM_BASE1 0x0A08
264#define NPU_REG_IFM_BASE1_HI 0x0A0C
265#define NPU_REG_IFM_BASE2 0x0A10
266#define NPU_REG_IFM_BASE2_HI 0x0A14
267#define NPU_REG_IFM_BASE3 0x0A18
268#define NPU_REG_IFM_BASE3_HI 0x0A1C
269#define NPU_REG_IFM_STRIDE_X 0x0A20
270#define NPU_REG_IFM_STRIDE_X_HI 0x0A24
271#define NPU_REG_IFM_STRIDE_Y 0x0A28
272#define NPU_REG_IFM_STRIDE_Y_HI 0x0A2C
273#define NPU_REG_IFM_STRIDE_C 0x0A30
274#define NPU_REG_IFM_STRIDE_C_HI 0x0A34
275#define TSU_IFM_BASE_REGISTERS_SIZE 0x0A40
276
277//
278// Register subpage TSU_OFM_BASE
279//
280#define NPU_REG_OFM_BASE0 0x0A40
281#define NPU_REG_OFM_BASE0_HI 0x0A44
282#define NPU_REG_OFM_BASE1 0x0A48
283#define NPU_REG_OFM_BASE1_HI 0x0A4C
284#define NPU_REG_OFM_BASE2 0x0A50
285#define NPU_REG_OFM_BASE2_HI 0x0A54
286#define NPU_REG_OFM_BASE3 0x0A58
287#define NPU_REG_OFM_BASE3_HI 0x0A5C
288#define NPU_REG_OFM_STRIDE_X 0x0A60
289#define NPU_REG_OFM_STRIDE_X_HI 0x0A64
290#define NPU_REG_OFM_STRIDE_Y 0x0A68
291#define NPU_REG_OFM_STRIDE_Y_HI 0x0A6C
292#define NPU_REG_OFM_STRIDE_C 0x0A70
293#define NPU_REG_OFM_STRIDE_C_HI 0x0A74
294#define TSU_OFM_BASE_REGISTERS_SIZE 0x0A80
295
296//
297// Register subpage TSU_WS_BASE
298//
299#define NPU_REG_WEIGHT_BASE 0x0A80
300#define NPU_REG_WEIGHT_BASE_HI 0x0A84
301#define NPU_REG_WEIGHT_LENGTH 0x0A88
302#define NPU_REG_WEIGHT_LENGTH_HI 0x0A8C
303#define NPU_REG_SCALE_BASE 0x0A90
304#define NPU_REG_SCALE_BASE_HI 0x0A94
305#define NPU_REG_SCALE_LENGTH 0x0A98
306#define NPU_REG_SCALE_LENGTH_HI 0x0A9C
307#define NPU_REG_OFM_SCALE 0x0AA0
308#define NPU_REG_OFM_SCALE_SHIFT 0x0AA4
309#define NPU_REG_OPA_SCALE 0x0AA8
310#define NPU_REG_OPA_SCALE_SHIFT 0x0AAC
311#define NPU_REG_OPB_SCALE 0x0AB0
312#define TSU_WS_BASE_REGISTERS_SIZE 0x0AC0
313
314//
315// Register subpage TSU_DMA_BASE
316//
317#define NPU_REG_DMA0_SRC 0x0AC0
318#define NPU_REG_DMA0_SRC_HI 0x0AC4
319#define NPU_REG_DMA0_DST 0x0AC8
320#define NPU_REG_DMA0_DST_HI 0x0ACC
321#define NPU_REG_DMA0_LEN 0x0AD0
322#define NPU_REG_DMA0_LEN_HI 0x0AD4
323#define NPU_REG_DMA0_SKIP0 0x0AD8
324#define NPU_REG_DMA0_SKIP0_HI 0x0ADC
325#define NPU_REG_DMA0_SKIP1 0x0AE0
326#define NPU_REG_DMA0_SKIP1_HI 0x0AE4
327#define TSU_DMA_BASE_REGISTERS_SIZE 0x0B00
328
329//
330// Register subpage TSU_IFM2_BASE
331//
332#define NPU_REG_IFM2_BASE0 0x0B00
333#define NPU_REG_IFM2_BASE0_HI 0x0B04
334#define NPU_REG_IFM2_BASE1 0x0B08
335#define NPU_REG_IFM2_BASE1_HI 0x0B0C
336#define NPU_REG_IFM2_BASE2 0x0B10
337#define NPU_REG_IFM2_BASE2_HI 0x0B14
338#define NPU_REG_IFM2_BASE3 0x0B18
339#define NPU_REG_IFM2_BASE3_HI 0x0B1C
340#define NPU_REG_IFM2_STRIDE_X 0x0B20
341#define NPU_REG_IFM2_STRIDE_X_HI 0x0B24
342#define NPU_REG_IFM2_STRIDE_Y 0x0B28
343#define NPU_REG_IFM2_STRIDE_Y_HI 0x0B2C
344#define NPU_REG_IFM2_STRIDE_C 0x0B30
345#define NPU_REG_IFM2_STRIDE_C_HI 0x0B34
346#define TSU_IFM2_BASE_REGISTERS_SIZE 0x0B40
347
348//
349// Register subpage TSU_WS1_BASE
350//
351#define NPU_REG_WEIGHT1_BASE 0x0B40
352#define NPU_REG_WEIGHT1_BASE_HI 0x0B44
353#define NPU_REG_WEIGHT1_LENGTH 0x0B48
354#define NPU_REG_WEIGHT1_LENGTH_HI 0x0B4C
355#define NPU_REG_SCALE1_BASE 0x0B50
356#define NPU_REG_SCALE1_BASE_HI 0x0B54
357#define NPU_REG_SCALE1_LENGTH 0x0B58
358#define NPU_REG_SCALE1_LENGTH_HI 0x0B5C
359#define TSU_WS1_BASE_REGISTERS_SIZE 0x0B80
360
361//
362// Register subpage TSU_USER_BASE
363//
364#define TSU_USER_BASE_REGISTERS_SIZE 0x0BC0
365
366//
367// Register subpage TSU_DMA_EBASE
368//
369#define TSU_DMA_EBASE_REGISTERS_SIZE 0x0C00
370
371//
372// Register subpage ID
373//
374#define NPU_REG_REVISION 0x0FC0
375#define NPU_REG_PID4 0x0FD0
376#define NPU_REG_PID5 0x0FD4
377#define NPU_REG_PID6 0x0FD8
378#define NPU_REG_PID7 0x0FDC
379#define NPU_REG_PID0 0x0FE0
380#define NPU_REG_PID1 0x0FE4
381#define NPU_REG_PID2 0x0FE8
382#define NPU_REG_PID3 0x0FEC
383#define NPU_REG_CID0 0x0FF0
384#define NPU_REG_CID1 0x0FF4
385#define NPU_REG_CID2 0x0FF8
386#define NPU_REG_CID3 0x0FFC
387#define ID_REGISTERS_SIZE 0x1000
388
389#ifdef __cplusplus
390// Enum types
391enum class acc_format : uint8_t
392{
393 I32 = 0,
394 I40 = 1,
395 F16 = 2,
396};
397
398enum class activation_clip_range : uint8_t
399{
400 OFM_PRECISION = 0,
401 FORCE_UINT8 = 2,
402 FORCE_INT8 = 3,
403 FORCE_INT16 = 5,
404};
405
406enum class activation_format : uint8_t
407{
408 NHWC = 0,
409 NHCWB16 = 1,
410};
411
412enum class activation_function : uint8_t
413{
414 RELU = 0,
415 TANH = 3,
416 SIGMOID = 4,
417 TABLE_0 = 16,
418 TABLE_1 = 17,
419 TABLE_2 = 18,
420 TABLE_3 = 19,
421 TABLE_4 = 20,
422 TABLE_5 = 21,
423 TABLE_6 = 22,
424 TABLE_7 = 23,
425};
426
427enum class activation_precision : uint8_t
428{
429 B8 = 0,
430 B16 = 1,
431 B32 = 2,
432 B64 = 3,
433};
434
435enum class activation_type : uint8_t
436{
437 UNSIGNED = 0,
438 SIGNED = 1,
439};
440
441enum class axi_mem_encoding : uint8_t
442{
443 DEVICE_NON_BUFFERABLE = 0,
444 DEVICE_BUFFERABLE = 1,
445 NORMAL_NON_CACHEABLE_NON_BUFFERABLE = 2,
446 NORMAL_NON_CACHEABLE_BUFFERABLE = 3,
447 WRITE_THROUGH_NO_ALLOCATE = 4,
448 WRITE_THROUGH_READ_ALLOCATE = 5,
449 WRITE_THROUGH_WRITE_ALLOCATE = 6,
450 WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7,
451 WRITE_BACK_NO_ALLOCATE = 8,
452 WRITE_BACK_READ_ALLOCATE = 9,
453 WRITE_BACK_WRITE_ALLOCATE = 10,
454 WRITE_BACK_READ_AND_WRITE_ALLOCATE = 11,
455};
456
457enum class broadcast_mode : uint8_t
458{
459 DISABLE = 0,
460 ENABLE = 1,
461};
462
463enum class cmd0_opcode : uint16_t
464{
465 NPU_OP_STOP = 0,
466 NPU_OP_IRQ = 1,
467 NPU_OP_CONV = 2,
468 NPU_OP_DEPTHWISE = 3,
469 NPU_OP_POOL = 5,
470 NPU_OP_ELEMENTWISE = 6,
471 NPU_OP_DMA_START = 16,
472 NPU_OP_DMA_WAIT = 17,
473 NPU_OP_KERNEL_WAIT = 18,
474 NPU_OP_PMU_MASK = 19,
475 NPU_SET_IFM_PAD_TOP = 256,
476 NPU_SET_IFM_PAD_LEFT = 257,
477 NPU_SET_IFM_PAD_RIGHT = 258,
478 NPU_SET_IFM_PAD_BOTTOM = 259,
479 NPU_SET_IFM_DEPTH_M1 = 260,
480 NPU_SET_IFM_PRECISION = 261,
481 NPU_SET_IFM_UPSCALE = 263,
482 NPU_SET_IFM_ZERO_POINT = 265,
483 NPU_SET_IFM_WIDTH0_M1 = 266,
484 NPU_SET_IFM_HEIGHT0_M1 = 267,
485 NPU_SET_IFM_HEIGHT1_M1 = 268,
486 NPU_SET_IFM_IB_END = 269,
487 NPU_SET_IFM_REGION = 271,
488 NPU_SET_OFM_WIDTH_M1 = 273,
489 NPU_SET_OFM_HEIGHT_M1 = 274,
490 NPU_SET_OFM_DEPTH_M1 = 275,
491 NPU_SET_OFM_PRECISION = 276,
492 NPU_SET_OFM_BLK_WIDTH_M1 = 277,
493 NPU_SET_OFM_BLK_HEIGHT_M1 = 278,
494 NPU_SET_OFM_BLK_DEPTH_M1 = 279,
495 NPU_SET_OFM_ZERO_POINT = 280,
496 NPU_SET_OFM_WIDTH0_M1 = 282,
497 NPU_SET_OFM_HEIGHT0_M1 = 283,
498 NPU_SET_OFM_HEIGHT1_M1 = 284,
499 NPU_SET_OFM_REGION = 287,
500 NPU_SET_KERNEL_WIDTH_M1 = 288,
501 NPU_SET_KERNEL_HEIGHT_M1 = 289,
502 NPU_SET_KERNEL_STRIDE = 290,
503 NPU_SET_PARALLEL_MODE = 291,
504 NPU_SET_ACC_FORMAT = 292,
505 NPU_SET_ACTIVATION = 293,
506 NPU_SET_ACTIVATION_MIN = 294,
507 NPU_SET_ACTIVATION_MAX = 295,
508 NPU_SET_WEIGHT_REGION = 296,
509 NPU_SET_SCALE_REGION = 297,
510 NPU_SET_AB_START = 301,
511 NPU_SET_BLOCKDEP = 303,
512 NPU_SET_DMA0_SRC_REGION = 304,
513 NPU_SET_DMA0_DST_REGION = 305,
514 NPU_SET_DMA0_SIZE0 = 306,
515 NPU_SET_DMA0_SIZE1 = 307,
516 NPU_SET_IFM2_BROADCAST = 384,
517 NPU_SET_IFM2_SCALAR = 385,
518 NPU_SET_IFM2_PRECISION = 389,
519 NPU_SET_IFM2_ZERO_POINT = 393,
520 NPU_SET_IFM2_WIDTH0_M1 = 394,
521 NPU_SET_IFM2_HEIGHT0_M1 = 395,
522 NPU_SET_IFM2_HEIGHT1_M1 = 396,
523 NPU_SET_IFM2_IB_START = 397,
524 NPU_SET_IFM2_REGION = 399,
525};
526
527enum class cmd1_opcode : uint16_t
528{
529 NPU_SET_IFM_BASE0 = 0,
530 NPU_SET_IFM_BASE1 = 1,
531 NPU_SET_IFM_BASE2 = 2,
532 NPU_SET_IFM_BASE3 = 3,
533 NPU_SET_IFM_STRIDE_X = 4,
534 NPU_SET_IFM_STRIDE_Y = 5,
535 NPU_SET_IFM_STRIDE_C = 6,
536 NPU_SET_OFM_BASE0 = 16,
537 NPU_SET_OFM_BASE1 = 17,
538 NPU_SET_OFM_BASE2 = 18,
539 NPU_SET_OFM_BASE3 = 19,
540 NPU_SET_OFM_STRIDE_X = 20,
541 NPU_SET_OFM_STRIDE_Y = 21,
542 NPU_SET_OFM_STRIDE_C = 22,
543 NPU_SET_WEIGHT_BASE = 32,
544 NPU_SET_WEIGHT_LENGTH = 33,
545 NPU_SET_SCALE_BASE = 34,
546 NPU_SET_SCALE_LENGTH = 35,
547 NPU_SET_OFM_SCALE = 36,
548 NPU_SET_OPA_SCALE = 37,
549 NPU_SET_OPB_SCALE = 38,
550 NPU_SET_DMA0_SRC = 48,
551 NPU_SET_DMA0_DST = 49,
552 NPU_SET_DMA0_LEN = 50,
553 NPU_SET_DMA0_SKIP0 = 51,
554 NPU_SET_DMA0_SKIP1 = 52,
555 NPU_SET_IFM2_BASE0 = 128,
556 NPU_SET_IFM2_BASE1 = 129,
557 NPU_SET_IFM2_BASE2 = 130,
558 NPU_SET_IFM2_BASE3 = 131,
559 NPU_SET_IFM2_STRIDE_X = 132,
560 NPU_SET_IFM2_STRIDE_Y = 133,
561 NPU_SET_IFM2_STRIDE_C = 134,
562 NPU_SET_WEIGHT1_BASE = 144,
563 NPU_SET_WEIGHT1_LENGTH = 145,
564 NPU_SET_SCALE1_BASE = 146,
565 NPU_SET_SCALE1_LENGTH = 147,
566};
567
568enum class cmd_ctrl : uint8_t
569{
570 CMD0_CTRL = 0,
571 CMD1_CTRL = 1,
572};
573
574enum class custom_dma : uint8_t
575{
576 NOT_IMPLEMENTED = 0,
577 IMPLEMENTED = 1,
578};
579
580enum class dma_fault_src : uint8_t
581{
582 AXI_M0 = 0,
583 AXI_M1 = 1,
584};
585
586enum class dma_region_mode : uint8_t
587{
588 EXTERNAL = 0,
589 INTERNAL = 1,
590};
591
592enum class dma_stride_mode : uint8_t
593{
594 D1 = 0,
595 D2 = 1,
596 D3 = 2,
597};
598
599enum class elementwise_mode : uint8_t
600{
601 MUL = 0,
602 ADD = 1,
603 SUB = 2,
604 MIN = 3,
605 MAX = 4,
606 LRELU = 5,
607 ABS = 6,
608 CLZ = 7,
609 SHR = 8,
610 SHL = 9,
611};
612
613enum class functional_safety : uint8_t
614{
615 NOT_IMPLEMENTED = 0,
616 IMPLEMENTED = 1,
617};
618
619enum class ifm2_operand_order : uint8_t
620{
621 ORDER_B = 0,
622 ORDER_A = 1,
623};
624
625enum class ifm_scale_mode : uint8_t
626{
627 OPA_OPB_16 = 0,
628 OPA_32 = 1,
629 OPB_32 = 2,
630};
631
632enum class ifm_upscale_mode : uint8_t
633{
634 NONE = 0,
635 NEAREST = 1,
636 ZEROS = 2,
637};
638
639enum class kernel_decomposition : uint8_t
640{
641 D8X8 = 0,
642 D4X4 = 1,
643};
644
645enum class kernel_dilation : uint8_t
646{
647 NONE = 0,
648 X2 = 1,
649};
650
651enum class max_beats : uint8_t
652{
653 B64 = 0,
654 B128 = 1,
655 B256 = 2,
656};
657
658enum class mem_attr : uint8_t
659{
660 AXI0_OUTSTANDING_COUNTER0 = 0,
661 AXI0_OUTSTANDING_COUNTER1 = 1,
662 AXI1_OUTSTANDING_COUNTER2 = 2,
663 AXI1_OUTSTANDING_COUNTER3 = 3,
664};
665
666enum class ofm_scale_mode : uint8_t
667{
668 PER_CHANNEL = 0,
669 GLOBAL = 1,
670};
671
672enum class parallel_mode : uint8_t
673{
674 SINGLE_CORE = 0,
675 DUAL_CORE_DEPTH = 1,
676};
677
678enum class pmu_axi_channel : uint8_t
679{
680 RD_CMD = 0,
681 RD_IFM = 1,
682 RD_WEIGHTS = 2,
683 RD_SCALE_BIAS = 3,
684 RD_MEM2MEM = 4,
685 WR_OFM = 8,
686 WR_MEM2MEM = 9,
687};
688
689enum class pmu_event : uint16_t
690{
691 NO_EVENT = 0,
692 CYCLE = 17,
693 NPU_IDLE = 32,
694 CC_STALLED_ON_BLOCKDEP = 33,
695 CC_STALLED_ON_SHRAM_RECONFIG = 34,
696 NPU_ACTIVE = 35,
697 MAC_ACTIVE = 48,
698 MAC_ACTIVE_8BIT = 49,
699 MAC_ACTIVE_16BIT = 50,
700 MAC_DPU_ACTIVE = 51,
701 MAC_STALLED_BY_WD_ACC = 52,
702 MAC_STALLED_BY_WD = 53,
703 MAC_STALLED_BY_ACC = 54,
704 MAC_STALLED_BY_IB = 55,
705 MAC_ACTIVE_32BIT = 56,
706 MAC_STALLED_BY_INT_W = 57,
707 MAC_STALLED_BY_INT_ACC = 58,
708 AO_ACTIVE = 64,
709 AO_ACTIVE_8BIT = 65,
710 AO_ACTIVE_16BIT = 66,
711 AO_STALLED_BY_OFMP_OB = 67,
712 AO_STALLED_BY_OFMP = 68,
713 AO_STALLED_BY_OB = 69,
714 AO_STALLED_BY_ACC_IB = 70,
715 AO_STALLED_BY_ACC = 71,
716 AO_STALLED_BY_IB = 72,
717 WD_ACTIVE = 80,
718 WD_STALLED = 81,
719 WD_STALLED_BY_WS = 82,
720 WD_STALLED_BY_WD_BUF = 83,
721 WD_PARSE_ACTIVE = 84,
722 WD_PARSE_STALLED = 85,
723 WD_PARSE_STALLED_IN = 86,
724 WD_PARSE_STALLED_OUT = 87,
725 WD_TRANS_WS = 88,
726 WD_TRANS_WB = 89,
727 WD_TRANS_DW0 = 90,
728 WD_TRANS_DW1 = 91,
729 AXI0_RD_TRANS_ACCEPTED = 128,
730 AXI0_RD_TRANS_COMPLETED = 129,
731 AXI0_RD_DATA_BEAT_RECEIVED = 130,
732 AXI0_RD_TRAN_REQ_STALLED = 131,
733 AXI0_WR_TRANS_ACCEPTED = 132,
734 AXI0_WR_TRANS_COMPLETED_M = 133,
735 AXI0_WR_TRANS_COMPLETED_S = 134,
736 AXI0_WR_DATA_BEAT_WRITTEN = 135,
737 AXI0_WR_TRAN_REQ_STALLED = 136,
738 AXI0_WR_DATA_BEAT_STALLED = 137,
739 AXI0_ENABLED_CYCLES = 140,
740 AXI0_RD_STALL_LIMIT = 142,
741 AXI0_WR_STALL_LIMIT = 143,
742 AXI_LATENCY_ANY = 160,
743 AXI_LATENCY_32 = 161,
744 AXI_LATENCY_64 = 162,
745 AXI_LATENCY_128 = 163,
746 AXI_LATENCY_256 = 164,
747 AXI_LATENCY_512 = 165,
748 AXI_LATENCY_1024 = 166,
749 ECC_DMA = 176,
750 ECC_SB0 = 177,
751 AXI1_RD_TRANS_ACCEPTED = 384,
752 AXI1_RD_TRANS_COMPLETED = 385,
753 AXI1_RD_DATA_BEAT_RECEIVED = 386,
754 AXI1_RD_TRAN_REQ_STALLED = 387,
755 AXI1_WR_TRANS_ACCEPTED = 388,
756 AXI1_WR_TRANS_COMPLETED_M = 389,
757 AXI1_WR_TRANS_COMPLETED_S = 390,
758 AXI1_WR_DATA_BEAT_WRITTEN = 391,
759 AXI1_WR_TRAN_REQ_STALLED = 392,
760 AXI1_WR_DATA_BEAT_STALLED = 393,
761 AXI1_ENABLED_CYCLES = 396,
762 AXI1_RD_STALL_LIMIT = 398,
763 AXI1_WR_STALL_LIMIT = 399,
764 ECC_SB1 = 433,
765};
766
767enum class pooling_mode : uint8_t
768{
769 MAX = 0,
770 AVERAGE = 1,
771 REDUCE_SUM = 2,
772};
773
774enum class privilege_level : uint8_t
775{
776 USER = 0,
777 PRIVILEGED = 1,
778};
779
780enum class round_mode : uint8_t
781{
782 DBL = 0,
783 TRUNCATE = 1,
784 NATURAL = 2,
785};
786
787enum class security_level : uint8_t
788{
789 SECURE = 0,
790 NON_SECURE = 1,
791};
792
793enum class state : uint8_t
794{
795 STOPPED = 0,
796 RUNNING = 1,
797};
798
799enum class wd_core_slice_state : uint8_t
800{
801 HEADER = 0,
802 PALETTE = 1,
803 WEIGHTS = 2,
804};
805
806enum class wd_ctrl_state : uint8_t
807{
808 IDLE = 0,
809 DRAIN = 1,
810 OFD_INIT = 2,
811 OFD_RUN = 3,
812};
813
814enum class weight_order : uint8_t
815{
816 DEPTH_FIRST = 0,
817 PART_KERNEL_FIRST = 1,
818};
819
820#else
821
828
836
842
857
865
871
887
893
895{
956};
957
959{
997};
998
1004
1010
1016
1022
1029
1043
1049
1055
1062
1069
1075
1081
1088
1096
1102
1108
1119
1121{
1196};
1197
1204
1210
1217
1223
1225{
1228};
1229
1236
1244
1250
1251#endif
1252
1253#ifdef NPU_DISASSEMBLE
1254
1255static const char *acc_format_str[] = {
1256 "ACC_FORMAT_I32",
1257 "ACC_FORMAT_I40",
1258 "ACC_FORMAT_F16",
1259};
1260
1261static const char *activation_clip_range_str[] = {
1262 "ACTIVATION_CLIP_RANGE_OFM_PRECISION",
1263 "****",
1264 "ACTIVATION_CLIP_RANGE_FORCE_UINT8",
1265 "ACTIVATION_CLIP_RANGE_FORCE_INT8",
1266 "****",
1267 "ACTIVATION_CLIP_RANGE_FORCE_INT16",
1268};
1269
1270static const char *activation_format_str[] = {
1271 "ACTIVATION_FORMAT_NHWC",
1272 "ACTIVATION_FORMAT_NHCWB16",
1273};
1274
1275static const char *activation_function_str[] = {
1276 "ACTIVATION_FUNCTION_RELU",
1277 "****",
1278 "****",
1279 "ACTIVATION_FUNCTION_TANH",
1280 "ACTIVATION_FUNCTION_SIGMOID",
1281 "****",
1282 "****",
1283 "****",
1284 "****",
1285 "****",
1286 "****",
1287 "****",
1288 "****",
1289 "****",
1290 "****",
1291 "****",
1292 "ACTIVATION_FUNCTION_TABLE_0",
1293 "ACTIVATION_FUNCTION_TABLE_1",
1294 "ACTIVATION_FUNCTION_TABLE_2",
1295 "ACTIVATION_FUNCTION_TABLE_3",
1296 "ACTIVATION_FUNCTION_TABLE_4",
1297 "ACTIVATION_FUNCTION_TABLE_5",
1298 "ACTIVATION_FUNCTION_TABLE_6",
1299 "ACTIVATION_FUNCTION_TABLE_7",
1300};
1301
1302static const char *activation_precision_str[] = {
1303 "ACTIVATION_PRECISION_B8",
1304 "ACTIVATION_PRECISION_B16",
1305 "ACTIVATION_PRECISION_B32",
1306 "ACTIVATION_PRECISION_B64",
1307};
1308
1309static const char *activation_type_str[] = {
1310 "ACTIVATION_TYPE_UNSIGNED",
1311 "ACTIVATION_TYPE_SIGNED",
1312};
1313
1314static const char *axi_mem_encoding_str[] = {
1315 "AXI_MEM_ENCODING_DEVICE_NON_BUFFERABLE",
1316 "AXI_MEM_ENCODING_DEVICE_BUFFERABLE",
1317 "AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_NON_BUFFERABLE",
1318 "AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_BUFFERABLE",
1319 "AXI_MEM_ENCODING_WRITE_THROUGH_NO_ALLOCATE",
1320 "AXI_MEM_ENCODING_WRITE_THROUGH_READ_ALLOCATE",
1321 "AXI_MEM_ENCODING_WRITE_THROUGH_WRITE_ALLOCATE",
1322 "AXI_MEM_ENCODING_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE",
1323 "AXI_MEM_ENCODING_WRITE_BACK_NO_ALLOCATE",
1324 "AXI_MEM_ENCODING_WRITE_BACK_READ_ALLOCATE",
1325 "AXI_MEM_ENCODING_WRITE_BACK_WRITE_ALLOCATE",
1326 "AXI_MEM_ENCODING_WRITE_BACK_READ_AND_WRITE_ALLOCATE",
1327};
1328
1329static const char *broadcast_mode_str[] = {
1330 "BROADCAST_MODE_DISABLE",
1331 "BROADCAST_MODE_ENABLE",
1332};
1333
1334static const char *cmd0_opcode_str[] = {
1335 "CMD0_OPCODE_NPU_OP_STOP",
1336 "CMD0_OPCODE_NPU_OP_IRQ",
1337 "CMD0_OPCODE_NPU_OP_CONV",
1338 "CMD0_OPCODE_NPU_OP_DEPTHWISE",
1339 "****",
1340 "CMD0_OPCODE_NPU_OP_POOL",
1341 "CMD0_OPCODE_NPU_OP_ELEMENTWISE",
1342 "****",
1343 "****",
1344 "****",
1345 "****",
1346 "****",
1347 "****",
1348 "****",
1349 "****",
1350 "****",
1351 "CMD0_OPCODE_NPU_OP_DMA_START",
1352 "CMD0_OPCODE_NPU_OP_DMA_WAIT",
1353 "CMD0_OPCODE_NPU_OP_KERNEL_WAIT",
1354 "CMD0_OPCODE_NPU_OP_PMU_MASK",
1355 "****",
1356 "****",
1357 "****",
1358 "****",
1359 "****",
1360 "****",
1361 "****",
1362 "****",
1363 "****",
1364 "****",
1365 "****",
1366 "****",
1367 "****",
1368 "****",
1369 "****",
1370 "****",
1371 "****",
1372 "****",
1373 "****",
1374 "****",
1375 "****",
1376 "****",
1377 "****",
1378 "****",
1379 "****",
1380 "****",
1381 "****",
1382 "****",
1383 "****",
1384 "****",
1385 "****",
1386 "****",
1387 "****",
1388 "****",
1389 "****",
1390 "****",
1391 "****",
1392 "****",
1393 "****",
1394 "****",
1395 "****",
1396 "****",
1397 "****",
1398 "****",
1399 "****",
1400 "****",
1401 "****",
1402 "****",
1403 "****",
1404 "****",
1405 "****",
1406 "****",
1407 "****",
1408 "****",
1409 "****",
1410 "****",
1411 "****",
1412 "****",
1413 "****",
1414 "****",
1415 "****",
1416 "****",
1417 "****",
1418 "****",
1419 "****",
1420 "****",
1421 "****",
1422 "****",
1423 "****",
1424 "****",
1425 "****",
1426 "****",
1427 "****",
1428 "****",
1429 "****",
1430 "****",
1431 "****",
1432 "****",
1433 "****",
1434 "****",
1435 "****",
1436 "****",
1437 "****",
1438 "****",
1439 "****",
1440 "****",
1441 "****",
1442 "****",
1443 "****",
1444 "****",
1445 "****",
1446 "****",
1447 "****",
1448 "****",
1449 "****",
1450 "****",
1451 "****",
1452 "****",
1453 "****",
1454 "****",
1455 "****",
1456 "****",
1457 "****",
1458 "****",
1459 "****",
1460 "****",
1461 "****",
1462 "****",
1463 "****",
1464 "****",
1465 "****",
1466 "****",
1467 "****",
1468 "****",
1469 "****",
1470 "****",
1471 "****",
1472 "****",
1473 "****",
1474 "****",
1475 "****",
1476 "****",
1477 "****",
1478 "****",
1479 "****",
1480 "****",
1481 "****",
1482 "****",
1483 "****",
1484 "****",
1485 "****",
1486 "****",
1487 "****",
1488 "****",
1489 "****",
1490 "****",
1491 "****",
1492 "****",
1493 "****",
1494 "****",
1495 "****",
1496 "****",
1497 "****",
1498 "****",
1499 "****",
1500 "****",
1501 "****",
1502 "****",
1503 "****",
1504 "****",
1505 "****",
1506 "****",
1507 "****",
1508 "****",
1509 "****",
1510 "****",
1511 "****",
1512 "****",
1513 "****",
1514 "****",
1515 "****",
1516 "****",
1517 "****",
1518 "****",
1519 "****",
1520 "****",
1521 "****",
1522 "****",
1523 "****",
1524 "****",
1525 "****",
1526 "****",
1527 "****",
1528 "****",
1529 "****",
1530 "****",
1531 "****",
1532 "****",
1533 "****",
1534 "****",
1535 "****",
1536 "****",
1537 "****",
1538 "****",
1539 "****",
1540 "****",
1541 "****",
1542 "****",
1543 "****",
1544 "****",
1545 "****",
1546 "****",
1547 "****",
1548 "****",
1549 "****",
1550 "****",
1551 "****",
1552 "****",
1553 "****",
1554 "****",
1555 "****",
1556 "****",
1557 "****",
1558 "****",
1559 "****",
1560 "****",
1561 "****",
1562 "****",
1563 "****",
1564 "****",
1565 "****",
1566 "****",
1567 "****",
1568 "****",
1569 "****",
1570 "****",
1571 "****",
1572 "****",
1573 "****",
1574 "****",
1575 "****",
1576 "****",
1577 "****",
1578 "****",
1579 "****",
1580 "****",
1581 "****",
1582 "****",
1583 "****",
1584 "****",
1585 "****",
1586 "****",
1587 "****",
1588 "****",
1589 "****",
1590 "****",
1591 "CMD0_OPCODE_NPU_SET_IFM_PAD_TOP",
1592 "CMD0_OPCODE_NPU_SET_IFM_PAD_LEFT",
1593 "CMD0_OPCODE_NPU_SET_IFM_PAD_RIGHT",
1594 "CMD0_OPCODE_NPU_SET_IFM_PAD_BOTTOM",
1595 "CMD0_OPCODE_NPU_SET_IFM_DEPTH_M1",
1596 "CMD0_OPCODE_NPU_SET_IFM_PRECISION",
1597 "****",
1598 "CMD0_OPCODE_NPU_SET_IFM_UPSCALE",
1599 "****",
1600 "CMD0_OPCODE_NPU_SET_IFM_ZERO_POINT",
1601 "CMD0_OPCODE_NPU_SET_IFM_WIDTH0_M1",
1602 "CMD0_OPCODE_NPU_SET_IFM_HEIGHT0_M1",
1603 "CMD0_OPCODE_NPU_SET_IFM_HEIGHT1_M1",
1604 "CMD0_OPCODE_NPU_SET_IFM_IB_END",
1605 "****",
1606 "CMD0_OPCODE_NPU_SET_IFM_REGION",
1607 "****",
1608 "CMD0_OPCODE_NPU_SET_OFM_WIDTH_M1",
1609 "CMD0_OPCODE_NPU_SET_OFM_HEIGHT_M1",
1610 "CMD0_OPCODE_NPU_SET_OFM_DEPTH_M1",
1611 "CMD0_OPCODE_NPU_SET_OFM_PRECISION",
1612 "CMD0_OPCODE_NPU_SET_OFM_BLK_WIDTH_M1",
1613 "CMD0_OPCODE_NPU_SET_OFM_BLK_HEIGHT_M1",
1614 "CMD0_OPCODE_NPU_SET_OFM_BLK_DEPTH_M1",
1615 "CMD0_OPCODE_NPU_SET_OFM_ZERO_POINT",
1616 "****",
1617 "CMD0_OPCODE_NPU_SET_OFM_WIDTH0_M1",
1618 "CMD0_OPCODE_NPU_SET_OFM_HEIGHT0_M1",
1619 "CMD0_OPCODE_NPU_SET_OFM_HEIGHT1_M1",
1620 "****",
1621 "****",
1622 "CMD0_OPCODE_NPU_SET_OFM_REGION",
1623 "CMD0_OPCODE_NPU_SET_KERNEL_WIDTH_M1",
1624 "CMD0_OPCODE_NPU_SET_KERNEL_HEIGHT_M1",
1625 "CMD0_OPCODE_NPU_SET_KERNEL_STRIDE",
1626 "CMD0_OPCODE_NPU_SET_PARALLEL_MODE",
1627 "CMD0_OPCODE_NPU_SET_ACC_FORMAT",
1628 "CMD0_OPCODE_NPU_SET_ACTIVATION",
1629 "CMD0_OPCODE_NPU_SET_ACTIVATION_MIN",
1630 "CMD0_OPCODE_NPU_SET_ACTIVATION_MAX",
1631 "CMD0_OPCODE_NPU_SET_WEIGHT_REGION",
1632 "CMD0_OPCODE_NPU_SET_SCALE_REGION",
1633 "****",
1634 "****",
1635 "****",
1636 "CMD0_OPCODE_NPU_SET_AB_START",
1637 "****",
1638 "CMD0_OPCODE_NPU_SET_BLOCKDEP",
1639 "CMD0_OPCODE_NPU_SET_DMA0_SRC_REGION",
1640 "CMD0_OPCODE_NPU_SET_DMA0_DST_REGION",
1641 "CMD0_OPCODE_NPU_SET_DMA0_SIZE0",
1642 "CMD0_OPCODE_NPU_SET_DMA0_SIZE1",
1643 "****",
1644 "****",
1645 "****",
1646 "****",
1647 "****",
1648 "****",
1649 "****",
1650 "****",
1651 "****",
1652 "****",
1653 "****",
1654 "****",
1655 "****",
1656 "****",
1657 "****",
1658 "****",
1659 "****",
1660 "****",
1661 "****",
1662 "****",
1663 "****",
1664 "****",
1665 "****",
1666 "****",
1667 "****",
1668 "****",
1669 "****",
1670 "****",
1671 "****",
1672 "****",
1673 "****",
1674 "****",
1675 "****",
1676 "****",
1677 "****",
1678 "****",
1679 "****",
1680 "****",
1681 "****",
1682 "****",
1683 "****",
1684 "****",
1685 "****",
1686 "****",
1687 "****",
1688 "****",
1689 "****",
1690 "****",
1691 "****",
1692 "****",
1693 "****",
1694 "****",
1695 "****",
1696 "****",
1697 "****",
1698 "****",
1699 "****",
1700 "****",
1701 "****",
1702 "****",
1703 "****",
1704 "****",
1705 "****",
1706 "****",
1707 "****",
1708 "****",
1709 "****",
1710 "****",
1711 "****",
1712 "****",
1713 "****",
1714 "****",
1715 "****",
1716 "****",
1717 "****",
1718 "****",
1719 "CMD0_OPCODE_NPU_SET_IFM2_BROADCAST",
1720 "CMD0_OPCODE_NPU_SET_IFM2_SCALAR",
1721 "****",
1722 "****",
1723 "****",
1724 "CMD0_OPCODE_NPU_SET_IFM2_PRECISION",
1725 "****",
1726 "****",
1727 "****",
1728 "CMD0_OPCODE_NPU_SET_IFM2_ZERO_POINT",
1729 "CMD0_OPCODE_NPU_SET_IFM2_WIDTH0_M1",
1730 "CMD0_OPCODE_NPU_SET_IFM2_HEIGHT0_M1",
1731 "CMD0_OPCODE_NPU_SET_IFM2_HEIGHT1_M1",
1732 "CMD0_OPCODE_NPU_SET_IFM2_IB_START",
1733 "****",
1734 "CMD0_OPCODE_NPU_SET_IFM2_REGION",
1735};
1736
1737static const char *cmd1_opcode_str[] = {
1738 "CMD1_OPCODE_NPU_SET_IFM_BASE0",
1739 "CMD1_OPCODE_NPU_SET_IFM_BASE1",
1740 "CMD1_OPCODE_NPU_SET_IFM_BASE2",
1741 "CMD1_OPCODE_NPU_SET_IFM_BASE3",
1742 "CMD1_OPCODE_NPU_SET_IFM_STRIDE_X",
1743 "CMD1_OPCODE_NPU_SET_IFM_STRIDE_Y",
1744 "CMD1_OPCODE_NPU_SET_IFM_STRIDE_C",
1745 "****",
1746 "****",
1747 "****",
1748 "****",
1749 "****",
1750 "****",
1751 "****",
1752 "****",
1753 "****",
1754 "CMD1_OPCODE_NPU_SET_OFM_BASE0",
1755 "CMD1_OPCODE_NPU_SET_OFM_BASE1",
1756 "CMD1_OPCODE_NPU_SET_OFM_BASE2",
1757 "CMD1_OPCODE_NPU_SET_OFM_BASE3",
1758 "CMD1_OPCODE_NPU_SET_OFM_STRIDE_X",
1759 "CMD1_OPCODE_NPU_SET_OFM_STRIDE_Y",
1760 "CMD1_OPCODE_NPU_SET_OFM_STRIDE_C",
1761 "****",
1762 "****",
1763 "****",
1764 "****",
1765 "****",
1766 "****",
1767 "****",
1768 "****",
1769 "****",
1770 "CMD1_OPCODE_NPU_SET_WEIGHT_BASE",
1771 "CMD1_OPCODE_NPU_SET_WEIGHT_LENGTH",
1772 "CMD1_OPCODE_NPU_SET_SCALE_BASE",
1773 "CMD1_OPCODE_NPU_SET_SCALE_LENGTH",
1774 "CMD1_OPCODE_NPU_SET_OFM_SCALE",
1775 "CMD1_OPCODE_NPU_SET_OPA_SCALE",
1776 "CMD1_OPCODE_NPU_SET_OPB_SCALE",
1777 "****",
1778 "****",
1779 "****",
1780 "****",
1781 "****",
1782 "****",
1783 "****",
1784 "****",
1785 "****",
1786 "CMD1_OPCODE_NPU_SET_DMA0_SRC",
1787 "CMD1_OPCODE_NPU_SET_DMA0_DST",
1788 "CMD1_OPCODE_NPU_SET_DMA0_LEN",
1789 "CMD1_OPCODE_NPU_SET_DMA0_SKIP0",
1790 "CMD1_OPCODE_NPU_SET_DMA0_SKIP1",
1791 "****",
1792 "****",
1793 "****",
1794 "****",
1795 "****",
1796 "****",
1797 "****",
1798 "****",
1799 "****",
1800 "****",
1801 "****",
1802 "****",
1803 "****",
1804 "****",
1805 "****",
1806 "****",
1807 "****",
1808 "****",
1809 "****",
1810 "****",
1811 "****",
1812 "****",
1813 "****",
1814 "****",
1815 "****",
1816 "****",
1817 "****",
1818 "****",
1819 "****",
1820 "****",
1821 "****",
1822 "****",
1823 "****",
1824 "****",
1825 "****",
1826 "****",
1827 "****",
1828 "****",
1829 "****",
1830 "****",
1831 "****",
1832 "****",
1833 "****",
1834 "****",
1835 "****",
1836 "****",
1837 "****",
1838 "****",
1839 "****",
1840 "****",
1841 "****",
1842 "****",
1843 "****",
1844 "****",
1845 "****",
1846 "****",
1847 "****",
1848 "****",
1849 "****",
1850 "****",
1851 "****",
1852 "****",
1853 "****",
1854 "****",
1855 "****",
1856 "****",
1857 "****",
1858 "****",
1859 "****",
1860 "****",
1861 "****",
1862 "****",
1863 "****",
1864 "****",
1865 "****",
1866 "CMD1_OPCODE_NPU_SET_IFM2_BASE0",
1867 "CMD1_OPCODE_NPU_SET_IFM2_BASE1",
1868 "CMD1_OPCODE_NPU_SET_IFM2_BASE2",
1869 "CMD1_OPCODE_NPU_SET_IFM2_BASE3",
1870 "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_X",
1871 "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_Y",
1872 "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_C",
1873 "****",
1874 "****",
1875 "****",
1876 "****",
1877 "****",
1878 "****",
1879 "****",
1880 "****",
1881 "****",
1882 "CMD1_OPCODE_NPU_SET_WEIGHT1_BASE",
1883 "CMD1_OPCODE_NPU_SET_WEIGHT1_LENGTH",
1884 "CMD1_OPCODE_NPU_SET_SCALE1_BASE",
1885 "CMD1_OPCODE_NPU_SET_SCALE1_LENGTH",
1886};
1887
1888static const char *cmd_ctrl_str[] = {
1889 "CMD_CTRL_CMD0_CTRL",
1890 "CMD_CTRL_CMD1_CTRL",
1891};
1892
1893static const char *custom_dma_str[] = {
1894 "CUSTOM_DMA_NOT_IMPLEMENTED",
1895 "CUSTOM_DMA_IMPLEMENTED",
1896};
1897
1898static const char *dma_fault_src_str[] = {
1899 "DMA_FAULT_SRC_AXI_M0",
1900 "DMA_FAULT_SRC_AXI_M1",
1901};
1902
1903static const char *dma_region_mode_str[] = {
1904 "DMA_REGION_MODE_EXTERNAL",
1905 "DMA_REGION_MODE_INTERNAL",
1906};
1907
1908static const char *dma_stride_mode_str[] = {
1909 "DMA_STRIDE_MODE_D1",
1910 "DMA_STRIDE_MODE_D2",
1911 "DMA_STRIDE_MODE_D3",
1912};
1913
1914static const char *elementwise_mode_str[] = {
1915 "ELEMENTWISE_MODE_MUL",
1916 "ELEMENTWISE_MODE_ADD",
1917 "ELEMENTWISE_MODE_SUB",
1918 "ELEMENTWISE_MODE_MIN",
1919 "ELEMENTWISE_MODE_MAX",
1920 "ELEMENTWISE_MODE_LRELU",
1921 "ELEMENTWISE_MODE_ABS",
1922 "ELEMENTWISE_MODE_CLZ",
1923 "ELEMENTWISE_MODE_SHR",
1924 "ELEMENTWISE_MODE_SHL",
1925};
1926
1927static const char *functional_safety_str[] = {
1928 "FUNCTIONAL_SAFETY_NOT_IMPLEMENTED",
1929 "FUNCTIONAL_SAFETY_IMPLEMENTED",
1930};
1931
1932static const char *ifm2_operand_order_str[] = {
1933 "IFM2_OPERAND_ORDER_ORDER_B",
1934 "IFM2_OPERAND_ORDER_ORDER_A",
1935};
1936
1937static const char *ifm_scale_mode_str[] = {
1938 "IFM_SCALE_MODE_OPA_OPB_16",
1939 "IFM_SCALE_MODE_OPA_32",
1940 "IFM_SCALE_MODE_OPB_32",
1941};
1942
1943static const char *ifm_upscale_mode_str[] = {
1944 "IFM_UPSCALE_MODE_NONE",
1945 "IFM_UPSCALE_MODE_NEAREST",
1946 "IFM_UPSCALE_MODE_ZEROS",
1947};
1948
1949static const char *kernel_decomposition_str[] = {
1950 "KERNEL_DECOMPOSITION_D8X8",
1951 "KERNEL_DECOMPOSITION_D4X4",
1952};
1953
1954static const char *kernel_dilation_str[] = {
1955 "KERNEL_DILATION_NONE",
1956 "KERNEL_DILATION_X2",
1957};
1958
1959static const char *max_beats_str[] = {
1960 "MAX_BEATS_B64",
1961 "MAX_BEATS_B128",
1962 "MAX_BEATS_B256",
1963};
1964
1965static const char *mem_attr_str[] = {
1966 "MEM_ATTR_AXI0_OUTSTANDING_COUNTER0",
1967 "MEM_ATTR_AXI0_OUTSTANDING_COUNTER1",
1968 "MEM_ATTR_AXI1_OUTSTANDING_COUNTER2",
1969 "MEM_ATTR_AXI1_OUTSTANDING_COUNTER3",
1970};
1971
1972static const char *ofm_scale_mode_str[] = {
1973 "OFM_SCALE_MODE_PER_CHANNEL",
1974 "OFM_SCALE_MODE_GLOBAL",
1975};
1976
1977static const char *parallel_mode_str[] = {
1978 "PARALLEL_MODE_SINGLE_CORE",
1979 "PARALLEL_MODE_DUAL_CORE_DEPTH",
1980};
1981
1982static const char *pmu_axi_channel_str[] = {
1983 "PMU_AXI_CHANNEL_RD_CMD",
1984 "PMU_AXI_CHANNEL_RD_IFM",
1985 "PMU_AXI_CHANNEL_RD_WEIGHTS",
1986 "PMU_AXI_CHANNEL_RD_SCALE_BIAS",
1987 "PMU_AXI_CHANNEL_RD_MEM2MEM",
1988 "****",
1989 "****",
1990 "****",
1991 "PMU_AXI_CHANNEL_WR_OFM",
1992 "PMU_AXI_CHANNEL_WR_MEM2MEM",
1993};
1994
1995static const char *pmu_event_str[] = {
1996 "PMU_EVENT_NO_EVENT",
1997 "****",
1998 "****",
1999 "****",
2000 "****",
2001 "****",
2002 "****",
2003 "****",
2004 "****",
2005 "****",
2006 "****",
2007 "****",
2008 "****",
2009 "****",
2010 "****",
2011 "****",
2012 "****",
2013 "PMU_EVENT_CYCLE",
2014 "****",
2015 "****",
2016 "****",
2017 "****",
2018 "****",
2019 "****",
2020 "****",
2021 "****",
2022 "****",
2023 "****",
2024 "****",
2025 "****",
2026 "****",
2027 "****",
2028 "PMU_EVENT_NPU_IDLE",
2029 "PMU_EVENT_CC_STALLED_ON_BLOCKDEP",
2030 "PMU_EVENT_CC_STALLED_ON_SHRAM_RECONFIG",
2031 "PMU_EVENT_NPU_ACTIVE",
2032 "****",
2033 "****",
2034 "****",
2035 "****",
2036 "****",
2037 "****",
2038 "****",
2039 "****",
2040 "****",
2041 "****",
2042 "****",
2043 "****",
2044 "PMU_EVENT_MAC_ACTIVE",
2045 "PMU_EVENT_MAC_ACTIVE_8BIT",
2046 "PMU_EVENT_MAC_ACTIVE_16BIT",
2047 "PMU_EVENT_MAC_DPU_ACTIVE",
2048 "PMU_EVENT_MAC_STALLED_BY_WD_ACC",
2049 "PMU_EVENT_MAC_STALLED_BY_WD",
2050 "PMU_EVENT_MAC_STALLED_BY_ACC",
2051 "PMU_EVENT_MAC_STALLED_BY_IB",
2052 "PMU_EVENT_MAC_ACTIVE_32BIT",
2053 "PMU_EVENT_MAC_STALLED_BY_INT_W",
2054 "PMU_EVENT_MAC_STALLED_BY_INT_ACC",
2055 "****",
2056 "****",
2057 "****",
2058 "****",
2059 "****",
2060 "PMU_EVENT_AO_ACTIVE",
2061 "PMU_EVENT_AO_ACTIVE_8BIT",
2062 "PMU_EVENT_AO_ACTIVE_16BIT",
2063 "PMU_EVENT_AO_STALLED_BY_OFMP_OB",
2064 "PMU_EVENT_AO_STALLED_BY_OFMP",
2065 "PMU_EVENT_AO_STALLED_BY_OB",
2066 "PMU_EVENT_AO_STALLED_BY_ACC_IB",
2067 "PMU_EVENT_AO_STALLED_BY_ACC",
2068 "PMU_EVENT_AO_STALLED_BY_IB",
2069 "****",
2070 "****",
2071 "****",
2072 "****",
2073 "****",
2074 "****",
2075 "****",
2076 "PMU_EVENT_WD_ACTIVE",
2077 "PMU_EVENT_WD_STALLED",
2078 "PMU_EVENT_WD_STALLED_BY_WS",
2079 "PMU_EVENT_WD_STALLED_BY_WD_BUF",
2080 "PMU_EVENT_WD_PARSE_ACTIVE",
2081 "PMU_EVENT_WD_PARSE_STALLED",
2082 "PMU_EVENT_WD_PARSE_STALLED_IN",
2083 "PMU_EVENT_WD_PARSE_STALLED_OUT",
2084 "PMU_EVENT_WD_TRANS_WS",
2085 "PMU_EVENT_WD_TRANS_WB",
2086 "PMU_EVENT_WD_TRANS_DW0",
2087 "PMU_EVENT_WD_TRANS_DW1",
2088 "****",
2089 "****",
2090 "****",
2091 "****",
2092 "****",
2093 "****",
2094 "****",
2095 "****",
2096 "****",
2097 "****",
2098 "****",
2099 "****",
2100 "****",
2101 "****",
2102 "****",
2103 "****",
2104 "****",
2105 "****",
2106 "****",
2107 "****",
2108 "****",
2109 "****",
2110 "****",
2111 "****",
2112 "****",
2113 "****",
2114 "****",
2115 "****",
2116 "****",
2117 "****",
2118 "****",
2119 "****",
2120 "****",
2121 "****",
2122 "****",
2123 "****",
2124 "PMU_EVENT_AXI0_RD_TRANS_ACCEPTED",
2125 "PMU_EVENT_AXI0_RD_TRANS_COMPLETED",
2126 "PMU_EVENT_AXI0_RD_DATA_BEAT_RECEIVED",
2127 "PMU_EVENT_AXI0_RD_TRAN_REQ_STALLED",
2128 "PMU_EVENT_AXI0_WR_TRANS_ACCEPTED",
2129 "PMU_EVENT_AXI0_WR_TRANS_COMPLETED_M",
2130 "PMU_EVENT_AXI0_WR_TRANS_COMPLETED_S",
2131 "PMU_EVENT_AXI0_WR_DATA_BEAT_WRITTEN",
2132 "PMU_EVENT_AXI0_WR_TRAN_REQ_STALLED",
2133 "PMU_EVENT_AXI0_WR_DATA_BEAT_STALLED",
2134 "****",
2135 "****",
2136 "PMU_EVENT_AXI0_ENABLED_CYCLES",
2137 "****",
2138 "PMU_EVENT_AXI0_RD_STALL_LIMIT",
2139 "PMU_EVENT_AXI0_WR_STALL_LIMIT",
2140 "****",
2141 "****",
2142 "****",
2143 "****",
2144 "****",
2145 "****",
2146 "****",
2147 "****",
2148 "****",
2149 "****",
2150 "****",
2151 "****",
2152 "****",
2153 "****",
2154 "****",
2155 "****",
2156 "PMU_EVENT_AXI_LATENCY_ANY",
2157 "PMU_EVENT_AXI_LATENCY_32",
2158 "PMU_EVENT_AXI_LATENCY_64",
2159 "PMU_EVENT_AXI_LATENCY_128",
2160 "PMU_EVENT_AXI_LATENCY_256",
2161 "PMU_EVENT_AXI_LATENCY_512",
2162 "PMU_EVENT_AXI_LATENCY_1024",
2163 "****",
2164 "****",
2165 "****",
2166 "****",
2167 "****",
2168 "****",
2169 "****",
2170 "****",
2171 "****",
2172 "PMU_EVENT_ECC_DMA",
2173 "PMU_EVENT_ECC_SB0",
2174 "****",
2175 "****",
2176 "****",
2177 "****",
2178 "****",
2179 "****",
2180 "****",
2181 "****",
2182 "****",
2183 "****",
2184 "****",
2185 "****",
2186 "****",
2187 "****",
2188 "****",
2189 "****",
2190 "****",
2191 "****",
2192 "****",
2193 "****",
2194 "****",
2195 "****",
2196 "****",
2197 "****",
2198 "****",
2199 "****",
2200 "****",
2201 "****",
2202 "****",
2203 "****",
2204 "****",
2205 "****",
2206 "****",
2207 "****",
2208 "****",
2209 "****",
2210 "****",
2211 "****",
2212 "****",
2213 "****",
2214 "****",
2215 "****",
2216 "****",
2217 "****",
2218 "****",
2219 "****",
2220 "****",
2221 "****",
2222 "****",
2223 "****",
2224 "****",
2225 "****",
2226 "****",
2227 "****",
2228 "****",
2229 "****",
2230 "****",
2231 "****",
2232 "****",
2233 "****",
2234 "****",
2235 "****",
2236 "****",
2237 "****",
2238 "****",
2239 "****",
2240 "****",
2241 "****",
2242 "****",
2243 "****",
2244 "****",
2245 "****",
2246 "****",
2247 "****",
2248 "****",
2249 "****",
2250 "****",
2251 "****",
2252 "****",
2253 "****",
2254 "****",
2255 "****",
2256 "****",
2257 "****",
2258 "****",
2259 "****",
2260 "****",
2261 "****",
2262 "****",
2263 "****",
2264 "****",
2265 "****",
2266 "****",
2267 "****",
2268 "****",
2269 "****",
2270 "****",
2271 "****",
2272 "****",
2273 "****",
2274 "****",
2275 "****",
2276 "****",
2277 "****",
2278 "****",
2279 "****",
2280 "****",
2281 "****",
2282 "****",
2283 "****",
2284 "****",
2285 "****",
2286 "****",
2287 "****",
2288 "****",
2289 "****",
2290 "****",
2291 "****",
2292 "****",
2293 "****",
2294 "****",
2295 "****",
2296 "****",
2297 "****",
2298 "****",
2299 "****",
2300 "****",
2301 "****",
2302 "****",
2303 "****",
2304 "****",
2305 "****",
2306 "****",
2307 "****",
2308 "****",
2309 "****",
2310 "****",
2311 "****",
2312 "****",
2313 "****",
2314 "****",
2315 "****",
2316 "****",
2317 "****",
2318 "****",
2319 "****",
2320 "****",
2321 "****",
2322 "****",
2323 "****",
2324 "****",
2325 "****",
2326 "****",
2327 "****",
2328 "****",
2329 "****",
2330 "****",
2331 "****",
2332 "****",
2333 "****",
2334 "****",
2335 "****",
2336 "****",
2337 "****",
2338 "****",
2339 "****",
2340 "****",
2341 "****",
2342 "****",
2343 "****",
2344 "****",
2345 "****",
2346 "****",
2347 "****",
2348 "****",
2349 "****",
2350 "****",
2351 "****",
2352 "****",
2353 "****",
2354 "****",
2355 "****",
2356 "****",
2357 "****",
2358 "****",
2359 "****",
2360 "****",
2361 "****",
2362 "****",
2363 "****",
2364 "****",
2365 "****",
2366 "****",
2367 "****",
2368 "****",
2369 "****",
2370 "****",
2371 "****",
2372 "****",
2373 "****",
2374 "****",
2375 "****",
2376 "****",
2377 "****",
2378 "****",
2379 "****",
2380 "PMU_EVENT_AXI1_RD_TRANS_ACCEPTED",
2381 "PMU_EVENT_AXI1_RD_TRANS_COMPLETED",
2382 "PMU_EVENT_AXI1_RD_DATA_BEAT_RECEIVED",
2383 "PMU_EVENT_AXI1_RD_TRAN_REQ_STALLED",
2384 "PMU_EVENT_AXI1_WR_TRANS_ACCEPTED",
2385 "PMU_EVENT_AXI1_WR_TRANS_COMPLETED_M",
2386 "PMU_EVENT_AXI1_WR_TRANS_COMPLETED_S",
2387 "PMU_EVENT_AXI1_WR_DATA_BEAT_WRITTEN",
2388 "PMU_EVENT_AXI1_WR_TRAN_REQ_STALLED",
2389 "PMU_EVENT_AXI1_WR_DATA_BEAT_STALLED",
2390 "****",
2391 "****",
2392 "PMU_EVENT_AXI1_ENABLED_CYCLES",
2393 "****",
2394 "PMU_EVENT_AXI1_RD_STALL_LIMIT",
2395 "PMU_EVENT_AXI1_WR_STALL_LIMIT",
2396 "****",
2397 "****",
2398 "****",
2399 "****",
2400 "****",
2401 "****",
2402 "****",
2403 "****",
2404 "****",
2405 "****",
2406 "****",
2407 "****",
2408 "****",
2409 "****",
2410 "****",
2411 "****",
2412 "****",
2413 "****",
2414 "****",
2415 "****",
2416 "****",
2417 "****",
2418 "****",
2419 "****",
2420 "****",
2421 "****",
2422 "****",
2423 "****",
2424 "****",
2425 "****",
2426 "****",
2427 "****",
2428 "****",
2429 "PMU_EVENT_ECC_SB1",
2430};
2431
2432static const char *pooling_mode_str[] = {
2433 "POOLING_MODE_MAX",
2434 "POOLING_MODE_AVERAGE",
2435 "POOLING_MODE_REDUCE_SUM",
2436};
2437
2438static const char *privilege_level_str[] = {
2439 "PRIVILEGE_LEVEL_USER",
2440 "PRIVILEGE_LEVEL_PRIVILEGED",
2441};
2442
2443static const char *round_mode_str[] = {
2444 "ROUND_MODE_DBL",
2445 "ROUND_MODE_TRUNCATE",
2446 "ROUND_MODE_NATURAL",
2447};
2448
2449static const char *security_level_str[] = {
2450 "SECURITY_LEVEL_SECURE",
2451 "SECURITY_LEVEL_NON_SECURE",
2452};
2453
2454static const char *state_str[] = {
2455 "STATE_STOPPED",
2456 "STATE_RUNNING",
2457};
2458
2459static const char *wd_core_slice_state_str[] = {
2460 "WD_CORE_SLICE_STATE_HEADER",
2461 "WD_CORE_SLICE_STATE_PALETTE",
2462 "WD_CORE_SLICE_STATE_WEIGHTS",
2463};
2464
2465static const char *wd_ctrl_state_str[] = {
2466 "WD_CTRL_STATE_IDLE",
2467 "WD_CTRL_STATE_DRAIN",
2468 "WD_CTRL_STATE_OFD_INIT",
2469 "WD_CTRL_STATE_OFD_RUN",
2470};
2471
2472static const char *weight_order_str[] = {
2473 "WEIGHT_ORDER_DEPTH_FIRST",
2474 "WEIGHT_ORDER_PART_KERNEL_FIRST",
2475};
2476
2477#endif
2478
2479// Register type structs
2480// id_r - ID register
2481struct id_r
2482{
2483#ifndef __cplusplus
2484 union
2485 {
2486 struct
2487 {
2488 uint32_t version_status : 4; // This is the version of the product
2489 uint32_t version_minor : 4; // This is the n for the P part of an RnPn release number
2490 uint32_t version_major : 4; // This is the n for the R part of an RnPn release number
2491 uint32_t product_major : 4; // Product major ID number (unique per base product)
2492 uint32_t arch_patch_rev : 4; // This is the patch number of the architecture version a.b
2493 uint32_t
2494 arch_minor_rev : 8; // This is the minor architecture version number, b in the architecture version a.b
2495 uint32_t
2496 arch_major_rev : 4; // This is the major architecture version number, a in the architecture version a.b
2497 };
2498 uint32_t word;
2499 };
2500#else
2501 private:
2502 uint32_t word0;
2503
2504 public:
2505 CONSTEXPR id_r() : word0(268853249) {}
2506 CONSTEXPR id_r(uint32_t init) : word0(init) {}
2507 CONSTEXPR void operator=(uint32_t value)
2508 {
2509 word0 = value;
2510 }
2511 void operator=(uint32_t value) volatile
2512 {
2513 word0 = value;
2514 }
2515 CONSTEXPR operator uint32_t()
2516 {
2517 return word0;
2518 }
2519 operator uint32_t() volatile
2520 {
2521 return word0;
2522 }
2523 id_r copy() volatile
2524 {
2525 return *this;
2526 }
2527 CONSTEXPR uint32_t get_version_status() const
2528 {
2529 uint32_t value = ((1U << 4) - 1) & (word0 >> 0);
2530 return value;
2531 }
2532 uint32_t get_version_status() const volatile
2533 {
2534 uint32_t value = ((1U << 4) - 1) & (word0 >> 0);
2535 return value;
2536 }
2537 CONSTEXPR id_r &set_version_status(uint32_t value)
2538 {
2539 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0);
2540 return *this;
2541 }
2542 volatile id_r &set_version_status(uint32_t value) volatile
2543 {
2544 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0);
2545 return *this;
2546 }
2547 CONSTEXPR uint32_t get_version_minor() const
2548 {
2549 uint32_t value = ((1U << 4) - 1) & (word0 >> 4);
2550 return value;
2551 }
2552 uint32_t get_version_minor() const volatile
2553 {
2554 uint32_t value = ((1U << 4) - 1) & (word0 >> 4);
2555 return value;
2556 }
2557 CONSTEXPR id_r &set_version_minor(uint32_t value)
2558 {
2559 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4);
2560 return *this;
2561 }
2562 volatile id_r &set_version_minor(uint32_t value) volatile
2563 {
2564 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4);
2565 return *this;
2566 }
2567 CONSTEXPR uint32_t get_version_major() const
2568 {
2569 uint32_t value = ((1U << 4) - 1) & (word0 >> 8);
2570 return value;
2571 }
2572 uint32_t get_version_major() const volatile
2573 {
2574 uint32_t value = ((1U << 4) - 1) & (word0 >> 8);
2575 return value;
2576 }
2577 CONSTEXPR id_r &set_version_major(uint32_t value)
2578 {
2579 word0 = (((~((1U << 4) - 1)) << 8) & word0) | ((((1U << 4) - 1) & value) << 8);
2580 return *this;
2581 }
2582 volatile id_r &set_version_major(uint32_t value) volatile
2583 {
2584 word0 = (((~((1U << 4) - 1)) << 8) & word0) | ((((1U << 4) - 1) & value) << 8);
2585 return *this;
2586 }
2587 CONSTEXPR uint32_t get_product_major() const
2588 {
2589 uint32_t value = ((1U << 4) - 1) & (word0 >> 12);
2590 return value;
2591 }
2592 uint32_t get_product_major() const volatile
2593 {
2594 uint32_t value = ((1U << 4) - 1) & (word0 >> 12);
2595 return value;
2596 }
2597 CONSTEXPR id_r &set_product_major(uint32_t value)
2598 {
2599 word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12);
2600 return *this;
2601 }
2602 volatile id_r &set_product_major(uint32_t value) volatile
2603 {
2604 word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12);
2605 return *this;
2606 }
2607 CONSTEXPR uint32_t get_arch_patch_rev() const
2608 {
2609 uint32_t value = ((1U << 4) - 1) & (word0 >> 16);
2610 return value;
2611 }
2612 uint32_t get_arch_patch_rev() const volatile
2613 {
2614 uint32_t value = ((1U << 4) - 1) & (word0 >> 16);
2615 return value;
2616 }
2617 CONSTEXPR id_r &set_arch_patch_rev(uint32_t value)
2618 {
2619 word0 = (((~((1U << 4) - 1)) << 16) & word0) | ((((1U << 4) - 1) & value) << 16);
2620 return *this;
2621 }
2622 volatile id_r &set_arch_patch_rev(uint32_t value) volatile
2623 {
2624 word0 = (((~((1U << 4) - 1)) << 16) & word0) | ((((1U << 4) - 1) & value) << 16);
2625 return *this;
2626 }
2627 CONSTEXPR uint32_t get_arch_minor_rev() const
2628 {
2629 uint32_t value = ((1U << 8) - 1) & (word0 >> 20);
2630 return value;
2631 }
2632 uint32_t get_arch_minor_rev() const volatile
2633 {
2634 uint32_t value = ((1U << 8) - 1) & (word0 >> 20);
2635 return value;
2636 }
2637 CONSTEXPR id_r &set_arch_minor_rev(uint32_t value)
2638 {
2639 word0 = (((~((1U << 8) - 1)) << 20) & word0) | ((((1U << 8) - 1) & value) << 20);
2640 return *this;
2641 }
2642 volatile id_r &set_arch_minor_rev(uint32_t value) volatile
2643 {
2644 word0 = (((~((1U << 8) - 1)) << 20) & word0) | ((((1U << 8) - 1) & value) << 20);
2645 return *this;
2646 }
2647 CONSTEXPR uint32_t get_arch_major_rev() const
2648 {
2649 uint32_t value = ((1U << 4) - 1) & (word0 >> 28);
2650 return value;
2651 }
2652 uint32_t get_arch_major_rev() const volatile
2653 {
2654 uint32_t value = ((1U << 4) - 1) & (word0 >> 28);
2655 return value;
2656 }
2657 CONSTEXPR id_r &set_arch_major_rev(uint32_t value)
2658 {
2659 word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28);
2660 return *this;
2661 }
2662 volatile id_r &set_arch_major_rev(uint32_t value) volatile
2663 {
2664 word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28);
2665 return *this;
2666 }
2667#endif
2668};
2669
2670// status_r - Register describes the current operating status of the NPU
2671struct status_r
2672{
2673#ifndef __cplusplus
2674 union
2675 {
2676 struct
2677 {
2678 uint32_t state : 1; // NPU state, 0 = Stopped, 1 = Running
2679 uint32_t irq_raised : 1; // Raw IRQ status, 0 = IRQ not raised, 1 = IRQ raised. IRQ is cleared using command
2680 // register bit 1
2681 uint32_t
2682 bus_status : 1; // 0=OK, 1=Bus abort detected and processing halted (NPU will reach IDLE state and not
2683 // to start process any more commands/AXI transactions). Can only be cleared by a reset
2684 uint32_t reset_status : 1; // Reset is ongoing and only this register can be read (other registers read as 0
2685 // and writes are ignored.) A value of 0 means NPU is not being reset and can be
2686 // accessed as normal
2687 uint32_t
2688 cmd_parse_error : 1; // 0=No error 1=Command stream parsing error detected. Can only be cleared by reset
2689 uint32_t cmd_end_reached : 1; // 0=Not reached, 1=Reached. Cleared by writing QBASE or QSIZE when NPU is in
2690 // stopped state
2691 uint32_t pmu_irq_raised : 1; // 0=No PMU IRQ, 1=PMU IRQ raised. Cleared by using command register bit 1
2692 uint32_t wd_fault : 1; // Weight decoder state: 0=no fault 1=weight decoder decompression fault. Can only be
2693 // cleared by reset
2694 uint32_t ecc_fault : 1; // ECC state for internal RAMs: 0=no fault 1=ECC fault signalled. Can only be
2695 // cleared by reset
2696 uint32_t reserved0 : 2;
2697 uint32_t faulting_interface : 1; // Faulting interface on bus abort
2698 uint32_t faulting_channel : 4; // Faulting channel on a bus abort. Read: 0=Cmd 1=IFM 2=Weights 3=Scale+Bias
2699 // 4=Mem2Mem; Write: 8=OFM 9=Mem2Mem
2700 uint32_t irq_history_mask : 16; // IRQ History mask
2701 };
2702 uint32_t word;
2703 };
2704#else
2705 private:
2706 uint32_t word0;
2707
2708 public:
2709 CONSTEXPR status_r() : word0(8) {}
2710 CONSTEXPR status_r(uint32_t init) : word0(init) {}
2711 CONSTEXPR void operator=(uint32_t value)
2712 {
2713 word0 = value;
2714 }
2715 void operator=(uint32_t value) volatile
2716 {
2717 word0 = value;
2718 }
2719 CONSTEXPR operator uint32_t()
2720 {
2721 return word0;
2722 }
2723 operator uint32_t() volatile
2724 {
2725 return word0;
2726 }
2727 status_r copy() volatile
2728 {
2729 return *this;
2730 }
2731 CONSTEXPR NPU_NAMESPACE::state get_state() const
2732 {
2733 NPU_NAMESPACE::state value = static_cast<NPU_NAMESPACE::state>(((1U << 1) - 1) & (word0 >> 0));
2734 return value;
2735 }
2736 NPU_NAMESPACE::state get_state() const volatile
2737 {
2738 NPU_NAMESPACE::state value = static_cast<NPU_NAMESPACE::state>(((1U << 1) - 1) & (word0 >> 0));
2739 return value;
2740 }
2741 CONSTEXPR status_r &set_state(NPU_NAMESPACE::state value)
2742 {
2743 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
2744 return *this;
2745 }
2746 volatile status_r &set_state(NPU_NAMESPACE::state value) volatile
2747 {
2748 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
2749 return *this;
2750 }
2751 CONSTEXPR uint32_t get_irq_raised() const
2752 {
2753 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
2754 return value;
2755 }
2756 uint32_t get_irq_raised() const volatile
2757 {
2758 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
2759 return value;
2760 }
2761 CONSTEXPR status_r &set_irq_raised(uint32_t value)
2762 {
2763 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
2764 return *this;
2765 }
2766 volatile status_r &set_irq_raised(uint32_t value) volatile
2767 {
2768 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
2769 return *this;
2770 }
2771 CONSTEXPR uint32_t get_bus_status() const
2772 {
2773 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
2774 return value;
2775 }
2776 uint32_t get_bus_status() const volatile
2777 {
2778 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
2779 return value;
2780 }
2781 CONSTEXPR status_r &set_bus_status(uint32_t value)
2782 {
2783 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
2784 return *this;
2785 }
2786 volatile status_r &set_bus_status(uint32_t value) volatile
2787 {
2788 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
2789 return *this;
2790 }
2791 CONSTEXPR uint32_t get_reset_status() const
2792 {
2793 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
2794 return value;
2795 }
2796 uint32_t get_reset_status() const volatile
2797 {
2798 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
2799 return value;
2800 }
2801 CONSTEXPR status_r &set_reset_status(uint32_t value)
2802 {
2803 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
2804 return *this;
2805 }
2806 volatile status_r &set_reset_status(uint32_t value) volatile
2807 {
2808 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
2809 return *this;
2810 }
2811 CONSTEXPR uint32_t get_cmd_parse_error() const
2812 {
2813 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
2814 return value;
2815 }
2816 uint32_t get_cmd_parse_error() const volatile
2817 {
2818 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
2819 return value;
2820 }
2821 CONSTEXPR status_r &set_cmd_parse_error(uint32_t value)
2822 {
2823 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
2824 return *this;
2825 }
2826 volatile status_r &set_cmd_parse_error(uint32_t value) volatile
2827 {
2828 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
2829 return *this;
2830 }
2831 CONSTEXPR uint32_t get_cmd_end_reached() const
2832 {
2833 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
2834 return value;
2835 }
2836 uint32_t get_cmd_end_reached() const volatile
2837 {
2838 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
2839 return value;
2840 }
2841 CONSTEXPR status_r &set_cmd_end_reached(uint32_t value)
2842 {
2843 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
2844 return *this;
2845 }
2846 volatile status_r &set_cmd_end_reached(uint32_t value) volatile
2847 {
2848 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
2849 return *this;
2850 }
2851 CONSTEXPR uint32_t get_pmu_irq_raised() const
2852 {
2853 uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
2854 return value;
2855 }
2856 uint32_t get_pmu_irq_raised() const volatile
2857 {
2858 uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
2859 return value;
2860 }
2861 CONSTEXPR status_r &set_pmu_irq_raised(uint32_t value)
2862 {
2863 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
2864 return *this;
2865 }
2866 volatile status_r &set_pmu_irq_raised(uint32_t value) volatile
2867 {
2868 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
2869 return *this;
2870 }
2871 CONSTEXPR uint32_t get_wd_fault() const
2872 {
2873 uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
2874 return value;
2875 }
2876 uint32_t get_wd_fault() const volatile
2877 {
2878 uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
2879 return value;
2880 }
2881 CONSTEXPR status_r &set_wd_fault(uint32_t value)
2882 {
2883 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
2884 return *this;
2885 }
2886 volatile status_r &set_wd_fault(uint32_t value) volatile
2887 {
2888 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
2889 return *this;
2890 }
2891 CONSTEXPR uint32_t get_ecc_fault() const
2892 {
2893 uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
2894 return value;
2895 }
2896 uint32_t get_ecc_fault() const volatile
2897 {
2898 uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
2899 return value;
2900 }
2901 CONSTEXPR status_r &set_ecc_fault(uint32_t value)
2902 {
2903 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
2904 return *this;
2905 }
2906 volatile status_r &set_ecc_fault(uint32_t value) volatile
2907 {
2908 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
2909 return *this;
2910 }
2911 CONSTEXPR NPU_NAMESPACE::dma_fault_src get_faulting_interface() const
2912 {
2913 NPU_NAMESPACE::dma_fault_src value = static_cast<NPU_NAMESPACE::dma_fault_src>(((1U << 1) - 1) & (word0 >> 11));
2914 return value;
2915 }
2916 NPU_NAMESPACE::dma_fault_src get_faulting_interface() const volatile
2917 {
2918 NPU_NAMESPACE::dma_fault_src value = static_cast<NPU_NAMESPACE::dma_fault_src>(((1U << 1) - 1) & (word0 >> 11));
2919 return value;
2920 }
2921 CONSTEXPR status_r &set_faulting_interface(NPU_NAMESPACE::dma_fault_src value)
2922 {
2923 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 11);
2924 return *this;
2925 }
2926 volatile status_r &set_faulting_interface(NPU_NAMESPACE::dma_fault_src value) volatile
2927 {
2928 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 11);
2929 return *this;
2930 }
2931 CONSTEXPR uint32_t get_faulting_channel() const
2932 {
2933 uint32_t value = ((1U << 4) - 1) & (word0 >> 12);
2934 return value;
2935 }
2936 uint32_t get_faulting_channel() const volatile
2937 {
2938 uint32_t value = ((1U << 4) - 1) & (word0 >> 12);
2939 return value;
2940 }
2941 CONSTEXPR status_r &set_faulting_channel(uint32_t value)
2942 {
2943 word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12);
2944 return *this;
2945 }
2946 volatile status_r &set_faulting_channel(uint32_t value) volatile
2947 {
2948 word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) & value) << 12);
2949 return *this;
2950 }
2951 CONSTEXPR uint32_t get_irq_history_mask() const
2952 {
2953 uint32_t value = ((1U << 16) - 1) & (word0 >> 16);
2954 return value;
2955 }
2956 uint32_t get_irq_history_mask() const volatile
2957 {
2958 uint32_t value = ((1U << 16) - 1) & (word0 >> 16);
2959 return value;
2960 }
2961 CONSTEXPR status_r &set_irq_history_mask(uint32_t value)
2962 {
2963 word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16);
2964 return *this;
2965 }
2966 volatile status_r &set_irq_history_mask(uint32_t value) volatile
2967 {
2968 word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16);
2969 return *this;
2970 }
2971#endif
2972};
2973
2974// cmd_r - Command register, reads as last written command
2975struct cmd_r
2976{
2977#ifndef __cplusplus
2978 union
2979 {
2980 struct
2981 {
2982 uint32_t transition_to_running_state : 1; // Write 1 to transition the NPU to running state. Writing 0 has
2983 // no effect
2984 uint32_t clear_irq : 1; // Write 1 to clear the IRQ status in the STATUS register. Writing 0 has no effect
2985 uint32_t clock_q_enable : 1; // Write 1 to this bit to enable clock off using clock q-interface and enable
2986 // the requester clock gate
2987 uint32_t power_q_enable : 1; // Write 1 to this bit to enable power off using power q-interface
2988 uint32_t
2989 stop_request : 1; // Write 1 to this bit to request STOP after completing any already-started commands
2990 uint32_t reserved0 : 11;
2991 uint32_t clear_irq_history : 16; // Clears the IRQ history mask
2992 };
2993 uint32_t word;
2994 };
2995#else
2996 private:
2997 uint32_t word0;
2998
2999 public:
3000 CONSTEXPR cmd_r() : word0(12) {}
3001 CONSTEXPR cmd_r(uint32_t init) : word0(init) {}
3002 CONSTEXPR void operator=(uint32_t value)
3003 {
3004 word0 = value;
3005 }
3006 void operator=(uint32_t value) volatile
3007 {
3008 word0 = value;
3009 }
3010 CONSTEXPR operator uint32_t()
3011 {
3012 return word0;
3013 }
3014 operator uint32_t() volatile
3015 {
3016 return word0;
3017 }
3018 cmd_r copy() volatile
3019 {
3020 return *this;
3021 }
3022 CONSTEXPR uint32_t get_transition_to_running_state() const
3023 {
3024 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
3025 return value;
3026 }
3027 uint32_t get_transition_to_running_state() const volatile
3028 {
3029 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
3030 return value;
3031 }
3032 CONSTEXPR cmd_r &set_transition_to_running_state(uint32_t value)
3033 {
3034 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
3035 return *this;
3036 }
3037 volatile cmd_r &set_transition_to_running_state(uint32_t value) volatile
3038 {
3039 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
3040 return *this;
3041 }
3042 CONSTEXPR uint32_t get_clear_irq() const
3043 {
3044 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
3045 return value;
3046 }
3047 uint32_t get_clear_irq() const volatile
3048 {
3049 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
3050 return value;
3051 }
3052 CONSTEXPR cmd_r &set_clear_irq(uint32_t value)
3053 {
3054 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
3055 return *this;
3056 }
3057 volatile cmd_r &set_clear_irq(uint32_t value) volatile
3058 {
3059 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
3060 return *this;
3061 }
3062 CONSTEXPR uint32_t get_clock_q_enable() const
3063 {
3064 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
3065 return value;
3066 }
3067 uint32_t get_clock_q_enable() const volatile
3068 {
3069 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
3070 return value;
3071 }
3072 CONSTEXPR cmd_r &set_clock_q_enable(uint32_t value)
3073 {
3074 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
3075 return *this;
3076 }
3077 volatile cmd_r &set_clock_q_enable(uint32_t value) volatile
3078 {
3079 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
3080 return *this;
3081 }
3082 CONSTEXPR uint32_t get_power_q_enable() const
3083 {
3084 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
3085 return value;
3086 }
3087 uint32_t get_power_q_enable() const volatile
3088 {
3089 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
3090 return value;
3091 }
3092 CONSTEXPR cmd_r &set_power_q_enable(uint32_t value)
3093 {
3094 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
3095 return *this;
3096 }
3097 volatile cmd_r &set_power_q_enable(uint32_t value) volatile
3098 {
3099 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
3100 return *this;
3101 }
3102 CONSTEXPR uint32_t get_stop_request() const
3103 {
3104 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
3105 return value;
3106 }
3107 uint32_t get_stop_request() const volatile
3108 {
3109 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
3110 return value;
3111 }
3112 CONSTEXPR cmd_r &set_stop_request(uint32_t value)
3113 {
3114 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
3115 return *this;
3116 }
3117 volatile cmd_r &set_stop_request(uint32_t value) volatile
3118 {
3119 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
3120 return *this;
3121 }
3122 CONSTEXPR uint32_t get_clear_irq_history() const
3123 {
3124 uint32_t value = ((1U << 16) - 1) & (word0 >> 16);
3125 return value;
3126 }
3127 uint32_t get_clear_irq_history() const volatile
3128 {
3129 uint32_t value = ((1U << 16) - 1) & (word0 >> 16);
3130 return value;
3131 }
3132 CONSTEXPR cmd_r &set_clear_irq_history(uint32_t value)
3133 {
3134 word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16);
3135 return *this;
3136 }
3137 volatile cmd_r &set_clear_irq_history(uint32_t value) volatile
3138 {
3139 word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) & value) << 16);
3140 return *this;
3141 }
3142#endif
3143};
3144
3145// reset_r - Request Reset and new security mode
3146struct reset_r
3147{
3148#ifndef __cplusplus
3149 union
3150 {
3151 struct
3152 {
3153 uint32_t pending_CPL : 1; // Current privilege level 0=User 1=Privileged
3154 uint32_t pending_CSL : 1; // Current security level 0=Secure 1=Non secure
3155 uint32_t reserved0 : 30;
3156 };
3157 uint32_t word;
3158 };
3159#else
3160 private:
3161 uint32_t word0;
3162
3163 public:
3164 CONSTEXPR reset_r() : word0(0) {}
3165 CONSTEXPR reset_r(uint32_t init) : word0(init) {}
3166 CONSTEXPR void operator=(uint32_t value)
3167 {
3168 word0 = value;
3169 }
3170 void operator=(uint32_t value) volatile
3171 {
3172 word0 = value;
3173 }
3174 CONSTEXPR operator uint32_t()
3175 {
3176 return word0;
3177 }
3178 operator uint32_t() volatile
3179 {
3180 return word0;
3181 }
3182 reset_r copy() volatile
3183 {
3184 return *this;
3185 }
3186 CONSTEXPR NPU_NAMESPACE::privilege_level get_pending_CPL() const
3187 {
3188 NPU_NAMESPACE::privilege_level value =
3189 static_cast<NPU_NAMESPACE::privilege_level>(((1U << 1) - 1) & (word0 >> 0));
3190 return value;
3191 }
3192 NPU_NAMESPACE::privilege_level get_pending_CPL() const volatile
3193 {
3194 NPU_NAMESPACE::privilege_level value =
3195 static_cast<NPU_NAMESPACE::privilege_level>(((1U << 1) - 1) & (word0 >> 0));
3196 return value;
3197 }
3198 CONSTEXPR reset_r &set_pending_CPL(NPU_NAMESPACE::privilege_level value)
3199 {
3200 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
3201 return *this;
3202 }
3203 volatile reset_r &set_pending_CPL(NPU_NAMESPACE::privilege_level value) volatile
3204 {
3205 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
3206 return *this;
3207 }
3208 CONSTEXPR NPU_NAMESPACE::security_level get_pending_CSL() const
3209 {
3210 NPU_NAMESPACE::security_level value =
3211 static_cast<NPU_NAMESPACE::security_level>(((1U << 1) - 1) & (word0 >> 1));
3212 return value;
3213 }
3214 NPU_NAMESPACE::security_level get_pending_CSL() const volatile
3215 {
3216 NPU_NAMESPACE::security_level value =
3217 static_cast<NPU_NAMESPACE::security_level>(((1U << 1) - 1) & (word0 >> 1));
3218 return value;
3219 }
3220 CONSTEXPR reset_r &set_pending_CSL(NPU_NAMESPACE::security_level value)
3221 {
3222 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 1);
3223 return *this;
3224 }
3225 volatile reset_r &set_pending_CSL(NPU_NAMESPACE::security_level value) volatile
3226 {
3227 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 1);
3228 return *this;
3229 }
3230#endif
3231};
3232
3233// qbase_r - Base address of the command stream in bytes
3234struct qbase_r
3235{
3236#ifndef __cplusplus
3237 union
3238 {
3239 struct
3240 {
3241 uint32_t offset_LO : 32; // Offset - LSB
3242 uint32_t offset_HI : 8; // Offset - MSB
3243 uint32_t reserved0 : 24;
3244 };
3245 uint32_t word[2];
3246 };
3247#else
3248 private:
3249 uint32_t word0;
3250 uint32_t word1;
3251
3252 public:
3253 CONSTEXPR qbase_r() : word0(0), word1(0) {}
3254 CONSTEXPR qbase_r(uint64_t init) :
3255 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
3256 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
3257 {
3258 }
3259 CONSTEXPR void operator=(uint64_t value)
3260 {
3261 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
3262 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
3263 }
3264 void operator=(uint64_t value) volatile
3265 {
3266 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
3267 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
3268 }
3269 CONSTEXPR operator uint64_t()
3270 {
3271 return (static_cast<uint64_t>(word1) << 32) | word0;
3272 }
3273 operator uint64_t() volatile
3274 {
3275 return (static_cast<uint64_t>(word1) << 32) | word0;
3276 }
3277 qbase_r copy() volatile
3278 {
3279 return *this;
3280 }
3281#endif
3282};
3283
3284// qread_r - Read offset in the command stream in bytes. Multiple of 4 in the range 0 to 16 MB
3285struct qread_r
3286{
3287#ifndef __cplusplus
3288 union
3289 {
3290 struct
3291 {
3292 uint32_t QREAD : 32; // The read offset of the current command under execution
3293 };
3294 uint32_t word;
3295 };
3296#else
3297 private:
3298 uint32_t word0;
3299
3300 public:
3301 CONSTEXPR qread_r() : word0(0) {}
3302 CONSTEXPR qread_r(uint32_t init) : word0(init) {}
3303 CONSTEXPR void operator=(uint32_t value)
3304 {
3305 word0 = value;
3306 }
3307 void operator=(uint32_t value) volatile
3308 {
3309 word0 = value;
3310 }
3311 CONSTEXPR operator uint32_t()
3312 {
3313 return word0;
3314 }
3315 operator uint32_t() volatile
3316 {
3317 return word0;
3318 }
3319 qread_r copy() volatile
3320 {
3321 return *this;
3322 }
3323 CONSTEXPR uint32_t get_QREAD() const
3324 {
3325 uint32_t value = word0;
3326 return value;
3327 }
3328 uint32_t get_QREAD() const volatile
3329 {
3330 uint32_t value = word0;
3331 return value;
3332 }
3333 CONSTEXPR qread_r &set_QREAD(uint32_t value)
3334 {
3335 word0 = value;
3336 return *this;
3337 }
3338 volatile qread_r &set_QREAD(uint32_t value) volatile
3339 {
3340 word0 = value;
3341 return *this;
3342 }
3343#endif
3344};
3345
3346// qconfig_r - AXI configuration for the command stream in the range 0-3. Same encoding as for REGIONCFG
3347struct qconfig_r
3348{
3349#ifndef __cplusplus
3350 union
3351 {
3352 struct
3353 {
3354 uint32_t cmd_region0 : 2; // Command region configuration
3355 uint32_t reserved0 : 30;
3356 };
3357 uint32_t word;
3358 };
3359#else
3360 private:
3361 uint32_t word0;
3362
3363 public:
3364 CONSTEXPR qconfig_r() : word0(0) {}
3365 CONSTEXPR qconfig_r(uint32_t init) : word0(init) {}
3366 CONSTEXPR void operator=(uint32_t value)
3367 {
3368 word0 = value;
3369 }
3370 void operator=(uint32_t value) volatile
3371 {
3372 word0 = value;
3373 }
3374 CONSTEXPR operator uint32_t()
3375 {
3376 return word0;
3377 }
3378 operator uint32_t() volatile
3379 {
3380 return word0;
3381 }
3382 qconfig_r copy() volatile
3383 {
3384 return *this;
3385 }
3386 CONSTEXPR NPU_NAMESPACE::mem_attr get_cmd_region0() const
3387 {
3388 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 0));
3389 return value;
3390 }
3391 NPU_NAMESPACE::mem_attr get_cmd_region0() const volatile
3392 {
3393 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 0));
3394 return value;
3395 }
3396 CONSTEXPR qconfig_r &set_cmd_region0(NPU_NAMESPACE::mem_attr value)
3397 {
3398 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
3399 return *this;
3400 }
3401 volatile qconfig_r &set_cmd_region0(NPU_NAMESPACE::mem_attr value) volatile
3402 {
3403 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
3404 return *this;
3405 }
3406#endif
3407};
3408
3409// qsize_r - Size of the command stream in bytes. Multiple of 4 in the range 0 to 16 MB
3410struct qsize_r
3411{
3412#ifndef __cplusplus
3413 union
3414 {
3415 struct
3416 {
3417 uint32_t QSIZE : 32; // Size of the next command stream to be executed by the NPU
3418 };
3419 uint32_t word;
3420 };
3421#else
3422 private:
3423 uint32_t word0;
3424
3425 public:
3426 CONSTEXPR qsize_r() : word0(0) {}
3427 CONSTEXPR qsize_r(uint32_t init) : word0(init) {}
3428 CONSTEXPR void operator=(uint32_t value)
3429 {
3430 word0 = value;
3431 }
3432 void operator=(uint32_t value) volatile
3433 {
3434 word0 = value;
3435 }
3436 CONSTEXPR operator uint32_t()
3437 {
3438 return word0;
3439 }
3440 operator uint32_t() volatile
3441 {
3442 return word0;
3443 }
3444 qsize_r copy() volatile
3445 {
3446 return *this;
3447 }
3448 CONSTEXPR uint32_t get_QSIZE() const
3449 {
3450 uint32_t value = word0;
3451 return value;
3452 }
3453 uint32_t get_QSIZE() const volatile
3454 {
3455 uint32_t value = word0;
3456 return value;
3457 }
3458 CONSTEXPR qsize_r &set_QSIZE(uint32_t value)
3459 {
3460 word0 = value;
3461 return *this;
3462 }
3463 volatile qsize_r &set_QSIZE(uint32_t value) volatile
3464 {
3465 word0 = value;
3466 return *this;
3467 }
3468#endif
3469};
3470
3471// prot_r - Protection level configured for the NPU when acting as an AXI requester
3472struct prot_r
3473{
3474#ifndef __cplusplus
3475 union
3476 {
3477 struct
3478 {
3479 uint32_t active_CPL : 1; // Current privilege level 0=User 1=Privileged
3480 uint32_t active_CSL : 1; // Current security level 0=Secure 1=Non secure
3481 uint32_t reserved0 : 30;
3482 };
3483 uint32_t word;
3484 };
3485#else
3486 private:
3487 uint32_t word0;
3488
3489 public:
3490 CONSTEXPR prot_r() : word0(0) {}
3491 CONSTEXPR prot_r(uint32_t init) : word0(init) {}
3492 CONSTEXPR void operator=(uint32_t value)
3493 {
3494 word0 = value;
3495 }
3496 void operator=(uint32_t value) volatile
3497 {
3498 word0 = value;
3499 }
3500 CONSTEXPR operator uint32_t()
3501 {
3502 return word0;
3503 }
3504 operator uint32_t() volatile
3505 {
3506 return word0;
3507 }
3508 prot_r copy() volatile
3509 {
3510 return *this;
3511 }
3512 CONSTEXPR NPU_NAMESPACE::privilege_level get_active_CPL() const
3513 {
3514 NPU_NAMESPACE::privilege_level value =
3515 static_cast<NPU_NAMESPACE::privilege_level>(((1U << 1) - 1) & (word0 >> 0));
3516 return value;
3517 }
3518 NPU_NAMESPACE::privilege_level get_active_CPL() const volatile
3519 {
3520 NPU_NAMESPACE::privilege_level value =
3521 static_cast<NPU_NAMESPACE::privilege_level>(((1U << 1) - 1) & (word0 >> 0));
3522 return value;
3523 }
3524 CONSTEXPR prot_r &set_active_CPL(NPU_NAMESPACE::privilege_level value)
3525 {
3526 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
3527 return *this;
3528 }
3529 volatile prot_r &set_active_CPL(NPU_NAMESPACE::privilege_level value) volatile
3530 {
3531 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 0);
3532 return *this;
3533 }
3534 CONSTEXPR NPU_NAMESPACE::security_level get_active_CSL() const
3535 {
3536 NPU_NAMESPACE::security_level value =
3537 static_cast<NPU_NAMESPACE::security_level>(((1U << 1) - 1) & (word0 >> 1));
3538 return value;
3539 }
3540 NPU_NAMESPACE::security_level get_active_CSL() const volatile
3541 {
3542 NPU_NAMESPACE::security_level value =
3543 static_cast<NPU_NAMESPACE::security_level>(((1U << 1) - 1) & (word0 >> 1));
3544 return value;
3545 }
3546 CONSTEXPR prot_r &set_active_CSL(NPU_NAMESPACE::security_level value)
3547 {
3548 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 1);
3549 return *this;
3550 }
3551 volatile prot_r &set_active_CSL(NPU_NAMESPACE::security_level value) volatile
3552 {
3553 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 1);
3554 return *this;
3555 }
3556#endif
3557};
3558
3559// config_r - RTL configuration
3560struct config_r
3561{
3562#ifndef __cplusplus
3563 union
3564 {
3565 struct
3566 {
3567 uint32_t macs_per_cc : 4; // The log2(macs/clock cycle)
3568 uint32_t cmd_stream_version : 4; // command stream version accepted by this NPU
3569 uint32_t shram_size : 8; // Total size in KB of internal SHRAM
3570 uint32_t reserved0 : 10;
3571 uint32_t functional_safety : 1; // Functional safety configuration
3572 uint32_t custom_dma : 1; // Custom DMA configuration
3573 uint32_t product : 4; // Product configuration
3574 };
3575 uint32_t word;
3576 };
3577#else
3578 private:
3579 uint32_t word0;
3580
3581 public:
3582 CONSTEXPR config_r() : word0(268435456) {}
3583 CONSTEXPR config_r(uint32_t init) : word0(init) {}
3584 CONSTEXPR void operator=(uint32_t value)
3585 {
3586 word0 = value;
3587 }
3588 void operator=(uint32_t value) volatile
3589 {
3590 word0 = value;
3591 }
3592 CONSTEXPR operator uint32_t()
3593 {
3594 return word0;
3595 }
3596 operator uint32_t() volatile
3597 {
3598 return word0;
3599 }
3600 config_r copy() volatile
3601 {
3602 return *this;
3603 }
3604 CONSTEXPR uint32_t get_macs_per_cc() const
3605 {
3606 uint32_t value = ((1U << 4) - 1) & (word0 >> 0);
3607 return value;
3608 }
3609 uint32_t get_macs_per_cc() const volatile
3610 {
3611 uint32_t value = ((1U << 4) - 1) & (word0 >> 0);
3612 return value;
3613 }
3614 CONSTEXPR config_r &set_macs_per_cc(uint32_t value)
3615 {
3616 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0);
3617 return *this;
3618 }
3619 volatile config_r &set_macs_per_cc(uint32_t value) volatile
3620 {
3621 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & value) << 0);
3622 return *this;
3623 }
3624 CONSTEXPR uint32_t get_cmd_stream_version() const
3625 {
3626 uint32_t value = ((1U << 4) - 1) & (word0 >> 4);
3627 return value;
3628 }
3629 uint32_t get_cmd_stream_version() const volatile
3630 {
3631 uint32_t value = ((1U << 4) - 1) & (word0 >> 4);
3632 return value;
3633 }
3634 CONSTEXPR config_r &set_cmd_stream_version(uint32_t value)
3635 {
3636 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4);
3637 return *this;
3638 }
3639 volatile config_r &set_cmd_stream_version(uint32_t value) volatile
3640 {
3641 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & value) << 4);
3642 return *this;
3643 }
3644 CONSTEXPR uint32_t get_shram_size() const
3645 {
3646 uint32_t value = ((1U << 8) - 1) & (word0 >> 8);
3647 return value;
3648 }
3649 uint32_t get_shram_size() const volatile
3650 {
3651 uint32_t value = ((1U << 8) - 1) & (word0 >> 8);
3652 return value;
3653 }
3654 CONSTEXPR config_r &set_shram_size(uint32_t value)
3655 {
3656 word0 = (((~((1U << 8) - 1)) << 8) & word0) | ((((1U << 8) - 1) & value) << 8);
3657 return *this;
3658 }
3659 volatile config_r &set_shram_size(uint32_t value) volatile
3660 {
3661 word0 = (((~((1U << 8) - 1)) << 8) & word0) | ((((1U << 8) - 1) & value) << 8);
3662 return *this;
3663 }
3664 CONSTEXPR NPU_NAMESPACE::functional_safety get_functional_safety() const
3665 {
3666 NPU_NAMESPACE::functional_safety value =
3667 static_cast<NPU_NAMESPACE::functional_safety>(((1U << 1) - 1) & (word0 >> 26));
3668 return value;
3669 }
3670 NPU_NAMESPACE::functional_safety get_functional_safety() const volatile
3671 {
3672 NPU_NAMESPACE::functional_safety value =
3673 static_cast<NPU_NAMESPACE::functional_safety>(((1U << 1) - 1) & (word0 >> 26));
3674 return value;
3675 }
3676 CONSTEXPR config_r &set_functional_safety(NPU_NAMESPACE::functional_safety value)
3677 {
3678 word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 26);
3679 return *this;
3680 }
3681 volatile config_r &set_functional_safety(NPU_NAMESPACE::functional_safety value) volatile
3682 {
3683 word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 26);
3684 return *this;
3685 }
3686 CONSTEXPR NPU_NAMESPACE::custom_dma get_custom_dma() const
3687 {
3688 NPU_NAMESPACE::custom_dma value = static_cast<NPU_NAMESPACE::custom_dma>(((1U << 1) - 1) & (word0 >> 27));
3689 return value;
3690 }
3691 NPU_NAMESPACE::custom_dma get_custom_dma() const volatile
3692 {
3693 NPU_NAMESPACE::custom_dma value = static_cast<NPU_NAMESPACE::custom_dma>(((1U << 1) - 1) & (word0 >> 27));
3694 return value;
3695 }
3696 CONSTEXPR config_r &set_custom_dma(NPU_NAMESPACE::custom_dma value)
3697 {
3698 word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 27);
3699 return *this;
3700 }
3701 volatile config_r &set_custom_dma(NPU_NAMESPACE::custom_dma value) volatile
3702 {
3703 word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & static_cast<uint32_t>(value)) << 27);
3704 return *this;
3705 }
3706 CONSTEXPR uint32_t get_product() const
3707 {
3708 uint32_t value = ((1U << 4) - 1) & (word0 >> 28);
3709 return value;
3710 }
3711 uint32_t get_product() const volatile
3712 {
3713 uint32_t value = ((1U << 4) - 1) & (word0 >> 28);
3714 return value;
3715 }
3716 CONSTEXPR config_r &set_product(uint32_t value)
3717 {
3718 word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28);
3719 return *this;
3720 }
3721 volatile config_r &set_product(uint32_t value) volatile
3722 {
3723 word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) & value) << 28);
3724 return *this;
3725 }
3726#endif
3727};
3728
3729// lock_r - Lock register. This register is designed for driver use and does not affect NPU functionality
3730struct lock_r
3731{
3732#ifndef __cplusplus
3733 union
3734 {
3735 struct
3736 {
3737 uint32_t LOCK : 32; // 32 bit value for LOCK configuration
3738 };
3739 uint32_t word;
3740 };
3741#else
3742 private:
3743 uint32_t word0;
3744
3745 public:
3746 CONSTEXPR lock_r() : word0(0) {}
3747 CONSTEXPR lock_r(uint32_t init) : word0(init) {}
3748 CONSTEXPR void operator=(uint32_t value)
3749 {
3750 word0 = value;
3751 }
3752 void operator=(uint32_t value) volatile
3753 {
3754 word0 = value;
3755 }
3756 CONSTEXPR operator uint32_t()
3757 {
3758 return word0;
3759 }
3760 operator uint32_t() volatile
3761 {
3762 return word0;
3763 }
3764 lock_r copy() volatile
3765 {
3766 return *this;
3767 }
3768 CONSTEXPR uint32_t get_LOCK() const
3769 {
3770 uint32_t value = word0;
3771 return value;
3772 }
3773 uint32_t get_LOCK() const volatile
3774 {
3775 uint32_t value = word0;
3776 return value;
3777 }
3778 CONSTEXPR lock_r &set_LOCK(uint32_t value)
3779 {
3780 word0 = value;
3781 return *this;
3782 }
3783 volatile lock_r &set_LOCK(uint32_t value) volatile
3784 {
3785 word0 = value;
3786 return *this;
3787 }
3788#endif
3789};
3790
3791// regioncfg_r - Region memory type configuration. Bits[2*k+1:2*k] give the memory type for REGION[k]
3792struct regioncfg_r
3793{
3794#ifndef __cplusplus
3795 union
3796 {
3797 struct
3798 {
3799 uint32_t region0 : 2; // Bits for Region0 Configuration
3800 uint32_t region1 : 2; // Bits for Region1 Configuration
3801 uint32_t region2 : 2; // Bits for Region2 Configuration
3802 uint32_t region3 : 2; // Bits for Region3 Configuration
3803 uint32_t region4 : 2; // Bits for Region4 Configuration
3804 uint32_t region5 : 2; // Bits for Region5 Configuration
3805 uint32_t region6 : 2; // Bits for Region6 Configuration
3806 uint32_t region7 : 2; // Bits for Region7 Configuration
3807 uint32_t reserved0 : 16;
3808 };
3809 uint32_t word;
3810 };
3811#else
3812 private:
3813 uint32_t word0;
3814
3815 public:
3816 CONSTEXPR regioncfg_r() : word0(0) {}
3817 CONSTEXPR regioncfg_r(uint32_t init) : word0(init) {}
3818 CONSTEXPR void operator=(uint32_t value)
3819 {
3820 word0 = value;
3821 }
3822 void operator=(uint32_t value) volatile
3823 {
3824 word0 = value;
3825 }
3826 CONSTEXPR operator uint32_t()
3827 {
3828 return word0;
3829 }
3830 operator uint32_t() volatile
3831 {
3832 return word0;
3833 }
3834 regioncfg_r copy() volatile
3835 {
3836 return *this;
3837 }
3838 CONSTEXPR NPU_NAMESPACE::mem_attr get_region0() const
3839 {
3840 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 0));
3841 return value;
3842 }
3843 NPU_NAMESPACE::mem_attr get_region0() const volatile
3844 {
3845 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 0));
3846 return value;
3847 }
3848 CONSTEXPR regioncfg_r &set_region0(NPU_NAMESPACE::mem_attr value)
3849 {
3850 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
3851 return *this;
3852 }
3853 volatile regioncfg_r &set_region0(NPU_NAMESPACE::mem_attr value) volatile
3854 {
3855 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
3856 return *this;
3857 }
3858 CONSTEXPR NPU_NAMESPACE::mem_attr get_region1() const
3859 {
3860 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 2));
3861 return value;
3862 }
3863 NPU_NAMESPACE::mem_attr get_region1() const volatile
3864 {
3865 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 2));
3866 return value;
3867 }
3868 CONSTEXPR regioncfg_r &set_region1(NPU_NAMESPACE::mem_attr value)
3869 {
3870 word0 = (((~((1U << 2) - 1)) << 2) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 2);
3871 return *this;
3872 }
3873 volatile regioncfg_r &set_region1(NPU_NAMESPACE::mem_attr value) volatile
3874 {
3875 word0 = (((~((1U << 2) - 1)) << 2) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 2);
3876 return *this;
3877 }
3878 CONSTEXPR NPU_NAMESPACE::mem_attr get_region2() const
3879 {
3880 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 4));
3881 return value;
3882 }
3883 NPU_NAMESPACE::mem_attr get_region2() const volatile
3884 {
3885 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 4));
3886 return value;
3887 }
3888 CONSTEXPR regioncfg_r &set_region2(NPU_NAMESPACE::mem_attr value)
3889 {
3890 word0 = (((~((1U << 2) - 1)) << 4) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 4);
3891 return *this;
3892 }
3893 volatile regioncfg_r &set_region2(NPU_NAMESPACE::mem_attr value) volatile
3894 {
3895 word0 = (((~((1U << 2) - 1)) << 4) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 4);
3896 return *this;
3897 }
3898 CONSTEXPR NPU_NAMESPACE::mem_attr get_region3() const
3899 {
3900 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 6));
3901 return value;
3902 }
3903 NPU_NAMESPACE::mem_attr get_region3() const volatile
3904 {
3905 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 6));
3906 return value;
3907 }
3908 CONSTEXPR regioncfg_r &set_region3(NPU_NAMESPACE::mem_attr value)
3909 {
3910 word0 = (((~((1U << 2) - 1)) << 6) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 6);
3911 return *this;
3912 }
3913 volatile regioncfg_r &set_region3(NPU_NAMESPACE::mem_attr value) volatile
3914 {
3915 word0 = (((~((1U << 2) - 1)) << 6) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 6);
3916 return *this;
3917 }
3918 CONSTEXPR NPU_NAMESPACE::mem_attr get_region4() const
3919 {
3920 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 8));
3921 return value;
3922 }
3923 NPU_NAMESPACE::mem_attr get_region4() const volatile
3924 {
3925 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 8));
3926 return value;
3927 }
3928 CONSTEXPR regioncfg_r &set_region4(NPU_NAMESPACE::mem_attr value)
3929 {
3930 word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 8);
3931 return *this;
3932 }
3933 volatile regioncfg_r &set_region4(NPU_NAMESPACE::mem_attr value) volatile
3934 {
3935 word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 8);
3936 return *this;
3937 }
3938 CONSTEXPR NPU_NAMESPACE::mem_attr get_region5() const
3939 {
3940 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 10));
3941 return value;
3942 }
3943 NPU_NAMESPACE::mem_attr get_region5() const volatile
3944 {
3945 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 10));
3946 return value;
3947 }
3948 CONSTEXPR regioncfg_r &set_region5(NPU_NAMESPACE::mem_attr value)
3949 {
3950 word0 = (((~((1U << 2) - 1)) << 10) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 10);
3951 return *this;
3952 }
3953 volatile regioncfg_r &set_region5(NPU_NAMESPACE::mem_attr value) volatile
3954 {
3955 word0 = (((~((1U << 2) - 1)) << 10) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 10);
3956 return *this;
3957 }
3958 CONSTEXPR NPU_NAMESPACE::mem_attr get_region6() const
3959 {
3960 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 12));
3961 return value;
3962 }
3963 NPU_NAMESPACE::mem_attr get_region6() const volatile
3964 {
3965 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 12));
3966 return value;
3967 }
3968 CONSTEXPR regioncfg_r &set_region6(NPU_NAMESPACE::mem_attr value)
3969 {
3970 word0 = (((~((1U << 2) - 1)) << 12) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 12);
3971 return *this;
3972 }
3973 volatile regioncfg_r &set_region6(NPU_NAMESPACE::mem_attr value) volatile
3974 {
3975 word0 = (((~((1U << 2) - 1)) << 12) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 12);
3976 return *this;
3977 }
3978 CONSTEXPR NPU_NAMESPACE::mem_attr get_region7() const
3979 {
3980 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 14));
3981 return value;
3982 }
3983 NPU_NAMESPACE::mem_attr get_region7() const volatile
3984 {
3985 NPU_NAMESPACE::mem_attr value = static_cast<NPU_NAMESPACE::mem_attr>(((1U << 2) - 1) & (word0 >> 14));
3986 return value;
3987 }
3988 CONSTEXPR regioncfg_r &set_region7(NPU_NAMESPACE::mem_attr value)
3989 {
3990 word0 = (((~((1U << 2) - 1)) << 14) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 14);
3991 return *this;
3992 }
3993 volatile regioncfg_r &set_region7(NPU_NAMESPACE::mem_attr value) volatile
3994 {
3995 word0 = (((~((1U << 2) - 1)) << 14) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 14);
3996 return *this;
3997 }
3998#endif
3999};
4000
4001// axi_limit0_r - AXI limits for port 0 counter 0
4002struct axi_limit0_r
4003{
4004#ifndef __cplusplus
4005 union
4006 {
4007 struct
4008 {
4009 uint32_t max_beats : 2; // Burst split alignment
4010 uint32_t reserved0 : 2;
4011 uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals
4012 uint32_t reserved1 : 8;
4013 uint32_t
4014 max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63
4015 uint32_t reserved2 : 2;
4016 uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range
4017 // 0 to 31
4018 uint32_t reserved3 : 3;
4019 };
4020 uint32_t word;
4021 };
4022#else
4023 private:
4024 uint32_t word0;
4025
4026 public:
4027 CONSTEXPR axi_limit0_r() : word0(0) {}
4028 CONSTEXPR axi_limit0_r(uint32_t init) : word0(init) {}
4029 CONSTEXPR void operator=(uint32_t value)
4030 {
4031 word0 = value;
4032 }
4033 void operator=(uint32_t value) volatile
4034 {
4035 word0 = value;
4036 }
4037 CONSTEXPR operator uint32_t()
4038 {
4039 return word0;
4040 }
4041 operator uint32_t() volatile
4042 {
4043 return word0;
4044 }
4045 axi_limit0_r copy() volatile
4046 {
4047 return *this;
4048 }
4049 CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const
4050 {
4051 NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4052 return value;
4053 }
4054 NPU_NAMESPACE::max_beats get_max_beats() const volatile
4055 {
4056 NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4057 return value;
4058 }
4059 CONSTEXPR axi_limit0_r &set_max_beats(NPU_NAMESPACE::max_beats value)
4060 {
4061 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4062 return *this;
4063 }
4064 volatile axi_limit0_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile
4065 {
4066 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4067 return *this;
4068 }
4069 CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const
4070 {
4071 NPU_NAMESPACE::axi_mem_encoding value =
4072 static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4073 return value;
4074 }
4075 NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile
4076 {
4077 NPU_NAMESPACE::axi_mem_encoding value =
4078 static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4079 return value;
4080 }
4081 CONSTEXPR axi_limit0_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value)
4082 {
4083 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4084 return *this;
4085 }
4086 volatile axi_limit0_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile
4087 {
4088 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4089 return *this;
4090 }
4091 CONSTEXPR uint32_t get_max_outstanding_read_m1() const
4092 {
4093 uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4094 return value;
4095 }
4096 uint32_t get_max_outstanding_read_m1() const volatile
4097 {
4098 uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4099 return value;
4100 }
4101 CONSTEXPR axi_limit0_r &set_max_outstanding_read_m1(uint32_t value)
4102 {
4103 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4104 return *this;
4105 }
4106 volatile axi_limit0_r &set_max_outstanding_read_m1(uint32_t value) volatile
4107 {
4108 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4109 return *this;
4110 }
4111 CONSTEXPR uint32_t get_max_outstanding_write_m1() const
4112 {
4113 uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4114 return value;
4115 }
4116 uint32_t get_max_outstanding_write_m1() const volatile
4117 {
4118 uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4119 return value;
4120 }
4121 CONSTEXPR axi_limit0_r &set_max_outstanding_write_m1(uint32_t value)
4122 {
4123 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4124 return *this;
4125 }
4126 volatile axi_limit0_r &set_max_outstanding_write_m1(uint32_t value) volatile
4127 {
4128 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4129 return *this;
4130 }
4131#endif
4132};
4133
4134// axi_limit1_r - AXI limits for port 0 counter 1
4135struct axi_limit1_r
4136{
4137#ifndef __cplusplus
4138 union
4139 {
4140 struct
4141 {
4142 uint32_t max_beats : 2; // Burst split alignment
4143 uint32_t reserved0 : 2;
4144 uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals
4145 uint32_t reserved1 : 8;
4146 uint32_t
4147 max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63
4148 uint32_t reserved2 : 2;
4149 uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range
4150 // 0 to 31
4151 uint32_t reserved3 : 3;
4152 };
4153 uint32_t word;
4154 };
4155#else
4156 private:
4157 uint32_t word0;
4158
4159 public:
4160 CONSTEXPR axi_limit1_r() : word0(0) {}
4161 CONSTEXPR axi_limit1_r(uint32_t init) : word0(init) {}
4162 CONSTEXPR void operator=(uint32_t value)
4163 {
4164 word0 = value;
4165 }
4166 void operator=(uint32_t value) volatile
4167 {
4168 word0 = value;
4169 }
4170 CONSTEXPR operator uint32_t()
4171 {
4172 return word0;
4173 }
4174 operator uint32_t() volatile
4175 {
4176 return word0;
4177 }
4178 axi_limit1_r copy() volatile
4179 {
4180 return *this;
4181 }
4182 CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const
4183 {
4184 NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4185 return value;
4186 }
4187 NPU_NAMESPACE::max_beats get_max_beats() const volatile
4188 {
4189 NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4190 return value;
4191 }
4192 CONSTEXPR axi_limit1_r &set_max_beats(NPU_NAMESPACE::max_beats value)
4193 {
4194 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4195 return *this;
4196 }
4197 volatile axi_limit1_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile
4198 {
4199 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4200 return *this;
4201 }
4202 CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const
4203 {
4204 NPU_NAMESPACE::axi_mem_encoding value =
4205 static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4206 return value;
4207 }
4208 NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile
4209 {
4210 NPU_NAMESPACE::axi_mem_encoding value =
4211 static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4212 return value;
4213 }
4214 CONSTEXPR axi_limit1_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value)
4215 {
4216 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4217 return *this;
4218 }
4219 volatile axi_limit1_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile
4220 {
4221 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4222 return *this;
4223 }
4224 CONSTEXPR uint32_t get_max_outstanding_read_m1() const
4225 {
4226 uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4227 return value;
4228 }
4229 uint32_t get_max_outstanding_read_m1() const volatile
4230 {
4231 uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4232 return value;
4233 }
4234 CONSTEXPR axi_limit1_r &set_max_outstanding_read_m1(uint32_t value)
4235 {
4236 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4237 return *this;
4238 }
4239 volatile axi_limit1_r &set_max_outstanding_read_m1(uint32_t value) volatile
4240 {
4241 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4242 return *this;
4243 }
4244 CONSTEXPR uint32_t get_max_outstanding_write_m1() const
4245 {
4246 uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4247 return value;
4248 }
4249 uint32_t get_max_outstanding_write_m1() const volatile
4250 {
4251 uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4252 return value;
4253 }
4254 CONSTEXPR axi_limit1_r &set_max_outstanding_write_m1(uint32_t value)
4255 {
4256 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4257 return *this;
4258 }
4259 volatile axi_limit1_r &set_max_outstanding_write_m1(uint32_t value) volatile
4260 {
4261 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4262 return *this;
4263 }
4264#endif
4265};
4266
4267// axi_limit2_r - AXI limits for port 1 counter 2
4268struct axi_limit2_r
4269{
4270#ifndef __cplusplus
4271 union
4272 {
4273 struct
4274 {
4275 uint32_t max_beats : 2; // Burst split alignment
4276 uint32_t reserved0 : 2;
4277 uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals
4278 uint32_t reserved1 : 8;
4279 uint32_t
4280 max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63
4281 uint32_t reserved2 : 2;
4282 uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range
4283 // 0 to 31
4284 uint32_t reserved3 : 3;
4285 };
4286 uint32_t word;
4287 };
4288#else
4289 private:
4290 uint32_t word0;
4291
4292 public:
4293 CONSTEXPR axi_limit2_r() : word0(0) {}
4294 CONSTEXPR axi_limit2_r(uint32_t init) : word0(init) {}
4295 CONSTEXPR void operator=(uint32_t value)
4296 {
4297 word0 = value;
4298 }
4299 void operator=(uint32_t value) volatile
4300 {
4301 word0 = value;
4302 }
4303 CONSTEXPR operator uint32_t()
4304 {
4305 return word0;
4306 }
4307 operator uint32_t() volatile
4308 {
4309 return word0;
4310 }
4311 axi_limit2_r copy() volatile
4312 {
4313 return *this;
4314 }
4315 CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const
4316 {
4317 NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4318 return value;
4319 }
4320 NPU_NAMESPACE::max_beats get_max_beats() const volatile
4321 {
4322 NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4323 return value;
4324 }
4325 CONSTEXPR axi_limit2_r &set_max_beats(NPU_NAMESPACE::max_beats value)
4326 {
4327 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4328 return *this;
4329 }
4330 volatile axi_limit2_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile
4331 {
4332 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4333 return *this;
4334 }
4335 CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const
4336 {
4337 NPU_NAMESPACE::axi_mem_encoding value =
4338 static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4339 return value;
4340 }
4341 NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile
4342 {
4343 NPU_NAMESPACE::axi_mem_encoding value =
4344 static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4345 return value;
4346 }
4347 CONSTEXPR axi_limit2_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value)
4348 {
4349 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4350 return *this;
4351 }
4352 volatile axi_limit2_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile
4353 {
4354 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4355 return *this;
4356 }
4357 CONSTEXPR uint32_t get_max_outstanding_read_m1() const
4358 {
4359 uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4360 return value;
4361 }
4362 uint32_t get_max_outstanding_read_m1() const volatile
4363 {
4364 uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4365 return value;
4366 }
4367 CONSTEXPR axi_limit2_r &set_max_outstanding_read_m1(uint32_t value)
4368 {
4369 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4370 return *this;
4371 }
4372 volatile axi_limit2_r &set_max_outstanding_read_m1(uint32_t value) volatile
4373 {
4374 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4375 return *this;
4376 }
4377 CONSTEXPR uint32_t get_max_outstanding_write_m1() const
4378 {
4379 uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4380 return value;
4381 }
4382 uint32_t get_max_outstanding_write_m1() const volatile
4383 {
4384 uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4385 return value;
4386 }
4387 CONSTEXPR axi_limit2_r &set_max_outstanding_write_m1(uint32_t value)
4388 {
4389 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4390 return *this;
4391 }
4392 volatile axi_limit2_r &set_max_outstanding_write_m1(uint32_t value) volatile
4393 {
4394 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4395 return *this;
4396 }
4397#endif
4398};
4399
4400// axi_limit3_r - AXI limits for port 1 counter 3
4401struct axi_limit3_r
4402{
4403#ifndef __cplusplus
4404 union
4405 {
4406 struct
4407 {
4408 uint32_t max_beats : 2; // Burst split alignment
4409 uint32_t reserved0 : 2;
4410 uint32_t memtype : 4; // Memtype to be used to encode AxCACHE signals
4411 uint32_t reserved1 : 8;
4412 uint32_t
4413 max_outstanding_read_m1 : 6; // Maximum number of outstanding AXI read transactions - 1 in range 0 to 63
4414 uint32_t reserved2 : 2;
4415 uint32_t max_outstanding_write_m1 : 5; // Maximum number of outstanding AXI write transactions - 1 in range
4416 // 0 to 31
4417 uint32_t reserved3 : 3;
4418 };
4419 uint32_t word;
4420 };
4421#else
4422 private:
4423 uint32_t word0;
4424
4425 public:
4426 CONSTEXPR axi_limit3_r() : word0(0) {}
4427 CONSTEXPR axi_limit3_r(uint32_t init) : word0(init) {}
4428 CONSTEXPR void operator=(uint32_t value)
4429 {
4430 word0 = value;
4431 }
4432 void operator=(uint32_t value) volatile
4433 {
4434 word0 = value;
4435 }
4436 CONSTEXPR operator uint32_t()
4437 {
4438 return word0;
4439 }
4440 operator uint32_t() volatile
4441 {
4442 return word0;
4443 }
4444 axi_limit3_r copy() volatile
4445 {
4446 return *this;
4447 }
4448 CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats() const
4449 {
4450 NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4451 return value;
4452 }
4453 NPU_NAMESPACE::max_beats get_max_beats() const volatile
4454 {
4455 NPU_NAMESPACE::max_beats value = static_cast<NPU_NAMESPACE::max_beats>(((1U << 2) - 1) & (word0 >> 0));
4456 return value;
4457 }
4458 CONSTEXPR axi_limit3_r &set_max_beats(NPU_NAMESPACE::max_beats value)
4459 {
4460 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4461 return *this;
4462 }
4463 volatile axi_limit3_r &set_max_beats(NPU_NAMESPACE::max_beats value) volatile
4464 {
4465 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4466 return *this;
4467 }
4468 CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype() const
4469 {
4470 NPU_NAMESPACE::axi_mem_encoding value =
4471 static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4472 return value;
4473 }
4474 NPU_NAMESPACE::axi_mem_encoding get_memtype() const volatile
4475 {
4476 NPU_NAMESPACE::axi_mem_encoding value =
4477 static_cast<NPU_NAMESPACE::axi_mem_encoding>(((1U << 4) - 1) & (word0 >> 4));
4478 return value;
4479 }
4480 CONSTEXPR axi_limit3_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value)
4481 {
4482 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4483 return *this;
4484 }
4485 volatile axi_limit3_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding value) volatile
4486 {
4487 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 4);
4488 return *this;
4489 }
4490 CONSTEXPR uint32_t get_max_outstanding_read_m1() const
4491 {
4492 uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4493 return value;
4494 }
4495 uint32_t get_max_outstanding_read_m1() const volatile
4496 {
4497 uint32_t value = ((1U << 6) - 1) & (word0 >> 16);
4498 return value;
4499 }
4500 CONSTEXPR axi_limit3_r &set_max_outstanding_read_m1(uint32_t value)
4501 {
4502 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4503 return *this;
4504 }
4505 volatile axi_limit3_r &set_max_outstanding_read_m1(uint32_t value) volatile
4506 {
4507 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) & value) << 16);
4508 return *this;
4509 }
4510 CONSTEXPR uint32_t get_max_outstanding_write_m1() const
4511 {
4512 uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4513 return value;
4514 }
4515 uint32_t get_max_outstanding_write_m1() const volatile
4516 {
4517 uint32_t value = ((1U << 5) - 1) & (word0 >> 24);
4518 return value;
4519 }
4520 CONSTEXPR axi_limit3_r &set_max_outstanding_write_m1(uint32_t value)
4521 {
4522 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4523 return *this;
4524 }
4525 volatile axi_limit3_r &set_max_outstanding_write_m1(uint32_t value) volatile
4526 {
4527 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) & value) << 24);
4528 return *this;
4529 }
4530#endif
4531};
4532
4533// basep_r - The driver can use this address to relocate the command stream on region 0. If the region contains data
4534// requiring A-byte alignment then the base must be a multiple of A
4535struct basep_r
4536{
4537#ifndef __cplusplus
4538 union
4539 {
4540 struct
4541 {
4542 uint32_t offset_LO : 32; // Offset - LSB
4543 uint32_t offset_HI : 8; // Offset - MSB
4544 uint32_t reserved0 : 24;
4545 };
4546 uint32_t word[2];
4547 };
4548#else
4549 private:
4550 uint32_t word0;
4551 uint32_t word1;
4552
4553 public:
4554 CONSTEXPR basep_r() : word0(0), word1(0) {}
4555 CONSTEXPR basep_r(uint64_t init) :
4556 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
4557 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
4558 {
4559 }
4560 CONSTEXPR void operator=(uint64_t value)
4561 {
4562 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
4563 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
4564 }
4565 void operator=(uint64_t value) volatile
4566 {
4567 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
4568 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
4569 }
4570 CONSTEXPR operator uint64_t()
4571 {
4572 return (static_cast<uint64_t>(word1) << 32) | word0;
4573 }
4574 operator uint64_t() volatile
4575 {
4576 return (static_cast<uint64_t>(word1) << 32) | word0;
4577 }
4578 basep_r copy() volatile
4579 {
4580 return *this;
4581 }
4582#endif
4583};
4584
4585// wd_status_r - WD_STATUS
4586struct wd_status_r
4587{
4588#ifndef __cplusplus
4589 union
4590 {
4591 struct
4592 {
4593 uint32_t core_slice_state : 2; // WD core slice parser state
4594 uint32_t core_idle : 1; // Core idle
4595 uint32_t ctrl_state : 2; // WD control state
4596 uint32_t ctrl_idle : 1; // All stripe jobs idle (all weights consumed)
4597 uint32_t write_buf_index0 : 3; // current write index for next data from core
4598 uint32_t write_buf_valid0 : 1; // write buf valid (full)
4599 uint32_t write_buf_idle0 : 1; // write buf idle (empty)
4600 uint32_t write_buf_index1 : 3; // current write index for next data from core
4601 uint32_t write_buf_valid1 : 1; // write buf valid (full)
4602 uint32_t write_buf_idle1 : 1; // write buf idle (empty)
4603 uint32_t events : 12; // WD events mapped as appendix A
4604 uint32_t reserved0 : 4;
4605 };
4606 uint32_t word;
4607 };
4608#else
4609 private:
4610 uint32_t word0;
4611
4612 public:
4613 CONSTEXPR wd_status_r() : word0(0) {}
4614 CONSTEXPR wd_status_r(uint32_t init) : word0(init) {}
4615 CONSTEXPR void operator=(uint32_t value)
4616 {
4617 word0 = value;
4618 }
4619 void operator=(uint32_t value) volatile
4620 {
4621 word0 = value;
4622 }
4623 CONSTEXPR operator uint32_t()
4624 {
4625 return word0;
4626 }
4627 operator uint32_t() volatile
4628 {
4629 return word0;
4630 }
4631 wd_status_r copy() volatile
4632 {
4633 return *this;
4634 }
4635 CONSTEXPR NPU_NAMESPACE::wd_core_slice_state get_core_slice_state() const
4636 {
4637 NPU_NAMESPACE::wd_core_slice_state value =
4638 static_cast<NPU_NAMESPACE::wd_core_slice_state>(((1U << 2) - 1) & (word0 >> 0));
4639 return value;
4640 }
4641 NPU_NAMESPACE::wd_core_slice_state get_core_slice_state() const volatile
4642 {
4643 NPU_NAMESPACE::wd_core_slice_state value =
4644 static_cast<NPU_NAMESPACE::wd_core_slice_state>(((1U << 2) - 1) & (word0 >> 0));
4645 return value;
4646 }
4647 CONSTEXPR wd_status_r &set_core_slice_state(NPU_NAMESPACE::wd_core_slice_state value)
4648 {
4649 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4650 return *this;
4651 }
4652 volatile wd_status_r &set_core_slice_state(NPU_NAMESPACE::wd_core_slice_state value) volatile
4653 {
4654 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 0);
4655 return *this;
4656 }
4657 CONSTEXPR uint32_t get_core_idle() const
4658 {
4659 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
4660 return value;
4661 }
4662 uint32_t get_core_idle() const volatile
4663 {
4664 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
4665 return value;
4666 }
4667 CONSTEXPR wd_status_r &set_core_idle(uint32_t value)
4668 {
4669 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
4670 return *this;
4671 }
4672 volatile wd_status_r &set_core_idle(uint32_t value) volatile
4673 {
4674 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
4675 return *this;
4676 }
4677 CONSTEXPR NPU_NAMESPACE::wd_ctrl_state get_ctrl_state() const
4678 {
4679 NPU_NAMESPACE::wd_ctrl_state value = static_cast<NPU_NAMESPACE::wd_ctrl_state>(((1U << 2) - 1) & (word0 >> 3));
4680 return value;
4681 }
4682 NPU_NAMESPACE::wd_ctrl_state get_ctrl_state() const volatile
4683 {
4684 NPU_NAMESPACE::wd_ctrl_state value = static_cast<NPU_NAMESPACE::wd_ctrl_state>(((1U << 2) - 1) & (word0 >> 3));
4685 return value;
4686 }
4687 CONSTEXPR wd_status_r &set_ctrl_state(NPU_NAMESPACE::wd_ctrl_state value)
4688 {
4689 word0 = (((~((1U << 2) - 1)) << 3) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 3);
4690 return *this;
4691 }
4692 volatile wd_status_r &set_ctrl_state(NPU_NAMESPACE::wd_ctrl_state value) volatile
4693 {
4694 word0 = (((~((1U << 2) - 1)) << 3) & word0) | ((((1U << 2) - 1) & static_cast<uint32_t>(value)) << 3);
4695 return *this;
4696 }
4697 CONSTEXPR uint32_t get_ctrl_idle() const
4698 {
4699 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
4700 return value;
4701 }
4702 uint32_t get_ctrl_idle() const volatile
4703 {
4704 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
4705 return value;
4706 }
4707 CONSTEXPR wd_status_r &set_ctrl_idle(uint32_t value)
4708 {
4709 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
4710 return *this;
4711 }
4712 volatile wd_status_r &set_ctrl_idle(uint32_t value) volatile
4713 {
4714 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
4715 return *this;
4716 }
4717 CONSTEXPR uint32_t get_write_buf_index0() const
4718 {
4719 uint32_t value = ((1U << 3) - 1) & (word0 >> 6);
4720 return value;
4721 }
4722 uint32_t get_write_buf_index0() const volatile
4723 {
4724 uint32_t value = ((1U << 3) - 1) & (word0 >> 6);
4725 return value;
4726 }
4727 CONSTEXPR wd_status_r &set_write_buf_index0(uint32_t value)
4728 {
4729 word0 = (((~((1U << 3) - 1)) << 6) & word0) | ((((1U << 3) - 1) & value) << 6);
4730 return *this;
4731 }
4732 volatile wd_status_r &set_write_buf_index0(uint32_t value) volatile
4733 {
4734 word0 = (((~((1U << 3) - 1)) << 6) & word0) | ((((1U << 3) - 1) & value) << 6);
4735 return *this;
4736 }
4737 CONSTEXPR uint32_t get_write_buf_valid0() const
4738 {
4739 uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
4740 return value;
4741 }
4742 uint32_t get_write_buf_valid0() const volatile
4743 {
4744 uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
4745 return value;
4746 }
4747 CONSTEXPR wd_status_r &set_write_buf_valid0(uint32_t value)
4748 {
4749 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
4750 return *this;
4751 }
4752 volatile wd_status_r &set_write_buf_valid0(uint32_t value) volatile
4753 {
4754 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
4755 return *this;
4756 }
4757 CONSTEXPR uint32_t get_write_buf_idle0() const
4758 {
4759 uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
4760 return value;
4761 }
4762 uint32_t get_write_buf_idle0() const volatile
4763 {
4764 uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
4765 return value;
4766 }
4767 CONSTEXPR wd_status_r &set_write_buf_idle0(uint32_t value)
4768 {
4769 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
4770 return *this;
4771 }
4772 volatile wd_status_r &set_write_buf_idle0(uint32_t value) volatile
4773 {
4774 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
4775 return *this;
4776 }
4777 CONSTEXPR uint32_t get_write_buf_index1() const
4778 {
4779 uint32_t value = ((1U << 3) - 1) & (word0 >> 11);
4780 return value;
4781 }
4782 uint32_t get_write_buf_index1() const volatile
4783 {
4784 uint32_t value = ((1U << 3) - 1) & (word0 >> 11);
4785 return value;
4786 }
4787 CONSTEXPR wd_status_r &set_write_buf_index1(uint32_t value)
4788 {
4789 word0 = (((~((1U << 3) - 1)) << 11) & word0) | ((((1U << 3) - 1) & value) << 11);
4790 return *this;
4791 }
4792 volatile wd_status_r &set_write_buf_index1(uint32_t value) volatile
4793 {
4794 word0 = (((~((1U << 3) - 1)) << 11) & word0) | ((((1U << 3) - 1) & value) << 11);
4795 return *this;
4796 }
4797 CONSTEXPR uint32_t get_write_buf_valid1() const
4798 {
4799 uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
4800 return value;
4801 }
4802 uint32_t get_write_buf_valid1() const volatile
4803 {
4804 uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
4805 return value;
4806 }
4807 CONSTEXPR wd_status_r &set_write_buf_valid1(uint32_t value)
4808 {
4809 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
4810 return *this;
4811 }
4812 volatile wd_status_r &set_write_buf_valid1(uint32_t value) volatile
4813 {
4814 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
4815 return *this;
4816 }
4817 CONSTEXPR uint32_t get_write_buf_idle1() const
4818 {
4819 uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
4820 return value;
4821 }
4822 uint32_t get_write_buf_idle1() const volatile
4823 {
4824 uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
4825 return value;
4826 }
4827 CONSTEXPR wd_status_r &set_write_buf_idle1(uint32_t value)
4828 {
4829 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
4830 return *this;
4831 }
4832 volatile wd_status_r &set_write_buf_idle1(uint32_t value) volatile
4833 {
4834 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
4835 return *this;
4836 }
4837 CONSTEXPR uint32_t get_events() const
4838 {
4839 uint32_t value = ((1U << 12) - 1) & (word0 >> 16);
4840 return value;
4841 }
4842 uint32_t get_events() const volatile
4843 {
4844 uint32_t value = ((1U << 12) - 1) & (word0 >> 16);
4845 return value;
4846 }
4847 CONSTEXPR wd_status_r &set_events(uint32_t value)
4848 {
4849 word0 = (((~((1U << 12) - 1)) << 16) & word0) | ((((1U << 12) - 1) & value) << 16);
4850 return *this;
4851 }
4852 volatile wd_status_r &set_events(uint32_t value) volatile
4853 {
4854 word0 = (((~((1U << 12) - 1)) << 16) & word0) | ((((1U << 12) - 1) & value) << 16);
4855 return *this;
4856 }
4857#endif
4858};
4859
4860// mac_status_r - MAC_STATUS
4861struct mac_status_r
4862{
4863#ifndef __cplusplus
4864 union
4865 {
4866 struct
4867 {
4868 uint32_t block_cfg_valid : 1; // MAC has a valid block configuration
4869 uint32_t trav_en : 1; // MAC is doing block traversal
4870 uint32_t wait_for_ib : 1; // MAC is waiting for an Input Buffer to become available
4871 uint32_t wait_for_acc_buf : 1; // MAC is waiting for an Accumulator Buffer to become available
4872 uint32_t wait_for_weights : 1; // MAC is waiting for a Weight Block to become available
4873 uint32_t stall_stripe : 1; // MAC is stalling between two stripes
4874 uint32_t dw_sel : 1; // Currently used weight interface in MAC AI
4875 uint32_t wait_for_dw0_ready : 1; // MAC AI is waiting for MAC DPU to send dw0_ready to WD
4876 uint32_t wait_for_dw1_ready : 1; // MAC AI is waiting for MAC DPU to send dw1_ready to WD
4877 uint32_t acc_buf_sel_ai : 1; // Currently used AccBuf interface in MAC AI
4878 uint32_t wait_for_acc0_ready : 1; // MAC AI is waiting for acc0_ready from AO
4879 uint32_t wait_for_acc1_ready : 1; // MAC AI is waiting for acc1_ready from AO
4880 uint32_t acc_buf_sel_aa : 1; // Currently used AccBuf interface in MAC ADDER_ARRAY
4881 uint32_t acc0_valid : 1; // MAC outgoing value of acc0_valid
4882 uint32_t acc1_valid : 1; // MAC outgoing value of acc1_valid
4883 uint32_t reserved0 : 1;
4884 uint32_t events : 11; // Mapped to MAC events described in Appendix A
4885 uint32_t reserved1 : 5;
4886 };
4887 uint32_t word;
4888 };
4889#else
4890 private:
4891 uint32_t word0;
4892
4893 public:
4894 CONSTEXPR mac_status_r() : word0(0) {}
4895 CONSTEXPR mac_status_r(uint32_t init) : word0(init) {}
4896 CONSTEXPR void operator=(uint32_t value)
4897 {
4898 word0 = value;
4899 }
4900 void operator=(uint32_t value) volatile
4901 {
4902 word0 = value;
4903 }
4904 CONSTEXPR operator uint32_t()
4905 {
4906 return word0;
4907 }
4908 operator uint32_t() volatile
4909 {
4910 return word0;
4911 }
4912 mac_status_r copy() volatile
4913 {
4914 return *this;
4915 }
4916 CONSTEXPR uint32_t get_block_cfg_valid() const
4917 {
4918 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
4919 return value;
4920 }
4921 uint32_t get_block_cfg_valid() const volatile
4922 {
4923 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
4924 return value;
4925 }
4926 CONSTEXPR mac_status_r &set_block_cfg_valid(uint32_t value)
4927 {
4928 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
4929 return *this;
4930 }
4931 volatile mac_status_r &set_block_cfg_valid(uint32_t value) volatile
4932 {
4933 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
4934 return *this;
4935 }
4936 CONSTEXPR uint32_t get_trav_en() const
4937 {
4938 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
4939 return value;
4940 }
4941 uint32_t get_trav_en() const volatile
4942 {
4943 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
4944 return value;
4945 }
4946 CONSTEXPR mac_status_r &set_trav_en(uint32_t value)
4947 {
4948 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
4949 return *this;
4950 }
4951 volatile mac_status_r &set_trav_en(uint32_t value) volatile
4952 {
4953 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
4954 return *this;
4955 }
4956 CONSTEXPR uint32_t get_wait_for_ib() const
4957 {
4958 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
4959 return value;
4960 }
4961 uint32_t get_wait_for_ib() const volatile
4962 {
4963 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
4964 return value;
4965 }
4966 CONSTEXPR mac_status_r &set_wait_for_ib(uint32_t value)
4967 {
4968 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
4969 return *this;
4970 }
4971 volatile mac_status_r &set_wait_for_ib(uint32_t value) volatile
4972 {
4973 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
4974 return *this;
4975 }
4976 CONSTEXPR uint32_t get_wait_for_acc_buf() const
4977 {
4978 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
4979 return value;
4980 }
4981 uint32_t get_wait_for_acc_buf() const volatile
4982 {
4983 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
4984 return value;
4985 }
4986 CONSTEXPR mac_status_r &set_wait_for_acc_buf(uint32_t value)
4987 {
4988 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
4989 return *this;
4990 }
4991 volatile mac_status_r &set_wait_for_acc_buf(uint32_t value) volatile
4992 {
4993 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
4994 return *this;
4995 }
4996 CONSTEXPR uint32_t get_wait_for_weights() const
4997 {
4998 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
4999 return value;
5000 }
5001 uint32_t get_wait_for_weights() const volatile
5002 {
5003 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
5004 return value;
5005 }
5006 CONSTEXPR mac_status_r &set_wait_for_weights(uint32_t value)
5007 {
5008 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5009 return *this;
5010 }
5011 volatile mac_status_r &set_wait_for_weights(uint32_t value) volatile
5012 {
5013 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5014 return *this;
5015 }
5016 CONSTEXPR uint32_t get_stall_stripe() const
5017 {
5018 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5019 return value;
5020 }
5021 uint32_t get_stall_stripe() const volatile
5022 {
5023 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5024 return value;
5025 }
5026 CONSTEXPR mac_status_r &set_stall_stripe(uint32_t value)
5027 {
5028 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5029 return *this;
5030 }
5031 volatile mac_status_r &set_stall_stripe(uint32_t value) volatile
5032 {
5033 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5034 return *this;
5035 }
5036 CONSTEXPR uint32_t get_dw_sel() const
5037 {
5038 uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5039 return value;
5040 }
5041 uint32_t get_dw_sel() const volatile
5042 {
5043 uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5044 return value;
5045 }
5046 CONSTEXPR mac_status_r &set_dw_sel(uint32_t value)
5047 {
5048 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5049 return *this;
5050 }
5051 volatile mac_status_r &set_dw_sel(uint32_t value) volatile
5052 {
5053 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5054 return *this;
5055 }
5056 CONSTEXPR uint32_t get_wait_for_dw0_ready() const
5057 {
5058 uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5059 return value;
5060 }
5061 uint32_t get_wait_for_dw0_ready() const volatile
5062 {
5063 uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5064 return value;
5065 }
5066 CONSTEXPR mac_status_r &set_wait_for_dw0_ready(uint32_t value)
5067 {
5068 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5069 return *this;
5070 }
5071 volatile mac_status_r &set_wait_for_dw0_ready(uint32_t value) volatile
5072 {
5073 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5074 return *this;
5075 }
5076 CONSTEXPR uint32_t get_wait_for_dw1_ready() const
5077 {
5078 uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
5079 return value;
5080 }
5081 uint32_t get_wait_for_dw1_ready() const volatile
5082 {
5083 uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
5084 return value;
5085 }
5086 CONSTEXPR mac_status_r &set_wait_for_dw1_ready(uint32_t value)
5087 {
5088 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
5089 return *this;
5090 }
5091 volatile mac_status_r &set_wait_for_dw1_ready(uint32_t value) volatile
5092 {
5093 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
5094 return *this;
5095 }
5096 CONSTEXPR uint32_t get_acc_buf_sel_ai() const
5097 {
5098 uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
5099 return value;
5100 }
5101 uint32_t get_acc_buf_sel_ai() const volatile
5102 {
5103 uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
5104 return value;
5105 }
5106 CONSTEXPR mac_status_r &set_acc_buf_sel_ai(uint32_t value)
5107 {
5108 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
5109 return *this;
5110 }
5111 volatile mac_status_r &set_acc_buf_sel_ai(uint32_t value) volatile
5112 {
5113 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
5114 return *this;
5115 }
5116 CONSTEXPR uint32_t get_wait_for_acc0_ready() const
5117 {
5118 uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
5119 return value;
5120 }
5121 uint32_t get_wait_for_acc0_ready() const volatile
5122 {
5123 uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
5124 return value;
5125 }
5126 CONSTEXPR mac_status_r &set_wait_for_acc0_ready(uint32_t value)
5127 {
5128 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
5129 return *this;
5130 }
5131 volatile mac_status_r &set_wait_for_acc0_ready(uint32_t value) volatile
5132 {
5133 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
5134 return *this;
5135 }
5136 CONSTEXPR uint32_t get_wait_for_acc1_ready() const
5137 {
5138 uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
5139 return value;
5140 }
5141 uint32_t get_wait_for_acc1_ready() const volatile
5142 {
5143 uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
5144 return value;
5145 }
5146 CONSTEXPR mac_status_r &set_wait_for_acc1_ready(uint32_t value)
5147 {
5148 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
5149 return *this;
5150 }
5151 volatile mac_status_r &set_wait_for_acc1_ready(uint32_t value) volatile
5152 {
5153 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
5154 return *this;
5155 }
5156 CONSTEXPR uint32_t get_acc_buf_sel_aa() const
5157 {
5158 uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
5159 return value;
5160 }
5161 uint32_t get_acc_buf_sel_aa() const volatile
5162 {
5163 uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
5164 return value;
5165 }
5166 CONSTEXPR mac_status_r &set_acc_buf_sel_aa(uint32_t value)
5167 {
5168 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
5169 return *this;
5170 }
5171 volatile mac_status_r &set_acc_buf_sel_aa(uint32_t value) volatile
5172 {
5173 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
5174 return *this;
5175 }
5176 CONSTEXPR uint32_t get_acc0_valid() const
5177 {
5178 uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
5179 return value;
5180 }
5181 uint32_t get_acc0_valid() const volatile
5182 {
5183 uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
5184 return value;
5185 }
5186 CONSTEXPR mac_status_r &set_acc0_valid(uint32_t value)
5187 {
5188 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
5189 return *this;
5190 }
5191 volatile mac_status_r &set_acc0_valid(uint32_t value) volatile
5192 {
5193 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
5194 return *this;
5195 }
5196 CONSTEXPR uint32_t get_acc1_valid() const
5197 {
5198 uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
5199 return value;
5200 }
5201 uint32_t get_acc1_valid() const volatile
5202 {
5203 uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
5204 return value;
5205 }
5206 CONSTEXPR mac_status_r &set_acc1_valid(uint32_t value)
5207 {
5208 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
5209 return *this;
5210 }
5211 volatile mac_status_r &set_acc1_valid(uint32_t value) volatile
5212 {
5213 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
5214 return *this;
5215 }
5216 CONSTEXPR uint32_t get_events() const
5217 {
5218 uint32_t value = ((1U << 11) - 1) & (word0 >> 16);
5219 return value;
5220 }
5221 uint32_t get_events() const volatile
5222 {
5223 uint32_t value = ((1U << 11) - 1) & (word0 >> 16);
5224 return value;
5225 }
5226 CONSTEXPR mac_status_r &set_events(uint32_t value)
5227 {
5228 word0 = (((~((1U << 11) - 1)) << 16) & word0) | ((((1U << 11) - 1) & value) << 16);
5229 return *this;
5230 }
5231 volatile mac_status_r &set_events(uint32_t value) volatile
5232 {
5233 word0 = (((~((1U << 11) - 1)) << 16) & word0) | ((((1U << 11) - 1) & value) << 16);
5234 return *this;
5235 }
5236#endif
5237};
5238
5239// ao_status_r - AO_STATUS
5240struct ao_status_r
5241{
5242#ifndef __cplusplus
5243 union
5244 {
5245 struct
5246 {
5247 uint32_t cmd_sbw_valid : 1; // Block command to shared buffer write module is valid
5248 uint32_t cmd_act_valid : 1; // Block command to activation function module is valid
5249 uint32_t cmd_ctl_valid : 1; // Block command to control module is valid
5250 uint32_t cmd_scl_valid : 1; // Block command to scale module is valid
5251 uint32_t cmd_sbr_valid : 1; // Block command to shared buffer read module is valid
5252 uint32_t cmd_ofm_valid : 1; // Block command to ofm parameter module is valid
5253 uint32_t blk_cmd_ready : 1; // Ready to accept block command
5254 uint32_t blk_cmd_valid : 1; // Block command from CC is valid
5255 uint32_t reserved0 : 8;
5256 uint32_t events : 8; // Mapped to AO events described in Appendix A
5257 uint32_t reserved1 : 8;
5258 };
5259 uint32_t word;
5260 };
5261#else
5262 private:
5263 uint32_t word0;
5264
5265 public:
5266 CONSTEXPR ao_status_r() : word0(0) {}
5267 CONSTEXPR ao_status_r(uint32_t init) : word0(init) {}
5268 CONSTEXPR void operator=(uint32_t value)
5269 {
5270 word0 = value;
5271 }
5272 void operator=(uint32_t value) volatile
5273 {
5274 word0 = value;
5275 }
5276 CONSTEXPR operator uint32_t()
5277 {
5278 return word0;
5279 }
5280 operator uint32_t() volatile
5281 {
5282 return word0;
5283 }
5284 ao_status_r copy() volatile
5285 {
5286 return *this;
5287 }
5288 CONSTEXPR uint32_t get_cmd_sbw_valid() const
5289 {
5290 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
5291 return value;
5292 }
5293 uint32_t get_cmd_sbw_valid() const volatile
5294 {
5295 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
5296 return value;
5297 }
5298 CONSTEXPR ao_status_r &set_cmd_sbw_valid(uint32_t value)
5299 {
5300 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
5301 return *this;
5302 }
5303 volatile ao_status_r &set_cmd_sbw_valid(uint32_t value) volatile
5304 {
5305 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
5306 return *this;
5307 }
5308 CONSTEXPR uint32_t get_cmd_act_valid() const
5309 {
5310 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
5311 return value;
5312 }
5313 uint32_t get_cmd_act_valid() const volatile
5314 {
5315 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
5316 return value;
5317 }
5318 CONSTEXPR ao_status_r &set_cmd_act_valid(uint32_t value)
5319 {
5320 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
5321 return *this;
5322 }
5323 volatile ao_status_r &set_cmd_act_valid(uint32_t value) volatile
5324 {
5325 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
5326 return *this;
5327 }
5328 CONSTEXPR uint32_t get_cmd_ctl_valid() const
5329 {
5330 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
5331 return value;
5332 }
5333 uint32_t get_cmd_ctl_valid() const volatile
5334 {
5335 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
5336 return value;
5337 }
5338 CONSTEXPR ao_status_r &set_cmd_ctl_valid(uint32_t value)
5339 {
5340 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
5341 return *this;
5342 }
5343 volatile ao_status_r &set_cmd_ctl_valid(uint32_t value) volatile
5344 {
5345 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
5346 return *this;
5347 }
5348 CONSTEXPR uint32_t get_cmd_scl_valid() const
5349 {
5350 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
5351 return value;
5352 }
5353 uint32_t get_cmd_scl_valid() const volatile
5354 {
5355 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
5356 return value;
5357 }
5358 CONSTEXPR ao_status_r &set_cmd_scl_valid(uint32_t value)
5359 {
5360 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
5361 return *this;
5362 }
5363 volatile ao_status_r &set_cmd_scl_valid(uint32_t value) volatile
5364 {
5365 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
5366 return *this;
5367 }
5368 CONSTEXPR uint32_t get_cmd_sbr_valid() const
5369 {
5370 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
5371 return value;
5372 }
5373 uint32_t get_cmd_sbr_valid() const volatile
5374 {
5375 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
5376 return value;
5377 }
5378 CONSTEXPR ao_status_r &set_cmd_sbr_valid(uint32_t value)
5379 {
5380 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5381 return *this;
5382 }
5383 volatile ao_status_r &set_cmd_sbr_valid(uint32_t value) volatile
5384 {
5385 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5386 return *this;
5387 }
5388 CONSTEXPR uint32_t get_cmd_ofm_valid() const
5389 {
5390 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5391 return value;
5392 }
5393 uint32_t get_cmd_ofm_valid() const volatile
5394 {
5395 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5396 return value;
5397 }
5398 CONSTEXPR ao_status_r &set_cmd_ofm_valid(uint32_t value)
5399 {
5400 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5401 return *this;
5402 }
5403 volatile ao_status_r &set_cmd_ofm_valid(uint32_t value) volatile
5404 {
5405 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5406 return *this;
5407 }
5408 CONSTEXPR uint32_t get_blk_cmd_ready() const
5409 {
5410 uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5411 return value;
5412 }
5413 uint32_t get_blk_cmd_ready() const volatile
5414 {
5415 uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5416 return value;
5417 }
5418 CONSTEXPR ao_status_r &set_blk_cmd_ready(uint32_t value)
5419 {
5420 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5421 return *this;
5422 }
5423 volatile ao_status_r &set_blk_cmd_ready(uint32_t value) volatile
5424 {
5425 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5426 return *this;
5427 }
5428 CONSTEXPR uint32_t get_blk_cmd_valid() const
5429 {
5430 uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5431 return value;
5432 }
5433 uint32_t get_blk_cmd_valid() const volatile
5434 {
5435 uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5436 return value;
5437 }
5438 CONSTEXPR ao_status_r &set_blk_cmd_valid(uint32_t value)
5439 {
5440 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5441 return *this;
5442 }
5443 volatile ao_status_r &set_blk_cmd_valid(uint32_t value) volatile
5444 {
5445 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5446 return *this;
5447 }
5448 CONSTEXPR uint32_t get_events() const
5449 {
5450 uint32_t value = ((1U << 8) - 1) & (word0 >> 16);
5451 return value;
5452 }
5453 uint32_t get_events() const volatile
5454 {
5455 uint32_t value = ((1U << 8) - 1) & (word0 >> 16);
5456 return value;
5457 }
5458 CONSTEXPR ao_status_r &set_events(uint32_t value)
5459 {
5460 word0 = (((~((1U << 8) - 1)) << 16) & word0) | ((((1U << 8) - 1) & value) << 16);
5461 return *this;
5462 }
5463 volatile ao_status_r &set_events(uint32_t value) volatile
5464 {
5465 word0 = (((~((1U << 8) - 1)) << 16) & word0) | ((((1U << 8) - 1) & value) << 16);
5466 return *this;
5467 }
5468#endif
5469};
5470
5471// dma_status0_r - DMA_STATUS0
5472struct dma_status0_r
5473{
5474#ifndef __cplusplus
5475 union
5476 {
5477 struct
5478 {
5479 uint32_t cmd_idle : 1; // When this bit is high means that the CMD block is not busy in generating addresses
5480 // for a CMD job
5481 uint32_t ifm_idle : 1; // When this bit is high means that there are no ongoing IFM jobs
5482 uint32_t wgt_idle_c0 : 1; // When this bit is high means that the WGT block is not busy in generating
5483 // addresses for a WGT job
5484 uint32_t bas_idle_c0 : 1; // When this bit is high means that the BAS block is not busy in generating
5485 // addresses for a BAS job
5486 uint32_t m2m_idle : 1; // When this bit is high means that there are no ongoing M2M jobs
5487 uint32_t ofm_idle : 1; // When this bit is high means that there are no ongoing OFM jobs
5488 uint32_t halt_req : 1; // CPM has requested to HALT AXI bus before soft reset
5489 uint32_t halt_ack : 1; // DMA is in condition to halt the AXI bus since there are no pending transactions
5490 uint32_t pause_req : 1; // CC has requested to pause the AXI
5491 uint32_t pause_ack : 1; // DMA is in condition to pause the AXI bus since there are no pending transactions
5492 uint32_t ib0_ai_valid_c0 : 1; // Data for AI to be read in IFM input buffer 0 - Core 0
5493 uint32_t ib0_ai_ready_c0 : 1; // Data consumed from AI in IFM input buffer 0 - Core 0
5494 uint32_t ib1_ai_valid_c0 : 1; // Data for AI to be read in IFM input buffer 1 - Core 0
5495 uint32_t ib1_ai_ready_c0 : 1; // Data consumed from AI in IFM input buffer 1 - Core 0
5496 uint32_t ib0_ao_valid_c0 : 1; // Data for AO to be read in IFM input buffer 0 - Core 0
5497 uint32_t ib0_ao_ready_c0 : 1; // Data consumed from AO in IFM input buffer 0 - Core 0
5498 uint32_t ib1_ao_valid_c0 : 1; // Data for AO to be read in IFM input buffer 0 - Core 0
5499 uint32_t ib1_ao_ready_c0 : 1; // Data consumed from AO in IFM input buffer 1 - Core 0
5500 uint32_t ob0_valid_c0 : 1; // Data for DMA ready to be consumed in OFM output buffer 0 - Core 0
5501 uint32_t ob0_ready_c0 : 1; // Data consumed from DMA in OFM output buffer 0 - Core 0
5502 uint32_t ob1_valid_c0 : 1; // Data for DMA ready to be consumed in OFM output buffer 1 - Core 0
5503 uint32_t ob1_ready_c0 : 1; // Data consumed from DMA in OFM output buffer 1 - Core 0
5504 uint32_t cmd_valid : 1; // New command word for CC to be consumed
5505 uint32_t cmd_ready : 1; // command word consumed by CC
5506 uint32_t wd_bitstream_valid_c0 : 1; // New weight word for WD to be consumed - Core 0
5507 uint32_t wd_bitstream_ready_c0 : 1; // Weight word consumed by WD - Core 0
5508 uint32_t bs_bitstream_valid_c0 : 1; // New BaS word for AO to be consumed - Core 0
5509 uint32_t bs_bitstream_ready_c0 : 1; // BaS word consumed by AO - Core 0
5510 uint32_t axi0_ar_stalled : 1; // Read transfer request stalled on arready low AXI0 (due to memory system)
5511 uint32_t axi0_rd_limit_stall : 1; // Read stalled due to one AXI0 limit counter being reached
5512 uint32_t axi0_aw_stalled : 1; // Write transfer request stalled on awready low AXI0 (due to memory system)
5513 uint32_t axi0_w_stalled : 1; // Write transfer stalled on awready low AXI0 (due to memory system)
5514 };
5515 uint32_t word;
5516 };
5517#else
5518 private:
5519 uint32_t word0;
5520
5521 public:
5522 CONSTEXPR dma_status0_r() : word0(0) {}
5523 CONSTEXPR dma_status0_r(uint32_t init) : word0(init) {}
5524 CONSTEXPR void operator=(uint32_t value)
5525 {
5526 word0 = value;
5527 }
5528 void operator=(uint32_t value) volatile
5529 {
5530 word0 = value;
5531 }
5532 CONSTEXPR operator uint32_t()
5533 {
5534 return word0;
5535 }
5536 operator uint32_t() volatile
5537 {
5538 return word0;
5539 }
5540 dma_status0_r copy() volatile
5541 {
5542 return *this;
5543 }
5544 CONSTEXPR uint32_t get_cmd_idle() const
5545 {
5546 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
5547 return value;
5548 }
5549 uint32_t get_cmd_idle() const volatile
5550 {
5551 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
5552 return value;
5553 }
5554 CONSTEXPR dma_status0_r &set_cmd_idle(uint32_t value)
5555 {
5556 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
5557 return *this;
5558 }
5559 volatile dma_status0_r &set_cmd_idle(uint32_t value) volatile
5560 {
5561 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
5562 return *this;
5563 }
5564 CONSTEXPR uint32_t get_ifm_idle() const
5565 {
5566 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
5567 return value;
5568 }
5569 uint32_t get_ifm_idle() const volatile
5570 {
5571 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
5572 return value;
5573 }
5574 CONSTEXPR dma_status0_r &set_ifm_idle(uint32_t value)
5575 {
5576 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
5577 return *this;
5578 }
5579 volatile dma_status0_r &set_ifm_idle(uint32_t value) volatile
5580 {
5581 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
5582 return *this;
5583 }
5584 CONSTEXPR uint32_t get_wgt_idle_c0() const
5585 {
5586 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
5587 return value;
5588 }
5589 uint32_t get_wgt_idle_c0() const volatile
5590 {
5591 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
5592 return value;
5593 }
5594 CONSTEXPR dma_status0_r &set_wgt_idle_c0(uint32_t value)
5595 {
5596 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
5597 return *this;
5598 }
5599 volatile dma_status0_r &set_wgt_idle_c0(uint32_t value) volatile
5600 {
5601 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
5602 return *this;
5603 }
5604 CONSTEXPR uint32_t get_bas_idle_c0() const
5605 {
5606 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
5607 return value;
5608 }
5609 uint32_t get_bas_idle_c0() const volatile
5610 {
5611 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
5612 return value;
5613 }
5614 CONSTEXPR dma_status0_r &set_bas_idle_c0(uint32_t value)
5615 {
5616 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
5617 return *this;
5618 }
5619 volatile dma_status0_r &set_bas_idle_c0(uint32_t value) volatile
5620 {
5621 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
5622 return *this;
5623 }
5624 CONSTEXPR uint32_t get_m2m_idle() const
5625 {
5626 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
5627 return value;
5628 }
5629 uint32_t get_m2m_idle() const volatile
5630 {
5631 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
5632 return value;
5633 }
5634 CONSTEXPR dma_status0_r &set_m2m_idle(uint32_t value)
5635 {
5636 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5637 return *this;
5638 }
5639 volatile dma_status0_r &set_m2m_idle(uint32_t value) volatile
5640 {
5641 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
5642 return *this;
5643 }
5644 CONSTEXPR uint32_t get_ofm_idle() const
5645 {
5646 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5647 return value;
5648 }
5649 uint32_t get_ofm_idle() const volatile
5650 {
5651 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
5652 return value;
5653 }
5654 CONSTEXPR dma_status0_r &set_ofm_idle(uint32_t value)
5655 {
5656 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5657 return *this;
5658 }
5659 volatile dma_status0_r &set_ofm_idle(uint32_t value) volatile
5660 {
5661 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
5662 return *this;
5663 }
5664 CONSTEXPR uint32_t get_halt_req() const
5665 {
5666 uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5667 return value;
5668 }
5669 uint32_t get_halt_req() const volatile
5670 {
5671 uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
5672 return value;
5673 }
5674 CONSTEXPR dma_status0_r &set_halt_req(uint32_t value)
5675 {
5676 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5677 return *this;
5678 }
5679 volatile dma_status0_r &set_halt_req(uint32_t value) volatile
5680 {
5681 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
5682 return *this;
5683 }
5684 CONSTEXPR uint32_t get_halt_ack() const
5685 {
5686 uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5687 return value;
5688 }
5689 uint32_t get_halt_ack() const volatile
5690 {
5691 uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
5692 return value;
5693 }
5694 CONSTEXPR dma_status0_r &set_halt_ack(uint32_t value)
5695 {
5696 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5697 return *this;
5698 }
5699 volatile dma_status0_r &set_halt_ack(uint32_t value) volatile
5700 {
5701 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
5702 return *this;
5703 }
5704 CONSTEXPR uint32_t get_pause_req() const
5705 {
5706 uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
5707 return value;
5708 }
5709 uint32_t get_pause_req() const volatile
5710 {
5711 uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
5712 return value;
5713 }
5714 CONSTEXPR dma_status0_r &set_pause_req(uint32_t value)
5715 {
5716 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
5717 return *this;
5718 }
5719 volatile dma_status0_r &set_pause_req(uint32_t value) volatile
5720 {
5721 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
5722 return *this;
5723 }
5724 CONSTEXPR uint32_t get_pause_ack() const
5725 {
5726 uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
5727 return value;
5728 }
5729 uint32_t get_pause_ack() const volatile
5730 {
5731 uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
5732 return value;
5733 }
5734 CONSTEXPR dma_status0_r &set_pause_ack(uint32_t value)
5735 {
5736 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
5737 return *this;
5738 }
5739 volatile dma_status0_r &set_pause_ack(uint32_t value) volatile
5740 {
5741 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
5742 return *this;
5743 }
5744 CONSTEXPR uint32_t get_ib0_ai_valid_c0() const
5745 {
5746 uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
5747 return value;
5748 }
5749 uint32_t get_ib0_ai_valid_c0() const volatile
5750 {
5751 uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
5752 return value;
5753 }
5754 CONSTEXPR dma_status0_r &set_ib0_ai_valid_c0(uint32_t value)
5755 {
5756 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
5757 return *this;
5758 }
5759 volatile dma_status0_r &set_ib0_ai_valid_c0(uint32_t value) volatile
5760 {
5761 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
5762 return *this;
5763 }
5764 CONSTEXPR uint32_t get_ib0_ai_ready_c0() const
5765 {
5766 uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
5767 return value;
5768 }
5769 uint32_t get_ib0_ai_ready_c0() const volatile
5770 {
5771 uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
5772 return value;
5773 }
5774 CONSTEXPR dma_status0_r &set_ib0_ai_ready_c0(uint32_t value)
5775 {
5776 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
5777 return *this;
5778 }
5779 volatile dma_status0_r &set_ib0_ai_ready_c0(uint32_t value) volatile
5780 {
5781 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
5782 return *this;
5783 }
5784 CONSTEXPR uint32_t get_ib1_ai_valid_c0() const
5785 {
5786 uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
5787 return value;
5788 }
5789 uint32_t get_ib1_ai_valid_c0() const volatile
5790 {
5791 uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
5792 return value;
5793 }
5794 CONSTEXPR dma_status0_r &set_ib1_ai_valid_c0(uint32_t value)
5795 {
5796 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
5797 return *this;
5798 }
5799 volatile dma_status0_r &set_ib1_ai_valid_c0(uint32_t value) volatile
5800 {
5801 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
5802 return *this;
5803 }
5804 CONSTEXPR uint32_t get_ib1_ai_ready_c0() const
5805 {
5806 uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
5807 return value;
5808 }
5809 uint32_t get_ib1_ai_ready_c0() const volatile
5810 {
5811 uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
5812 return value;
5813 }
5814 CONSTEXPR dma_status0_r &set_ib1_ai_ready_c0(uint32_t value)
5815 {
5816 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
5817 return *this;
5818 }
5819 volatile dma_status0_r &set_ib1_ai_ready_c0(uint32_t value) volatile
5820 {
5821 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
5822 return *this;
5823 }
5824 CONSTEXPR uint32_t get_ib0_ao_valid_c0() const
5825 {
5826 uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
5827 return value;
5828 }
5829 uint32_t get_ib0_ao_valid_c0() const volatile
5830 {
5831 uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
5832 return value;
5833 }
5834 CONSTEXPR dma_status0_r &set_ib0_ao_valid_c0(uint32_t value)
5835 {
5836 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
5837 return *this;
5838 }
5839 volatile dma_status0_r &set_ib0_ao_valid_c0(uint32_t value) volatile
5840 {
5841 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
5842 return *this;
5843 }
5844 CONSTEXPR uint32_t get_ib0_ao_ready_c0() const
5845 {
5846 uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
5847 return value;
5848 }
5849 uint32_t get_ib0_ao_ready_c0() const volatile
5850 {
5851 uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
5852 return value;
5853 }
5854 CONSTEXPR dma_status0_r &set_ib0_ao_ready_c0(uint32_t value)
5855 {
5856 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
5857 return *this;
5858 }
5859 volatile dma_status0_r &set_ib0_ao_ready_c0(uint32_t value) volatile
5860 {
5861 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
5862 return *this;
5863 }
5864 CONSTEXPR uint32_t get_ib1_ao_valid_c0() const
5865 {
5866 uint32_t value = ((1U << 1) - 1) & (word0 >> 16);
5867 return value;
5868 }
5869 uint32_t get_ib1_ao_valid_c0() const volatile
5870 {
5871 uint32_t value = ((1U << 1) - 1) & (word0 >> 16);
5872 return value;
5873 }
5874 CONSTEXPR dma_status0_r &set_ib1_ao_valid_c0(uint32_t value)
5875 {
5876 word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16);
5877 return *this;
5878 }
5879 volatile dma_status0_r &set_ib1_ao_valid_c0(uint32_t value) volatile
5880 {
5881 word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16);
5882 return *this;
5883 }
5884 CONSTEXPR uint32_t get_ib1_ao_ready_c0() const
5885 {
5886 uint32_t value = ((1U << 1) - 1) & (word0 >> 17);
5887 return value;
5888 }
5889 uint32_t get_ib1_ao_ready_c0() const volatile
5890 {
5891 uint32_t value = ((1U << 1) - 1) & (word0 >> 17);
5892 return value;
5893 }
5894 CONSTEXPR dma_status0_r &set_ib1_ao_ready_c0(uint32_t value)
5895 {
5896 word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17);
5897 return *this;
5898 }
5899 volatile dma_status0_r &set_ib1_ao_ready_c0(uint32_t value) volatile
5900 {
5901 word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17);
5902 return *this;
5903 }
5904 CONSTEXPR uint32_t get_ob0_valid_c0() const
5905 {
5906 uint32_t value = ((1U << 1) - 1) & (word0 >> 18);
5907 return value;
5908 }
5909 uint32_t get_ob0_valid_c0() const volatile
5910 {
5911 uint32_t value = ((1U << 1) - 1) & (word0 >> 18);
5912 return value;
5913 }
5914 CONSTEXPR dma_status0_r &set_ob0_valid_c0(uint32_t value)
5915 {
5916 word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18);
5917 return *this;
5918 }
5919 volatile dma_status0_r &set_ob0_valid_c0(uint32_t value) volatile
5920 {
5921 word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18);
5922 return *this;
5923 }
5924 CONSTEXPR uint32_t get_ob0_ready_c0() const
5925 {
5926 uint32_t value = ((1U << 1) - 1) & (word0 >> 19);
5927 return value;
5928 }
5929 uint32_t get_ob0_ready_c0() const volatile
5930 {
5931 uint32_t value = ((1U << 1) - 1) & (word0 >> 19);
5932 return value;
5933 }
5934 CONSTEXPR dma_status0_r &set_ob0_ready_c0(uint32_t value)
5935 {
5936 word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19);
5937 return *this;
5938 }
5939 volatile dma_status0_r &set_ob0_ready_c0(uint32_t value) volatile
5940 {
5941 word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19);
5942 return *this;
5943 }
5944 CONSTEXPR uint32_t get_ob1_valid_c0() const
5945 {
5946 uint32_t value = ((1U << 1) - 1) & (word0 >> 20);
5947 return value;
5948 }
5949 uint32_t get_ob1_valid_c0() const volatile
5950 {
5951 uint32_t value = ((1U << 1) - 1) & (word0 >> 20);
5952 return value;
5953 }
5954 CONSTEXPR dma_status0_r &set_ob1_valid_c0(uint32_t value)
5955 {
5956 word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20);
5957 return *this;
5958 }
5959 volatile dma_status0_r &set_ob1_valid_c0(uint32_t value) volatile
5960 {
5961 word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20);
5962 return *this;
5963 }
5964 CONSTEXPR uint32_t get_ob1_ready_c0() const
5965 {
5966 uint32_t value = ((1U << 1) - 1) & (word0 >> 21);
5967 return value;
5968 }
5969 uint32_t get_ob1_ready_c0() const volatile
5970 {
5971 uint32_t value = ((1U << 1) - 1) & (word0 >> 21);
5972 return value;
5973 }
5974 CONSTEXPR dma_status0_r &set_ob1_ready_c0(uint32_t value)
5975 {
5976 word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21);
5977 return *this;
5978 }
5979 volatile dma_status0_r &set_ob1_ready_c0(uint32_t value) volatile
5980 {
5981 word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21);
5982 return *this;
5983 }
5984 CONSTEXPR uint32_t get_cmd_valid() const
5985 {
5986 uint32_t value = ((1U << 1) - 1) & (word0 >> 22);
5987 return value;
5988 }
5989 uint32_t get_cmd_valid() const volatile
5990 {
5991 uint32_t value = ((1U << 1) - 1) & (word0 >> 22);
5992 return value;
5993 }
5994 CONSTEXPR dma_status0_r &set_cmd_valid(uint32_t value)
5995 {
5996 word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22);
5997 return *this;
5998 }
5999 volatile dma_status0_r &set_cmd_valid(uint32_t value) volatile
6000 {
6001 word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22);
6002 return *this;
6003 }
6004 CONSTEXPR uint32_t get_cmd_ready() const
6005 {
6006 uint32_t value = ((1U << 1) - 1) & (word0 >> 23);
6007 return value;
6008 }
6009 uint32_t get_cmd_ready() const volatile
6010 {
6011 uint32_t value = ((1U << 1) - 1) & (word0 >> 23);
6012 return value;
6013 }
6014 CONSTEXPR dma_status0_r &set_cmd_ready(uint32_t value)
6015 {
6016 word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23);
6017 return *this;
6018 }
6019 volatile dma_status0_r &set_cmd_ready(uint32_t value) volatile
6020 {
6021 word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23);
6022 return *this;
6023 }
6024 CONSTEXPR uint32_t get_wd_bitstream_valid_c0() const
6025 {
6026 uint32_t value = ((1U << 1) - 1) & (word0 >> 24);
6027 return value;
6028 }
6029 uint32_t get_wd_bitstream_valid_c0() const volatile
6030 {
6031 uint32_t value = ((1U << 1) - 1) & (word0 >> 24);
6032 return value;
6033 }
6034 CONSTEXPR dma_status0_r &set_wd_bitstream_valid_c0(uint32_t value)
6035 {
6036 word0 = (((~((1U << 1) - 1)) << 24) & word0) | ((((1U << 1) - 1) & value) << 24);
6037 return *this;
6038 }
6039 volatile dma_status0_r &set_wd_bitstream_valid_c0(uint32_t value) volatile
6040 {
6041 word0 = (((~((1U << 1) - 1)) << 24) & word0) | ((((1U << 1) - 1) & value) << 24);
6042 return *this;
6043 }
6044 CONSTEXPR uint32_t get_wd_bitstream_ready_c0() const
6045 {
6046 uint32_t value = ((1U << 1) - 1) & (word0 >> 25);
6047 return value;
6048 }
6049 uint32_t get_wd_bitstream_ready_c0() const volatile
6050 {
6051 uint32_t value = ((1U << 1) - 1) & (word0 >> 25);
6052 return value;
6053 }
6054 CONSTEXPR dma_status0_r &set_wd_bitstream_ready_c0(uint32_t value)
6055 {
6056 word0 = (((~((1U << 1) - 1)) << 25) & word0) | ((((1U << 1) - 1) & value) << 25);
6057 return *this;
6058 }
6059 volatile dma_status0_r &set_wd_bitstream_ready_c0(uint32_t value) volatile
6060 {
6061 word0 = (((~((1U << 1) - 1)) << 25) & word0) | ((((1U << 1) - 1) & value) << 25);
6062 return *this;
6063 }
6064 CONSTEXPR uint32_t get_bs_bitstream_valid_c0() const
6065 {
6066 uint32_t value = ((1U << 1) - 1) & (word0 >> 26);
6067 return value;
6068 }
6069 uint32_t get_bs_bitstream_valid_c0() const volatile
6070 {
6071 uint32_t value = ((1U << 1) - 1) & (word0 >> 26);
6072 return value;
6073 }
6074 CONSTEXPR dma_status0_r &set_bs_bitstream_valid_c0(uint32_t value)
6075 {
6076 word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & value) << 26);
6077 return *this;
6078 }
6079 volatile dma_status0_r &set_bs_bitstream_valid_c0(uint32_t value) volatile
6080 {
6081 word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) & value) << 26);
6082 return *this;
6083 }
6084 CONSTEXPR uint32_t get_bs_bitstream_ready_c0() const
6085 {
6086 uint32_t value = ((1U << 1) - 1) & (word0 >> 27);
6087 return value;
6088 }
6089 uint32_t get_bs_bitstream_ready_c0() const volatile
6090 {
6091 uint32_t value = ((1U << 1) - 1) & (word0 >> 27);
6092 return value;
6093 }
6094 CONSTEXPR dma_status0_r &set_bs_bitstream_ready_c0(uint32_t value)
6095 {
6096 word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & value) << 27);
6097 return *this;
6098 }
6099 volatile dma_status0_r &set_bs_bitstream_ready_c0(uint32_t value) volatile
6100 {
6101 word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) & value) << 27);
6102 return *this;
6103 }
6104 CONSTEXPR uint32_t get_axi0_ar_stalled() const
6105 {
6106 uint32_t value = ((1U << 1) - 1) & (word0 >> 28);
6107 return value;
6108 }
6109 uint32_t get_axi0_ar_stalled() const volatile
6110 {
6111 uint32_t value = ((1U << 1) - 1) & (word0 >> 28);
6112 return value;
6113 }
6114 CONSTEXPR dma_status0_r &set_axi0_ar_stalled(uint32_t value)
6115 {
6116 word0 = (((~((1U << 1) - 1)) << 28) & word0) | ((((1U << 1) - 1) & value) << 28);
6117 return *this;
6118 }
6119 volatile dma_status0_r &set_axi0_ar_stalled(uint32_t value) volatile
6120 {
6121 word0 = (((~((1U << 1) - 1)) << 28) & word0) | ((((1U << 1) - 1) & value) << 28);
6122 return *this;
6123 }
6124 CONSTEXPR uint32_t get_axi0_rd_limit_stall() const
6125 {
6126 uint32_t value = ((1U << 1) - 1) & (word0 >> 29);
6127 return value;
6128 }
6129 uint32_t get_axi0_rd_limit_stall() const volatile
6130 {
6131 uint32_t value = ((1U << 1) - 1) & (word0 >> 29);
6132 return value;
6133 }
6134 CONSTEXPR dma_status0_r &set_axi0_rd_limit_stall(uint32_t value)
6135 {
6136 word0 = (((~((1U << 1) - 1)) << 29) & word0) | ((((1U << 1) - 1) & value) << 29);
6137 return *this;
6138 }
6139 volatile dma_status0_r &set_axi0_rd_limit_stall(uint32_t value) volatile
6140 {
6141 word0 = (((~((1U << 1) - 1)) << 29) & word0) | ((((1U << 1) - 1) & value) << 29);
6142 return *this;
6143 }
6144 CONSTEXPR uint32_t get_axi0_aw_stalled() const
6145 {
6146 uint32_t value = ((1U << 1) - 1) & (word0 >> 30);
6147 return value;
6148 }
6149 uint32_t get_axi0_aw_stalled() const volatile
6150 {
6151 uint32_t value = ((1U << 1) - 1) & (word0 >> 30);
6152 return value;
6153 }
6154 CONSTEXPR dma_status0_r &set_axi0_aw_stalled(uint32_t value)
6155 {
6156 word0 = (((~((1U << 1) - 1)) << 30) & word0) | ((((1U << 1) - 1) & value) << 30);
6157 return *this;
6158 }
6159 volatile dma_status0_r &set_axi0_aw_stalled(uint32_t value) volatile
6160 {
6161 word0 = (((~((1U << 1) - 1)) << 30) & word0) | ((((1U << 1) - 1) & value) << 30);
6162 return *this;
6163 }
6164 CONSTEXPR uint32_t get_axi0_w_stalled() const
6165 {
6166 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
6167 return value;
6168 }
6169 uint32_t get_axi0_w_stalled() const volatile
6170 {
6171 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
6172 return value;
6173 }
6174 CONSTEXPR dma_status0_r &set_axi0_w_stalled(uint32_t value)
6175 {
6176 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
6177 return *this;
6178 }
6179 volatile dma_status0_r &set_axi0_w_stalled(uint32_t value) volatile
6180 {
6181 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
6182 return *this;
6183 }
6184#endif
6185};
6186
6187// dma_status1_r - DMA_STATUS1
6188struct dma_status1_r
6189{
6190#ifndef __cplusplus
6191 union
6192 {
6193 struct
6194 {
6195 uint32_t axi0_wr_limit_stall : 1; // Write stalled due to one AXI0 limit counter being reached
6196 uint32_t axi1_ar_stalled : 1; // Read transfer request stalled on arready low AXI1 (due to memory system)
6197 uint32_t axi1_rd_limit_stall : 1; // Read stalled due to one AXI1 limit counter being reached
6198 uint32_t axi1_wr_stalled : 1; // Write transfer request stalled on awready low AXI1 (due to memory system)
6199 uint32_t axi1_w_stalled : 1; // Write transfer stalled on wready low AXI1 (due to memory system)
6200 uint32_t axi1_wr_limit_stall : 1; // Write stalled due to one AXI1 limit counter being reached
6201 uint32_t wgt_idle_c1 : 1; // When this bit is high means that the WGT block is not busy in generating
6202 // addresses for a WGT job
6203 uint32_t bas_idle_c1 : 1; // When this bit is high means that the BAS block is not busy in generating
6204 // addresses for a BAS job
6205 uint32_t ib0_ai_valid_c1 : 1; // Data for AI to be read in IFM input buffer 0 - Core 1
6206 uint32_t ib0_ai_ready_c1 : 1; // Data consumed from AI in IFM input buffer 0 - Core 1
6207 uint32_t ib1_ai_valid_c1 : 1; // Data for AI to be read in IFM input buffer 1 - Core 1
6208 uint32_t ib1_ai_ready_c1 : 1; // Data consumed from AI in IFM input buffer 1 - Core 1
6209 uint32_t ib0_ao_valid_c1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1
6210 uint32_t ib0_ao_ready_c1 : 1; // Data consumed from AO in IFM input buffer 0 - Core 1
6211 uint32_t ib1_ao_valid_c1 : 1; // Data for AO to be read in IFM input buffer 0 - Core 1
6212 uint32_t ib1_ao_ready_c1 : 1; // Data consumed from AO in IFM input buffer 1 - Core 1
6213 uint32_t ob0_valid_c1 : 1; // Data for DMA ready to be consumed in OFM output buffer 0 - Core 1
6214 uint32_t ob0_ready_c1 : 1; // Data consumed from DMA in OFM output buffer 0 - Core 1
6215 uint32_t ob1_valid_c1 : 1; // Data for DMA ready to be consumed in OFM output buffer 1 - Core 1
6216 uint32_t ob1_ready_c1 : 1; // Data consumed from DMA in OFM output buffer 1 - Core 1
6217 uint32_t wd_bitstream_valid_c1 : 1; // New weight word for WD to be consumed - Core 1
6218 uint32_t wd_bitstream_ready_c1 : 1; // Weight word consumed by WD - Core 1
6219 uint32_t bs_bitstream_valid_c1 : 1; // New BaS word for AO to be consumed - Core 1
6220 uint32_t bs_bitstream_ready_c1 : 1; // BaS word consumed by AO - Core 1
6221 uint32_t reserved0 : 8;
6222 };
6223 uint32_t word;
6224 };
6225#else
6226 private:
6227 uint32_t word0;
6228
6229 public:
6230 CONSTEXPR dma_status1_r() : word0(0) {}
6231 CONSTEXPR dma_status1_r(uint32_t init) : word0(init) {}
6232 CONSTEXPR void operator=(uint32_t value)
6233 {
6234 word0 = value;
6235 }
6236 void operator=(uint32_t value) volatile
6237 {
6238 word0 = value;
6239 }
6240 CONSTEXPR operator uint32_t()
6241 {
6242 return word0;
6243 }
6244 operator uint32_t() volatile
6245 {
6246 return word0;
6247 }
6248 dma_status1_r copy() volatile
6249 {
6250 return *this;
6251 }
6252 CONSTEXPR uint32_t get_axi0_wr_limit_stall() const
6253 {
6254 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
6255 return value;
6256 }
6257 uint32_t get_axi0_wr_limit_stall() const volatile
6258 {
6259 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
6260 return value;
6261 }
6262 CONSTEXPR dma_status1_r &set_axi0_wr_limit_stall(uint32_t value)
6263 {
6264 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
6265 return *this;
6266 }
6267 volatile dma_status1_r &set_axi0_wr_limit_stall(uint32_t value) volatile
6268 {
6269 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
6270 return *this;
6271 }
6272 CONSTEXPR uint32_t get_axi1_ar_stalled() const
6273 {
6274 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
6275 return value;
6276 }
6277 uint32_t get_axi1_ar_stalled() const volatile
6278 {
6279 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
6280 return value;
6281 }
6282 CONSTEXPR dma_status1_r &set_axi1_ar_stalled(uint32_t value)
6283 {
6284 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
6285 return *this;
6286 }
6287 volatile dma_status1_r &set_axi1_ar_stalled(uint32_t value) volatile
6288 {
6289 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
6290 return *this;
6291 }
6292 CONSTEXPR uint32_t get_axi1_rd_limit_stall() const
6293 {
6294 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
6295 return value;
6296 }
6297 uint32_t get_axi1_rd_limit_stall() const volatile
6298 {
6299 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
6300 return value;
6301 }
6302 CONSTEXPR dma_status1_r &set_axi1_rd_limit_stall(uint32_t value)
6303 {
6304 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
6305 return *this;
6306 }
6307 volatile dma_status1_r &set_axi1_rd_limit_stall(uint32_t value) volatile
6308 {
6309 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
6310 return *this;
6311 }
6312 CONSTEXPR uint32_t get_axi1_wr_stalled() const
6313 {
6314 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
6315 return value;
6316 }
6317 uint32_t get_axi1_wr_stalled() const volatile
6318 {
6319 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
6320 return value;
6321 }
6322 CONSTEXPR dma_status1_r &set_axi1_wr_stalled(uint32_t value)
6323 {
6324 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
6325 return *this;
6326 }
6327 volatile dma_status1_r &set_axi1_wr_stalled(uint32_t value) volatile
6328 {
6329 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
6330 return *this;
6331 }
6332 CONSTEXPR uint32_t get_axi1_w_stalled() const
6333 {
6334 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
6335 return value;
6336 }
6337 uint32_t get_axi1_w_stalled() const volatile
6338 {
6339 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
6340 return value;
6341 }
6342 CONSTEXPR dma_status1_r &set_axi1_w_stalled(uint32_t value)
6343 {
6344 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
6345 return *this;
6346 }
6347 volatile dma_status1_r &set_axi1_w_stalled(uint32_t value) volatile
6348 {
6349 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
6350 return *this;
6351 }
6352 CONSTEXPR uint32_t get_axi1_wr_limit_stall() const
6353 {
6354 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
6355 return value;
6356 }
6357 uint32_t get_axi1_wr_limit_stall() const volatile
6358 {
6359 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
6360 return value;
6361 }
6362 CONSTEXPR dma_status1_r &set_axi1_wr_limit_stall(uint32_t value)
6363 {
6364 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
6365 return *this;
6366 }
6367 volatile dma_status1_r &set_axi1_wr_limit_stall(uint32_t value) volatile
6368 {
6369 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
6370 return *this;
6371 }
6372 CONSTEXPR uint32_t get_wgt_idle_c1() const
6373 {
6374 uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
6375 return value;
6376 }
6377 uint32_t get_wgt_idle_c1() const volatile
6378 {
6379 uint32_t value = ((1U << 1) - 1) & (word0 >> 6);
6380 return value;
6381 }
6382 CONSTEXPR dma_status1_r &set_wgt_idle_c1(uint32_t value)
6383 {
6384 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
6385 return *this;
6386 }
6387 volatile dma_status1_r &set_wgt_idle_c1(uint32_t value) volatile
6388 {
6389 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) & value) << 6);
6390 return *this;
6391 }
6392 CONSTEXPR uint32_t get_bas_idle_c1() const
6393 {
6394 uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
6395 return value;
6396 }
6397 uint32_t get_bas_idle_c1() const volatile
6398 {
6399 uint32_t value = ((1U << 1) - 1) & (word0 >> 7);
6400 return value;
6401 }
6402 CONSTEXPR dma_status1_r &set_bas_idle_c1(uint32_t value)
6403 {
6404 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
6405 return *this;
6406 }
6407 volatile dma_status1_r &set_bas_idle_c1(uint32_t value) volatile
6408 {
6409 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) & value) << 7);
6410 return *this;
6411 }
6412 CONSTEXPR uint32_t get_ib0_ai_valid_c1() const
6413 {
6414 uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
6415 return value;
6416 }
6417 uint32_t get_ib0_ai_valid_c1() const volatile
6418 {
6419 uint32_t value = ((1U << 1) - 1) & (word0 >> 8);
6420 return value;
6421 }
6422 CONSTEXPR dma_status1_r &set_ib0_ai_valid_c1(uint32_t value)
6423 {
6424 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
6425 return *this;
6426 }
6427 volatile dma_status1_r &set_ib0_ai_valid_c1(uint32_t value) volatile
6428 {
6429 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) & value) << 8);
6430 return *this;
6431 }
6432 CONSTEXPR uint32_t get_ib0_ai_ready_c1() const
6433 {
6434 uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
6435 return value;
6436 }
6437 uint32_t get_ib0_ai_ready_c1() const volatile
6438 {
6439 uint32_t value = ((1U << 1) - 1) & (word0 >> 9);
6440 return value;
6441 }
6442 CONSTEXPR dma_status1_r &set_ib0_ai_ready_c1(uint32_t value)
6443 {
6444 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
6445 return *this;
6446 }
6447 volatile dma_status1_r &set_ib0_ai_ready_c1(uint32_t value) volatile
6448 {
6449 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) & value) << 9);
6450 return *this;
6451 }
6452 CONSTEXPR uint32_t get_ib1_ai_valid_c1() const
6453 {
6454 uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
6455 return value;
6456 }
6457 uint32_t get_ib1_ai_valid_c1() const volatile
6458 {
6459 uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
6460 return value;
6461 }
6462 CONSTEXPR dma_status1_r &set_ib1_ai_valid_c1(uint32_t value)
6463 {
6464 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
6465 return *this;
6466 }
6467 volatile dma_status1_r &set_ib1_ai_valid_c1(uint32_t value) volatile
6468 {
6469 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
6470 return *this;
6471 }
6472 CONSTEXPR uint32_t get_ib1_ai_ready_c1() const
6473 {
6474 uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
6475 return value;
6476 }
6477 uint32_t get_ib1_ai_ready_c1() const volatile
6478 {
6479 uint32_t value = ((1U << 1) - 1) & (word0 >> 11);
6480 return value;
6481 }
6482 CONSTEXPR dma_status1_r &set_ib1_ai_ready_c1(uint32_t value)
6483 {
6484 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
6485 return *this;
6486 }
6487 volatile dma_status1_r &set_ib1_ai_ready_c1(uint32_t value) volatile
6488 {
6489 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) & value) << 11);
6490 return *this;
6491 }
6492 CONSTEXPR uint32_t get_ib0_ao_valid_c1() const
6493 {
6494 uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
6495 return value;
6496 }
6497 uint32_t get_ib0_ao_valid_c1() const volatile
6498 {
6499 uint32_t value = ((1U << 1) - 1) & (word0 >> 12);
6500 return value;
6501 }
6502 CONSTEXPR dma_status1_r &set_ib0_ao_valid_c1(uint32_t value)
6503 {
6504 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
6505 return *this;
6506 }
6507 volatile dma_status1_r &set_ib0_ao_valid_c1(uint32_t value) volatile
6508 {
6509 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) & value) << 12);
6510 return *this;
6511 }
6512 CONSTEXPR uint32_t get_ib0_ao_ready_c1() const
6513 {
6514 uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
6515 return value;
6516 }
6517 uint32_t get_ib0_ao_ready_c1() const volatile
6518 {
6519 uint32_t value = ((1U << 1) - 1) & (word0 >> 13);
6520 return value;
6521 }
6522 CONSTEXPR dma_status1_r &set_ib0_ao_ready_c1(uint32_t value)
6523 {
6524 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
6525 return *this;
6526 }
6527 volatile dma_status1_r &set_ib0_ao_ready_c1(uint32_t value) volatile
6528 {
6529 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) & value) << 13);
6530 return *this;
6531 }
6532 CONSTEXPR uint32_t get_ib1_ao_valid_c1() const
6533 {
6534 uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
6535 return value;
6536 }
6537 uint32_t get_ib1_ao_valid_c1() const volatile
6538 {
6539 uint32_t value = ((1U << 1) - 1) & (word0 >> 14);
6540 return value;
6541 }
6542 CONSTEXPR dma_status1_r &set_ib1_ao_valid_c1(uint32_t value)
6543 {
6544 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
6545 return *this;
6546 }
6547 volatile dma_status1_r &set_ib1_ao_valid_c1(uint32_t value) volatile
6548 {
6549 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) & value) << 14);
6550 return *this;
6551 }
6552 CONSTEXPR uint32_t get_ib1_ao_ready_c1() const
6553 {
6554 uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
6555 return value;
6556 }
6557 uint32_t get_ib1_ao_ready_c1() const volatile
6558 {
6559 uint32_t value = ((1U << 1) - 1) & (word0 >> 15);
6560 return value;
6561 }
6562 CONSTEXPR dma_status1_r &set_ib1_ao_ready_c1(uint32_t value)
6563 {
6564 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
6565 return *this;
6566 }
6567 volatile dma_status1_r &set_ib1_ao_ready_c1(uint32_t value) volatile
6568 {
6569 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) & value) << 15);
6570 return *this;
6571 }
6572 CONSTEXPR uint32_t get_ob0_valid_c1() const
6573 {
6574 uint32_t value = ((1U << 1) - 1) & (word0 >> 16);
6575 return value;
6576 }
6577 uint32_t get_ob0_valid_c1() const volatile
6578 {
6579 uint32_t value = ((1U << 1) - 1) & (word0 >> 16);
6580 return value;
6581 }
6582 CONSTEXPR dma_status1_r &set_ob0_valid_c1(uint32_t value)
6583 {
6584 word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16);
6585 return *this;
6586 }
6587 volatile dma_status1_r &set_ob0_valid_c1(uint32_t value) volatile
6588 {
6589 word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) & value) << 16);
6590 return *this;
6591 }
6592 CONSTEXPR uint32_t get_ob0_ready_c1() const
6593 {
6594 uint32_t value = ((1U << 1) - 1) & (word0 >> 17);
6595 return value;
6596 }
6597 uint32_t get_ob0_ready_c1() const volatile
6598 {
6599 uint32_t value = ((1U << 1) - 1) & (word0 >> 17);
6600 return value;
6601 }
6602 CONSTEXPR dma_status1_r &set_ob0_ready_c1(uint32_t value)
6603 {
6604 word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17);
6605 return *this;
6606 }
6607 volatile dma_status1_r &set_ob0_ready_c1(uint32_t value) volatile
6608 {
6609 word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) & value) << 17);
6610 return *this;
6611 }
6612 CONSTEXPR uint32_t get_ob1_valid_c1() const
6613 {
6614 uint32_t value = ((1U << 1) - 1) & (word0 >> 18);
6615 return value;
6616 }
6617 uint32_t get_ob1_valid_c1() const volatile
6618 {
6619 uint32_t value = ((1U << 1) - 1) & (word0 >> 18);
6620 return value;
6621 }
6622 CONSTEXPR dma_status1_r &set_ob1_valid_c1(uint32_t value)
6623 {
6624 word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18);
6625 return *this;
6626 }
6627 volatile dma_status1_r &set_ob1_valid_c1(uint32_t value) volatile
6628 {
6629 word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) & value) << 18);
6630 return *this;
6631 }
6632 CONSTEXPR uint32_t get_ob1_ready_c1() const
6633 {
6634 uint32_t value = ((1U << 1) - 1) & (word0 >> 19);
6635 return value;
6636 }
6637 uint32_t get_ob1_ready_c1() const volatile
6638 {
6639 uint32_t value = ((1U << 1) - 1) & (word0 >> 19);
6640 return value;
6641 }
6642 CONSTEXPR dma_status1_r &set_ob1_ready_c1(uint32_t value)
6643 {
6644 word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19);
6645 return *this;
6646 }
6647 volatile dma_status1_r &set_ob1_ready_c1(uint32_t value) volatile
6648 {
6649 word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) & value) << 19);
6650 return *this;
6651 }
6652 CONSTEXPR uint32_t get_wd_bitstream_valid_c1() const
6653 {
6654 uint32_t value = ((1U << 1) - 1) & (word0 >> 20);
6655 return value;
6656 }
6657 uint32_t get_wd_bitstream_valid_c1() const volatile
6658 {
6659 uint32_t value = ((1U << 1) - 1) & (word0 >> 20);
6660 return value;
6661 }
6662 CONSTEXPR dma_status1_r &set_wd_bitstream_valid_c1(uint32_t value)
6663 {
6664 word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20);
6665 return *this;
6666 }
6667 volatile dma_status1_r &set_wd_bitstream_valid_c1(uint32_t value) volatile
6668 {
6669 word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) & value) << 20);
6670 return *this;
6671 }
6672 CONSTEXPR uint32_t get_wd_bitstream_ready_c1() const
6673 {
6674 uint32_t value = ((1U << 1) - 1) & (word0 >> 21);
6675 return value;
6676 }
6677 uint32_t get_wd_bitstream_ready_c1() const volatile
6678 {
6679 uint32_t value = ((1U << 1) - 1) & (word0 >> 21);
6680 return value;
6681 }
6682 CONSTEXPR dma_status1_r &set_wd_bitstream_ready_c1(uint32_t value)
6683 {
6684 word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21);
6685 return *this;
6686 }
6687 volatile dma_status1_r &set_wd_bitstream_ready_c1(uint32_t value) volatile
6688 {
6689 word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) & value) << 21);
6690 return *this;
6691 }
6692 CONSTEXPR uint32_t get_bs_bitstream_valid_c1() const
6693 {
6694 uint32_t value = ((1U << 1) - 1) & (word0 >> 22);
6695 return value;
6696 }
6697 uint32_t get_bs_bitstream_valid_c1() const volatile
6698 {
6699 uint32_t value = ((1U << 1) - 1) & (word0 >> 22);
6700 return value;
6701 }
6702 CONSTEXPR dma_status1_r &set_bs_bitstream_valid_c1(uint32_t value)
6703 {
6704 word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22);
6705 return *this;
6706 }
6707 volatile dma_status1_r &set_bs_bitstream_valid_c1(uint32_t value) volatile
6708 {
6709 word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) & value) << 22);
6710 return *this;
6711 }
6712 CONSTEXPR uint32_t get_bs_bitstream_ready_c1() const
6713 {
6714 uint32_t value = ((1U << 1) - 1) & (word0 >> 23);
6715 return value;
6716 }
6717 uint32_t get_bs_bitstream_ready_c1() const volatile
6718 {
6719 uint32_t value = ((1U << 1) - 1) & (word0 >> 23);
6720 return value;
6721 }
6722 CONSTEXPR dma_status1_r &set_bs_bitstream_ready_c1(uint32_t value)
6723 {
6724 word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23);
6725 return *this;
6726 }
6727 volatile dma_status1_r &set_bs_bitstream_ready_c1(uint32_t value) volatile
6728 {
6729 word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) & value) << 23);
6730 return *this;
6731 }
6732#endif
6733};
6734
6735// clkforce_r - Force clocks on for clock gating
6736struct clkforce_r
6737{
6738#ifndef __cplusplus
6739 union
6740 {
6741 struct
6742 {
6743 uint32_t top_level_clk : 1; // set to 1 to force on TOP level clock
6744 uint32_t cc_clk : 1; // set to 1 to force on CC clock
6745 uint32_t dma_clk : 1; // set to 1 to force on DMA clock
6746 uint32_t mac_clk : 1; // set to 1 to force on MAC clock
6747 uint32_t ao_clk : 1; // set to 1 to force on AO clock
6748 uint32_t wd_clk : 1; // set to 1 to force on WD clock
6749 uint32_t reserved0 : 26;
6750 };
6751 uint32_t word;
6752 };
6753#else
6754 private:
6755 uint32_t word0;
6756
6757 public:
6758 CONSTEXPR clkforce_r() : word0(0) {}
6759 CONSTEXPR clkforce_r(uint32_t init) : word0(init) {}
6760 CONSTEXPR void operator=(uint32_t value)
6761 {
6762 word0 = value;
6763 }
6764 void operator=(uint32_t value) volatile
6765 {
6766 word0 = value;
6767 }
6768 CONSTEXPR operator uint32_t()
6769 {
6770 return word0;
6771 }
6772 operator uint32_t() volatile
6773 {
6774 return word0;
6775 }
6776 clkforce_r copy() volatile
6777 {
6778 return *this;
6779 }
6780 CONSTEXPR uint32_t get_top_level_clk() const
6781 {
6782 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
6783 return value;
6784 }
6785 uint32_t get_top_level_clk() const volatile
6786 {
6787 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
6788 return value;
6789 }
6790 CONSTEXPR clkforce_r &set_top_level_clk(uint32_t value)
6791 {
6792 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
6793 return *this;
6794 }
6795 volatile clkforce_r &set_top_level_clk(uint32_t value) volatile
6796 {
6797 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
6798 return *this;
6799 }
6800 CONSTEXPR uint32_t get_cc_clk() const
6801 {
6802 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
6803 return value;
6804 }
6805 uint32_t get_cc_clk() const volatile
6806 {
6807 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
6808 return value;
6809 }
6810 CONSTEXPR clkforce_r &set_cc_clk(uint32_t value)
6811 {
6812 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
6813 return *this;
6814 }
6815 volatile clkforce_r &set_cc_clk(uint32_t value) volatile
6816 {
6817 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
6818 return *this;
6819 }
6820 CONSTEXPR uint32_t get_dma_clk() const
6821 {
6822 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
6823 return value;
6824 }
6825 uint32_t get_dma_clk() const volatile
6826 {
6827 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
6828 return value;
6829 }
6830 CONSTEXPR clkforce_r &set_dma_clk(uint32_t value)
6831 {
6832 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
6833 return *this;
6834 }
6835 volatile clkforce_r &set_dma_clk(uint32_t value) volatile
6836 {
6837 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
6838 return *this;
6839 }
6840 CONSTEXPR uint32_t get_mac_clk() const
6841 {
6842 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
6843 return value;
6844 }
6845 uint32_t get_mac_clk() const volatile
6846 {
6847 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
6848 return value;
6849 }
6850 CONSTEXPR clkforce_r &set_mac_clk(uint32_t value)
6851 {
6852 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
6853 return *this;
6854 }
6855 volatile clkforce_r &set_mac_clk(uint32_t value) volatile
6856 {
6857 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
6858 return *this;
6859 }
6860 CONSTEXPR uint32_t get_ao_clk() const
6861 {
6862 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
6863 return value;
6864 }
6865 uint32_t get_ao_clk() const volatile
6866 {
6867 uint32_t value = ((1U << 1) - 1) & (word0 >> 4);
6868 return value;
6869 }
6870 CONSTEXPR clkforce_r &set_ao_clk(uint32_t value)
6871 {
6872 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
6873 return *this;
6874 }
6875 volatile clkforce_r &set_ao_clk(uint32_t value) volatile
6876 {
6877 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) & value) << 4);
6878 return *this;
6879 }
6880 CONSTEXPR uint32_t get_wd_clk() const
6881 {
6882 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
6883 return value;
6884 }
6885 uint32_t get_wd_clk() const volatile
6886 {
6887 uint32_t value = ((1U << 1) - 1) & (word0 >> 5);
6888 return value;
6889 }
6890 CONSTEXPR clkforce_r &set_wd_clk(uint32_t value)
6891 {
6892 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
6893 return *this;
6894 }
6895 volatile clkforce_r &set_wd_clk(uint32_t value) volatile
6896 {
6897 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) & value) << 5);
6898 return *this;
6899 }
6900#endif
6901};
6902
6903// debug_address_r - Set debug address for register reads 0x400-0x7FF. The address must be 1KB aligned
6904struct debug_address_r
6905{
6906#ifndef __cplusplus
6907 union
6908 {
6909 struct
6910 {
6911 uint32_t addr : 32; // Register address
6912 };
6913 uint32_t word;
6914 };
6915#else
6916 private:
6917 uint32_t word0;
6918
6919 public:
6920 CONSTEXPR debug_address_r() : word0(0) {}
6921 CONSTEXPR debug_address_r(uint32_t init) : word0(init) {}
6922 CONSTEXPR void operator=(uint32_t value)
6923 {
6924 word0 = value;
6925 }
6926 void operator=(uint32_t value) volatile
6927 {
6928 word0 = value;
6929 }
6930 CONSTEXPR operator uint32_t()
6931 {
6932 return word0;
6933 }
6934 operator uint32_t() volatile
6935 {
6936 return word0;
6937 }
6938 debug_address_r copy() volatile
6939 {
6940 return *this;
6941 }
6942 CONSTEXPR uint32_t get_addr() const
6943 {
6944 uint32_t value = word0;
6945 return value;
6946 }
6947 uint32_t get_addr() const volatile
6948 {
6949 uint32_t value = word0;
6950 return value;
6951 }
6952 CONSTEXPR debug_address_r &set_addr(uint32_t value)
6953 {
6954 word0 = value;
6955 return *this;
6956 }
6957 volatile debug_address_r &set_addr(uint32_t value) volatile
6958 {
6959 word0 = value;
6960 return *this;
6961 }
6962#endif
6963};
6964
6965// debug_misc_r - 32-bit read/write register for driver debug use. This does not affect NPU function
6966struct debug_misc_r
6967{
6968#ifndef __cplusplus
6969 union
6970 {
6971 struct
6972 {
6973 uint32_t misc : 32; // Debug misc
6974 };
6975 uint32_t word;
6976 };
6977#else
6978 private:
6979 uint32_t word0;
6980
6981 public:
6982 CONSTEXPR debug_misc_r() : word0(0) {}
6983 CONSTEXPR debug_misc_r(uint32_t init) : word0(init) {}
6984 CONSTEXPR void operator=(uint32_t value)
6985 {
6986 word0 = value;
6987 }
6988 void operator=(uint32_t value) volatile
6989 {
6990 word0 = value;
6991 }
6992 CONSTEXPR operator uint32_t()
6993 {
6994 return word0;
6995 }
6996 operator uint32_t() volatile
6997 {
6998 return word0;
6999 }
7000 debug_misc_r copy() volatile
7001 {
7002 return *this;
7003 }
7004 CONSTEXPR uint32_t get_misc() const
7005 {
7006 uint32_t value = word0;
7007 return value;
7008 }
7009 uint32_t get_misc() const volatile
7010 {
7011 uint32_t value = word0;
7012 return value;
7013 }
7014 CONSTEXPR debug_misc_r &set_misc(uint32_t value)
7015 {
7016 word0 = value;
7017 return *this;
7018 }
7019 volatile debug_misc_r &set_misc(uint32_t value) volatile
7020 {
7021 word0 = value;
7022 return *this;
7023 }
7024#endif
7025};
7026
7027// debugcore_r - Select core number for debug registers (0x200-0x2FF) and RAM reads (0x400-0x7FF). Value is 0 or 1
7029{
7030#ifndef __cplusplus
7031 union
7032 {
7033 struct
7034 {
7035 uint32_t core : 32; // Debug core
7036 };
7037 uint32_t word;
7038 };
7039#else
7040 private:
7041 uint32_t word0;
7042
7043 public:
7044 CONSTEXPR debugcore_r() : word0(0) {}
7045 CONSTEXPR debugcore_r(uint32_t init) : word0(init) {}
7046 CONSTEXPR void operator=(uint32_t value)
7047 {
7048 word0 = value;
7049 }
7050 void operator=(uint32_t value) volatile
7051 {
7052 word0 = value;
7053 }
7054 CONSTEXPR operator uint32_t()
7055 {
7056 return word0;
7057 }
7058 operator uint32_t() volatile
7059 {
7060 return word0;
7061 }
7062 debugcore_r copy() volatile
7063 {
7064 return *this;
7065 }
7066 CONSTEXPR uint32_t get_core() const
7067 {
7068 uint32_t value = word0;
7069 return value;
7070 }
7071 uint32_t get_core() const volatile
7072 {
7073 uint32_t value = word0;
7074 return value;
7075 }
7076 CONSTEXPR debugcore_r &set_core(uint32_t value)
7077 {
7078 word0 = value;
7079 return *this;
7080 }
7081 volatile debugcore_r &set_core(uint32_t value) volatile
7082 {
7083 word0 = value;
7084 return *this;
7085 }
7086#endif
7087};
7088
7089// debug_block_r - Set from which of four block banks the TSU registers are read. 0 = read from the current bank 256+n =
7090// force to read from bank n where n is in the range 0 to 3
7091struct debug_block_r
7092{
7093#ifndef __cplusplus
7094 union
7095 {
7096 struct
7097 {
7098 uint32_t block : 32; // Debug block
7099 };
7100 uint32_t word;
7101 };
7102#else
7103 private:
7104 uint32_t word0;
7105
7106 public:
7107 CONSTEXPR debug_block_r() : word0(0) {}
7108 CONSTEXPR debug_block_r(uint32_t init) : word0(init) {}
7109 CONSTEXPR void operator=(uint32_t value)
7110 {
7111 word0 = value;
7112 }
7113 void operator=(uint32_t value) volatile
7114 {
7115 word0 = value;
7116 }
7117 CONSTEXPR operator uint32_t()
7118 {
7119 return word0;
7120 }
7121 operator uint32_t() volatile
7122 {
7123 return word0;
7124 }
7125 debug_block_r copy() volatile
7126 {
7127 return *this;
7128 }
7129 CONSTEXPR uint32_t get_block() const
7130 {
7131 uint32_t value = word0;
7132 return value;
7133 }
7134 uint32_t get_block() const volatile
7135 {
7136 uint32_t value = word0;
7137 return value;
7138 }
7139 CONSTEXPR debug_block_r &set_block(uint32_t value)
7140 {
7141 word0 = value;
7142 return *this;
7143 }
7144 volatile debug_block_r &set_block(uint32_t value) volatile
7145 {
7146 word0 = value;
7147 return *this;
7148 }
7149#endif
7150};
7151
7152// pmcr_r - PMU Register control
7153struct pmcr_r
7154{
7155#ifndef __cplusplus
7156 union
7157 {
7158 struct
7159 {
7160 uint32_t cnt_en : 1; // Enable counter
7161 uint32_t event_cnt_rst : 1; // Reset event counter
7162 uint32_t cycle_cnt_rst : 1; // Reset cycle counter
7163 uint32_t mask_en : 1; // PMU can be enabled/disabled by command stream operation NPU_OP_PMU_MASK
7164 uint32_t reserved0 : 7;
7165 uint32_t num_event_cnt : 5; // Number of event counters
7166 uint32_t reserved1 : 16;
7167 };
7168 uint32_t word;
7169 };
7170#else
7171 private:
7172 uint32_t word0;
7173
7174 public:
7175 CONSTEXPR pmcr_r() : word0(8192) {}
7176 CONSTEXPR pmcr_r(uint32_t init) : word0(init) {}
7177 CONSTEXPR void operator=(uint32_t value)
7178 {
7179 word0 = value;
7180 }
7181 void operator=(uint32_t value) volatile
7182 {
7183 word0 = value;
7184 }
7185 CONSTEXPR operator uint32_t()
7186 {
7187 return word0;
7188 }
7189 operator uint32_t() volatile
7190 {
7191 return word0;
7192 }
7193 pmcr_r copy() volatile
7194 {
7195 return *this;
7196 }
7197 CONSTEXPR uint32_t get_cnt_en() const
7198 {
7199 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7200 return value;
7201 }
7202 uint32_t get_cnt_en() const volatile
7203 {
7204 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7205 return value;
7206 }
7207 CONSTEXPR pmcr_r &set_cnt_en(uint32_t value)
7208 {
7209 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7210 return *this;
7211 }
7212 volatile pmcr_r &set_cnt_en(uint32_t value) volatile
7213 {
7214 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7215 return *this;
7216 }
7217 CONSTEXPR uint32_t get_event_cnt_rst() const
7218 {
7219 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7220 return value;
7221 }
7222 uint32_t get_event_cnt_rst() const volatile
7223 {
7224 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7225 return value;
7226 }
7227 CONSTEXPR pmcr_r &set_event_cnt_rst(uint32_t value)
7228 {
7229 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7230 return *this;
7231 }
7232 volatile pmcr_r &set_event_cnt_rst(uint32_t value) volatile
7233 {
7234 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7235 return *this;
7236 }
7237 CONSTEXPR uint32_t get_cycle_cnt_rst() const
7238 {
7239 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7240 return value;
7241 }
7242 uint32_t get_cycle_cnt_rst() const volatile
7243 {
7244 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7245 return value;
7246 }
7247 CONSTEXPR pmcr_r &set_cycle_cnt_rst(uint32_t value)
7248 {
7249 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7250 return *this;
7251 }
7252 volatile pmcr_r &set_cycle_cnt_rst(uint32_t value) volatile
7253 {
7254 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7255 return *this;
7256 }
7257 CONSTEXPR uint32_t get_mask_en() const
7258 {
7259 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7260 return value;
7261 }
7262 uint32_t get_mask_en() const volatile
7263 {
7264 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7265 return value;
7266 }
7267 CONSTEXPR pmcr_r &set_mask_en(uint32_t value)
7268 {
7269 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7270 return *this;
7271 }
7272 volatile pmcr_r &set_mask_en(uint32_t value) volatile
7273 {
7274 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7275 return *this;
7276 }
7277 CONSTEXPR uint32_t get_num_event_cnt() const
7278 {
7279 uint32_t value = ((1U << 5) - 1) & (word0 >> 11);
7280 return value;
7281 }
7282 uint32_t get_num_event_cnt() const volatile
7283 {
7284 uint32_t value = ((1U << 5) - 1) & (word0 >> 11);
7285 return value;
7286 }
7287 CONSTEXPR pmcr_r &set_num_event_cnt(uint32_t value)
7288 {
7289 word0 = (((~((1U << 5) - 1)) << 11) & word0) | ((((1U << 5) - 1) & value) << 11);
7290 return *this;
7291 }
7292 volatile pmcr_r &set_num_event_cnt(uint32_t value) volatile
7293 {
7294 word0 = (((~((1U << 5) - 1)) << 11) & word0) | ((((1U << 5) - 1) & value) << 11);
7295 return *this;
7296 }
7297#endif
7298};
7299
7300// pmcntenset_r - Count enable set register
7301struct pmcntenset_r
7302{
7303#ifndef __cplusplus
7304 union
7305 {
7306 struct
7307 {
7308 uint32_t EVENT_CNT_0 : 1; // Event counter enable bit for PMEVCNTR0
7309 uint32_t EVENT_CNT_1 : 1; // Event counter enable bit for PMEVCNTR1
7310 uint32_t EVENT_CNT_2 : 1; // Event counter enable bit for PMEVCNTR2
7311 uint32_t EVENT_CNT_3 : 1; // Event counter enable bit for PMEVCNTR3
7312 uint32_t reserved0 : 27;
7313 uint32_t CYCLE_CNT : 1; // PMCCNTR enable bit
7314 };
7315 uint32_t word;
7316 };
7317#else
7318 private:
7319 uint32_t word0;
7320
7321 public:
7322 CONSTEXPR pmcntenset_r() : word0(0) {}
7323 CONSTEXPR pmcntenset_r(uint32_t init) : word0(init) {}
7324 CONSTEXPR void operator=(uint32_t value)
7325 {
7326 word0 = value;
7327 }
7328 void operator=(uint32_t value) volatile
7329 {
7330 word0 = value;
7331 }
7332 CONSTEXPR operator uint32_t()
7333 {
7334 return word0;
7335 }
7336 operator uint32_t() volatile
7337 {
7338 return word0;
7339 }
7340 pmcntenset_r copy() volatile
7341 {
7342 return *this;
7343 }
7344 CONSTEXPR uint32_t get_EVENT_CNT_0() const
7345 {
7346 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7347 return value;
7348 }
7349 uint32_t get_EVENT_CNT_0() const volatile
7350 {
7351 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7352 return value;
7353 }
7354 CONSTEXPR pmcntenset_r &set_EVENT_CNT_0(uint32_t value)
7355 {
7356 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7357 return *this;
7358 }
7359 volatile pmcntenset_r &set_EVENT_CNT_0(uint32_t value) volatile
7360 {
7361 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7362 return *this;
7363 }
7364 CONSTEXPR uint32_t get_EVENT_CNT_1() const
7365 {
7366 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7367 return value;
7368 }
7369 uint32_t get_EVENT_CNT_1() const volatile
7370 {
7371 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7372 return value;
7373 }
7374 CONSTEXPR pmcntenset_r &set_EVENT_CNT_1(uint32_t value)
7375 {
7376 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7377 return *this;
7378 }
7379 volatile pmcntenset_r &set_EVENT_CNT_1(uint32_t value) volatile
7380 {
7381 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7382 return *this;
7383 }
7384 CONSTEXPR uint32_t get_EVENT_CNT_2() const
7385 {
7386 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7387 return value;
7388 }
7389 uint32_t get_EVENT_CNT_2() const volatile
7390 {
7391 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7392 return value;
7393 }
7394 CONSTEXPR pmcntenset_r &set_EVENT_CNT_2(uint32_t value)
7395 {
7396 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7397 return *this;
7398 }
7399 volatile pmcntenset_r &set_EVENT_CNT_2(uint32_t value) volatile
7400 {
7401 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7402 return *this;
7403 }
7404 CONSTEXPR uint32_t get_EVENT_CNT_3() const
7405 {
7406 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7407 return value;
7408 }
7409 uint32_t get_EVENT_CNT_3() const volatile
7410 {
7411 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7412 return value;
7413 }
7414 CONSTEXPR pmcntenset_r &set_EVENT_CNT_3(uint32_t value)
7415 {
7416 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7417 return *this;
7418 }
7419 volatile pmcntenset_r &set_EVENT_CNT_3(uint32_t value) volatile
7420 {
7421 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7422 return *this;
7423 }
7424 CONSTEXPR uint32_t get_CYCLE_CNT() const
7425 {
7426 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7427 return value;
7428 }
7429 uint32_t get_CYCLE_CNT() const volatile
7430 {
7431 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7432 return value;
7433 }
7434 CONSTEXPR pmcntenset_r &set_CYCLE_CNT(uint32_t value)
7435 {
7436 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7437 return *this;
7438 }
7439 volatile pmcntenset_r &set_CYCLE_CNT(uint32_t value) volatile
7440 {
7441 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7442 return *this;
7443 }
7444#endif
7445};
7446
7447// pmcntenclr_r - Count enable clear register
7448struct pmcntenclr_r
7449{
7450#ifndef __cplusplus
7451 union
7452 {
7453 struct
7454 {
7455 uint32_t EVENT_CNT_0 : 1; // Event counter disable bit for PMEVCNTR0
7456 uint32_t EVENT_CNT_1 : 1; // Event counter disable bit for PMEVCNTR1
7457 uint32_t EVENT_CNT_2 : 1; // Event counter disable bit for PMEVCNTR2
7458 uint32_t EVENT_CNT_3 : 1; // Event counter disable bit for PMEVCNTR3
7459 uint32_t reserved0 : 27;
7460 uint32_t CYCLE_CNT : 1; // PMCCNTR disable bit
7461 };
7462 uint32_t word;
7463 };
7464#else
7465 private:
7466 uint32_t word0;
7467
7468 public:
7469 CONSTEXPR pmcntenclr_r() : word0(0) {}
7470 CONSTEXPR pmcntenclr_r(uint32_t init) : word0(init) {}
7471 CONSTEXPR void operator=(uint32_t value)
7472 {
7473 word0 = value;
7474 }
7475 void operator=(uint32_t value) volatile
7476 {
7477 word0 = value;
7478 }
7479 CONSTEXPR operator uint32_t()
7480 {
7481 return word0;
7482 }
7483 operator uint32_t() volatile
7484 {
7485 return word0;
7486 }
7487 pmcntenclr_r copy() volatile
7488 {
7489 return *this;
7490 }
7491 CONSTEXPR uint32_t get_EVENT_CNT_0() const
7492 {
7493 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7494 return value;
7495 }
7496 uint32_t get_EVENT_CNT_0() const volatile
7497 {
7498 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7499 return value;
7500 }
7501 CONSTEXPR pmcntenclr_r &set_EVENT_CNT_0(uint32_t value)
7502 {
7503 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7504 return *this;
7505 }
7506 volatile pmcntenclr_r &set_EVENT_CNT_0(uint32_t value) volatile
7507 {
7508 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7509 return *this;
7510 }
7511 CONSTEXPR uint32_t get_EVENT_CNT_1() const
7512 {
7513 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7514 return value;
7515 }
7516 uint32_t get_EVENT_CNT_1() const volatile
7517 {
7518 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7519 return value;
7520 }
7521 CONSTEXPR pmcntenclr_r &set_EVENT_CNT_1(uint32_t value)
7522 {
7523 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7524 return *this;
7525 }
7526 volatile pmcntenclr_r &set_EVENT_CNT_1(uint32_t value) volatile
7527 {
7528 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7529 return *this;
7530 }
7531 CONSTEXPR uint32_t get_EVENT_CNT_2() const
7532 {
7533 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7534 return value;
7535 }
7536 uint32_t get_EVENT_CNT_2() const volatile
7537 {
7538 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7539 return value;
7540 }
7541 CONSTEXPR pmcntenclr_r &set_EVENT_CNT_2(uint32_t value)
7542 {
7543 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7544 return *this;
7545 }
7546 volatile pmcntenclr_r &set_EVENT_CNT_2(uint32_t value) volatile
7547 {
7548 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7549 return *this;
7550 }
7551 CONSTEXPR uint32_t get_EVENT_CNT_3() const
7552 {
7553 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7554 return value;
7555 }
7556 uint32_t get_EVENT_CNT_3() const volatile
7557 {
7558 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7559 return value;
7560 }
7561 CONSTEXPR pmcntenclr_r &set_EVENT_CNT_3(uint32_t value)
7562 {
7563 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7564 return *this;
7565 }
7566 volatile pmcntenclr_r &set_EVENT_CNT_3(uint32_t value) volatile
7567 {
7568 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7569 return *this;
7570 }
7571 CONSTEXPR uint32_t get_CYCLE_CNT() const
7572 {
7573 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7574 return value;
7575 }
7576 uint32_t get_CYCLE_CNT() const volatile
7577 {
7578 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7579 return value;
7580 }
7581 CONSTEXPR pmcntenclr_r &set_CYCLE_CNT(uint32_t value)
7582 {
7583 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7584 return *this;
7585 }
7586 volatile pmcntenclr_r &set_CYCLE_CNT(uint32_t value) volatile
7587 {
7588 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7589 return *this;
7590 }
7591#endif
7592};
7593
7594// pmovsset_r - Overflow flag status set register
7595struct pmovsset_r
7596{
7597#ifndef __cplusplus
7598 union
7599 {
7600 struct
7601 {
7602 uint32_t EVENT_CNT_0_OVF : 1; // Event counter overflow set bit for PMEVCNTR0
7603 uint32_t EVENT_CNT_1_OVF : 1; // Event counter overflow set bit for PMEVCNTR1
7604 uint32_t EVENT_CNT_2_OVF : 1; // Event counter overflow set bit for PMEVCNTR2
7605 uint32_t EVENT_CNT_3_OVF : 1; // Event counter overflow set bit for PMEVCNTR3
7606 uint32_t reserved0 : 27;
7607 uint32_t CYCLE_CNT_OVF : 1; // PMCCNTR overflow set bit
7608 };
7609 uint32_t word;
7610 };
7611#else
7612 private:
7613 uint32_t word0;
7614
7615 public:
7616 CONSTEXPR pmovsset_r() : word0(0) {}
7617 CONSTEXPR pmovsset_r(uint32_t init) : word0(init) {}
7618 CONSTEXPR void operator=(uint32_t value)
7619 {
7620 word0 = value;
7621 }
7622 void operator=(uint32_t value) volatile
7623 {
7624 word0 = value;
7625 }
7626 CONSTEXPR operator uint32_t()
7627 {
7628 return word0;
7629 }
7630 operator uint32_t() volatile
7631 {
7632 return word0;
7633 }
7634 pmovsset_r copy() volatile
7635 {
7636 return *this;
7637 }
7638 CONSTEXPR uint32_t get_EVENT_CNT_0_OVF() const
7639 {
7640 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7641 return value;
7642 }
7643 uint32_t get_EVENT_CNT_0_OVF() const volatile
7644 {
7645 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7646 return value;
7647 }
7648 CONSTEXPR pmovsset_r &set_EVENT_CNT_0_OVF(uint32_t value)
7649 {
7650 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7651 return *this;
7652 }
7653 volatile pmovsset_r &set_EVENT_CNT_0_OVF(uint32_t value) volatile
7654 {
7655 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7656 return *this;
7657 }
7658 CONSTEXPR uint32_t get_EVENT_CNT_1_OVF() const
7659 {
7660 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7661 return value;
7662 }
7663 uint32_t get_EVENT_CNT_1_OVF() const volatile
7664 {
7665 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7666 return value;
7667 }
7668 CONSTEXPR pmovsset_r &set_EVENT_CNT_1_OVF(uint32_t value)
7669 {
7670 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7671 return *this;
7672 }
7673 volatile pmovsset_r &set_EVENT_CNT_1_OVF(uint32_t value) volatile
7674 {
7675 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7676 return *this;
7677 }
7678 CONSTEXPR uint32_t get_EVENT_CNT_2_OVF() const
7679 {
7680 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7681 return value;
7682 }
7683 uint32_t get_EVENT_CNT_2_OVF() const volatile
7684 {
7685 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7686 return value;
7687 }
7688 CONSTEXPR pmovsset_r &set_EVENT_CNT_2_OVF(uint32_t value)
7689 {
7690 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7691 return *this;
7692 }
7693 volatile pmovsset_r &set_EVENT_CNT_2_OVF(uint32_t value) volatile
7694 {
7695 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7696 return *this;
7697 }
7698 CONSTEXPR uint32_t get_EVENT_CNT_3_OVF() const
7699 {
7700 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7701 return value;
7702 }
7703 uint32_t get_EVENT_CNT_3_OVF() const volatile
7704 {
7705 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7706 return value;
7707 }
7708 CONSTEXPR pmovsset_r &set_EVENT_CNT_3_OVF(uint32_t value)
7709 {
7710 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7711 return *this;
7712 }
7713 volatile pmovsset_r &set_EVENT_CNT_3_OVF(uint32_t value) volatile
7714 {
7715 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7716 return *this;
7717 }
7718 CONSTEXPR uint32_t get_CYCLE_CNT_OVF() const
7719 {
7720 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7721 return value;
7722 }
7723 uint32_t get_CYCLE_CNT_OVF() const volatile
7724 {
7725 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7726 return value;
7727 }
7728 CONSTEXPR pmovsset_r &set_CYCLE_CNT_OVF(uint32_t value)
7729 {
7730 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7731 return *this;
7732 }
7733 volatile pmovsset_r &set_CYCLE_CNT_OVF(uint32_t value) volatile
7734 {
7735 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7736 return *this;
7737 }
7738#endif
7739};
7740
7741// pmovsclr_r - Overflow flag status clear register
7742struct pmovsclr_r
7743{
7744#ifndef __cplusplus
7745 union
7746 {
7747 struct
7748 {
7749 uint32_t EVENT_CNT_0_OVF : 1; // Event counter overflow clear bit for PMEVCNTR0
7750 uint32_t EVENT_CNT_1_OVF : 1; // Event counter overflow clear bit for PMEVCNTR1
7751 uint32_t EVENT_CNT_2_OVF : 1; // Event counter overflow clear bit for PMEVCNTR2
7752 uint32_t EVENT_CNT_3_OVF : 1; // Event counter overflow clear bit for PMEVCNTR3
7753 uint32_t reserved0 : 27;
7754 uint32_t CYCLE_CNT_OVF : 1; // PMCCNTR overflow clear bit
7755 };
7756 uint32_t word;
7757 };
7758#else
7759 private:
7760 uint32_t word0;
7761
7762 public:
7763 CONSTEXPR pmovsclr_r() : word0(0) {}
7764 CONSTEXPR pmovsclr_r(uint32_t init) : word0(init) {}
7765 CONSTEXPR void operator=(uint32_t value)
7766 {
7767 word0 = value;
7768 }
7769 void operator=(uint32_t value) volatile
7770 {
7771 word0 = value;
7772 }
7773 CONSTEXPR operator uint32_t()
7774 {
7775 return word0;
7776 }
7777 operator uint32_t() volatile
7778 {
7779 return word0;
7780 }
7781 pmovsclr_r copy() volatile
7782 {
7783 return *this;
7784 }
7785 CONSTEXPR uint32_t get_EVENT_CNT_0_OVF() const
7786 {
7787 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7788 return value;
7789 }
7790 uint32_t get_EVENT_CNT_0_OVF() const volatile
7791 {
7792 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7793 return value;
7794 }
7795 CONSTEXPR pmovsclr_r &set_EVENT_CNT_0_OVF(uint32_t value)
7796 {
7797 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7798 return *this;
7799 }
7800 volatile pmovsclr_r &set_EVENT_CNT_0_OVF(uint32_t value) volatile
7801 {
7802 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7803 return *this;
7804 }
7805 CONSTEXPR uint32_t get_EVENT_CNT_1_OVF() const
7806 {
7807 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7808 return value;
7809 }
7810 uint32_t get_EVENT_CNT_1_OVF() const volatile
7811 {
7812 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7813 return value;
7814 }
7815 CONSTEXPR pmovsclr_r &set_EVENT_CNT_1_OVF(uint32_t value)
7816 {
7817 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7818 return *this;
7819 }
7820 volatile pmovsclr_r &set_EVENT_CNT_1_OVF(uint32_t value) volatile
7821 {
7822 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7823 return *this;
7824 }
7825 CONSTEXPR uint32_t get_EVENT_CNT_2_OVF() const
7826 {
7827 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7828 return value;
7829 }
7830 uint32_t get_EVENT_CNT_2_OVF() const volatile
7831 {
7832 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7833 return value;
7834 }
7835 CONSTEXPR pmovsclr_r &set_EVENT_CNT_2_OVF(uint32_t value)
7836 {
7837 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7838 return *this;
7839 }
7840 volatile pmovsclr_r &set_EVENT_CNT_2_OVF(uint32_t value) volatile
7841 {
7842 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7843 return *this;
7844 }
7845 CONSTEXPR uint32_t get_EVENT_CNT_3_OVF() const
7846 {
7847 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7848 return value;
7849 }
7850 uint32_t get_EVENT_CNT_3_OVF() const volatile
7851 {
7852 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7853 return value;
7854 }
7855 CONSTEXPR pmovsclr_r &set_EVENT_CNT_3_OVF(uint32_t value)
7856 {
7857 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7858 return *this;
7859 }
7860 volatile pmovsclr_r &set_EVENT_CNT_3_OVF(uint32_t value) volatile
7861 {
7862 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
7863 return *this;
7864 }
7865 CONSTEXPR uint32_t get_CYCLE_CNT_OVF() const
7866 {
7867 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7868 return value;
7869 }
7870 uint32_t get_CYCLE_CNT_OVF() const volatile
7871 {
7872 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
7873 return value;
7874 }
7875 CONSTEXPR pmovsclr_r &set_CYCLE_CNT_OVF(uint32_t value)
7876 {
7877 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7878 return *this;
7879 }
7880 volatile pmovsclr_r &set_CYCLE_CNT_OVF(uint32_t value) volatile
7881 {
7882 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
7883 return *this;
7884 }
7885#endif
7886};
7887
7888// pmintset_r - Interrupt enable set register
7889struct pmintset_r
7890{
7891#ifndef __cplusplus
7892 union
7893 {
7894 struct
7895 {
7896 uint32_t EVENT_CNT_0_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR0
7897 uint32_t EVENT_CNT_1_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR1
7898 uint32_t EVENT_CNT_2_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR2
7899 uint32_t EVENT_CNT_3_INT : 1; // Event counter overflow interrupt request enable bit for PMEVCNTR3
7900 uint32_t reserved0 : 27;
7901 uint32_t CYCLE_CNT_INT : 1; // PMCCNTR overflow interrupt request enable bit
7902 };
7903 uint32_t word;
7904 };
7905#else
7906 private:
7907 uint32_t word0;
7908
7909 public:
7910 CONSTEXPR pmintset_r() : word0(0) {}
7911 CONSTEXPR pmintset_r(uint32_t init) : word0(init) {}
7912 CONSTEXPR void operator=(uint32_t value)
7913 {
7914 word0 = value;
7915 }
7916 void operator=(uint32_t value) volatile
7917 {
7918 word0 = value;
7919 }
7920 CONSTEXPR operator uint32_t()
7921 {
7922 return word0;
7923 }
7924 operator uint32_t() volatile
7925 {
7926 return word0;
7927 }
7928 pmintset_r copy() volatile
7929 {
7930 return *this;
7931 }
7932 CONSTEXPR uint32_t get_EVENT_CNT_0_INT() const
7933 {
7934 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7935 return value;
7936 }
7937 uint32_t get_EVENT_CNT_0_INT() const volatile
7938 {
7939 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
7940 return value;
7941 }
7942 CONSTEXPR pmintset_r &set_EVENT_CNT_0_INT(uint32_t value)
7943 {
7944 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7945 return *this;
7946 }
7947 volatile pmintset_r &set_EVENT_CNT_0_INT(uint32_t value) volatile
7948 {
7949 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
7950 return *this;
7951 }
7952 CONSTEXPR uint32_t get_EVENT_CNT_1_INT() const
7953 {
7954 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7955 return value;
7956 }
7957 uint32_t get_EVENT_CNT_1_INT() const volatile
7958 {
7959 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
7960 return value;
7961 }
7962 CONSTEXPR pmintset_r &set_EVENT_CNT_1_INT(uint32_t value)
7963 {
7964 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7965 return *this;
7966 }
7967 volatile pmintset_r &set_EVENT_CNT_1_INT(uint32_t value) volatile
7968 {
7969 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
7970 return *this;
7971 }
7972 CONSTEXPR uint32_t get_EVENT_CNT_2_INT() const
7973 {
7974 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7975 return value;
7976 }
7977 uint32_t get_EVENT_CNT_2_INT() const volatile
7978 {
7979 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
7980 return value;
7981 }
7982 CONSTEXPR pmintset_r &set_EVENT_CNT_2_INT(uint32_t value)
7983 {
7984 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7985 return *this;
7986 }
7987 volatile pmintset_r &set_EVENT_CNT_2_INT(uint32_t value) volatile
7988 {
7989 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
7990 return *this;
7991 }
7992 CONSTEXPR uint32_t get_EVENT_CNT_3_INT() const
7993 {
7994 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
7995 return value;
7996 }
7997 uint32_t get_EVENT_CNT_3_INT() const volatile
7998 {
7999 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
8000 return value;
8001 }
8002 CONSTEXPR pmintset_r &set_EVENT_CNT_3_INT(uint32_t value)
8003 {
8004 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
8005 return *this;
8006 }
8007 volatile pmintset_r &set_EVENT_CNT_3_INT(uint32_t value) volatile
8008 {
8009 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
8010 return *this;
8011 }
8012 CONSTEXPR uint32_t get_CYCLE_CNT_INT() const
8013 {
8014 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
8015 return value;
8016 }
8017 uint32_t get_CYCLE_CNT_INT() const volatile
8018 {
8019 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
8020 return value;
8021 }
8022 CONSTEXPR pmintset_r &set_CYCLE_CNT_INT(uint32_t value)
8023 {
8024 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
8025 return *this;
8026 }
8027 volatile pmintset_r &set_CYCLE_CNT_INT(uint32_t value) volatile
8028 {
8029 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
8030 return *this;
8031 }
8032#endif
8033};
8034
8035// pmintclr_r - Interrupt enable clear register
8036struct pmintclr_r
8037{
8038#ifndef __cplusplus
8039 union
8040 {
8041 struct
8042 {
8043 uint32_t EVENT_CNT_0_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR0
8044 uint32_t EVENT_CNT_1_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR1
8045 uint32_t EVENT_CNT_2_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR2
8046 uint32_t EVENT_CNT_3_INT : 1; // Event counter overflow interrupt request disable bit for PMEVCNTR3
8047 uint32_t reserved0 : 27;
8048 uint32_t CYCLE_CNT_INT : 1; // PMCCNTR overflow interrupt request disable bit
8049 };
8050 uint32_t word;
8051 };
8052#else
8053 private:
8054 uint32_t word0;
8055
8056 public:
8057 CONSTEXPR pmintclr_r() : word0(0) {}
8058 CONSTEXPR pmintclr_r(uint32_t init) : word0(init) {}
8059 CONSTEXPR void operator=(uint32_t value)
8060 {
8061 word0 = value;
8062 }
8063 void operator=(uint32_t value) volatile
8064 {
8065 word0 = value;
8066 }
8067 CONSTEXPR operator uint32_t()
8068 {
8069 return word0;
8070 }
8071 operator uint32_t() volatile
8072 {
8073 return word0;
8074 }
8075 pmintclr_r copy() volatile
8076 {
8077 return *this;
8078 }
8079 CONSTEXPR uint32_t get_EVENT_CNT_0_INT() const
8080 {
8081 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
8082 return value;
8083 }
8084 uint32_t get_EVENT_CNT_0_INT() const volatile
8085 {
8086 uint32_t value = ((1U << 1) - 1) & (word0 >> 0);
8087 return value;
8088 }
8089 CONSTEXPR pmintclr_r &set_EVENT_CNT_0_INT(uint32_t value)
8090 {
8091 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
8092 return *this;
8093 }
8094 volatile pmintclr_r &set_EVENT_CNT_0_INT(uint32_t value) volatile
8095 {
8096 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) & value) << 0);
8097 return *this;
8098 }
8099 CONSTEXPR uint32_t get_EVENT_CNT_1_INT() const
8100 {
8101 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
8102 return value;
8103 }
8104 uint32_t get_EVENT_CNT_1_INT() const volatile
8105 {
8106 uint32_t value = ((1U << 1) - 1) & (word0 >> 1);
8107 return value;
8108 }
8109 CONSTEXPR pmintclr_r &set_EVENT_CNT_1_INT(uint32_t value)
8110 {
8111 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
8112 return *this;
8113 }
8114 volatile pmintclr_r &set_EVENT_CNT_1_INT(uint32_t value) volatile
8115 {
8116 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) & value) << 1);
8117 return *this;
8118 }
8119 CONSTEXPR uint32_t get_EVENT_CNT_2_INT() const
8120 {
8121 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
8122 return value;
8123 }
8124 uint32_t get_EVENT_CNT_2_INT() const volatile
8125 {
8126 uint32_t value = ((1U << 1) - 1) & (word0 >> 2);
8127 return value;
8128 }
8129 CONSTEXPR pmintclr_r &set_EVENT_CNT_2_INT(uint32_t value)
8130 {
8131 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
8132 return *this;
8133 }
8134 volatile pmintclr_r &set_EVENT_CNT_2_INT(uint32_t value) volatile
8135 {
8136 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) & value) << 2);
8137 return *this;
8138 }
8139 CONSTEXPR uint32_t get_EVENT_CNT_3_INT() const
8140 {
8141 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
8142 return value;
8143 }
8144 uint32_t get_EVENT_CNT_3_INT() const volatile
8145 {
8146 uint32_t value = ((1U << 1) - 1) & (word0 >> 3);
8147 return value;
8148 }
8149 CONSTEXPR pmintclr_r &set_EVENT_CNT_3_INT(uint32_t value)
8150 {
8151 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
8152 return *this;
8153 }
8154 volatile pmintclr_r &set_EVENT_CNT_3_INT(uint32_t value) volatile
8155 {
8156 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) & value) << 3);
8157 return *this;
8158 }
8159 CONSTEXPR uint32_t get_CYCLE_CNT_INT() const
8160 {
8161 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
8162 return value;
8163 }
8164 uint32_t get_CYCLE_CNT_INT() const volatile
8165 {
8166 uint32_t value = ((1U << 1) - 1) & (word0 >> 31);
8167 return value;
8168 }
8169 CONSTEXPR pmintclr_r &set_CYCLE_CNT_INT(uint32_t value)
8170 {
8171 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
8172 return *this;
8173 }
8174 volatile pmintclr_r &set_CYCLE_CNT_INT(uint32_t value) volatile
8175 {
8176 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) & value) << 31);
8177 return *this;
8178 }
8179#endif
8180};
8181
8182// pmccntr_r - Performance monitor cycle count register
8183struct pmccntr_r
8184{
8185#ifndef __cplusplus
8186 union
8187 {
8188 struct
8189 {
8190 uint32_t CYCLE_CNT_LO : 32; // Cycle count - LSB
8191 uint32_t CYCLE_CNT_HI : 16; // Cycle count - MSB
8192 uint32_t reserved0 : 16;
8193 };
8194 uint32_t word[2];
8195 };
8196#else
8197 private:
8198 uint32_t word0;
8199 uint32_t word1;
8200
8201 public:
8202 CONSTEXPR pmccntr_r() : word0(0), word1(0) {}
8203 CONSTEXPR pmccntr_r(uint64_t init) :
8204 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
8205 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
8206 {
8207 }
8208 CONSTEXPR void operator=(uint64_t value)
8209 {
8210 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
8211 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
8212 }
8213 void operator=(uint64_t value) volatile
8214 {
8215 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
8216 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
8217 }
8218 CONSTEXPR operator uint64_t()
8219 {
8220 return (static_cast<uint64_t>(word1) << 32) | word0;
8221 }
8222 operator uint64_t() volatile
8223 {
8224 return (static_cast<uint64_t>(word1) << 32) | word0;
8225 }
8226 pmccntr_r copy() volatile
8227 {
8228 return *this;
8229 }
8230#endif
8231};
8232
8233// pmccntr_cfg_r - Set start/stop event on the cycle counter
8234struct pmccntr_cfg_r
8235{
8236#ifndef __cplusplus
8237 union
8238 {
8239 struct
8240 {
8241 uint32_t CYCLE_CNT_CFG_START : 10; // Cycle counter start event
8242 uint32_t reserved0 : 6;
8243 uint32_t CYCLE_CNT_CFG_STOP : 10; // Cycle counter stop event
8244 uint32_t reserved1 : 6;
8245 };
8246 uint32_t word;
8247 };
8248#else
8249 private:
8250 uint32_t word0;
8251
8252 public:
8253 CONSTEXPR pmccntr_cfg_r() : word0(0) {}
8254 CONSTEXPR pmccntr_cfg_r(uint32_t init) : word0(init) {}
8255 CONSTEXPR void operator=(uint32_t value)
8256 {
8257 word0 = value;
8258 }
8259 void operator=(uint32_t value) volatile
8260 {
8261 word0 = value;
8262 }
8263 CONSTEXPR operator uint32_t()
8264 {
8265 return word0;
8266 }
8267 operator uint32_t() volatile
8268 {
8269 return word0;
8270 }
8271 pmccntr_cfg_r copy() volatile
8272 {
8273 return *this;
8274 }
8275 CONSTEXPR NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_START() const
8276 {
8277 NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 0));
8278 return value;
8279 }
8280 NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_START() const volatile
8281 {
8282 NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 0));
8283 return value;
8284 }
8285 CONSTEXPR pmccntr_cfg_r &set_CYCLE_CNT_CFG_START(NPU_NAMESPACE::pmu_event value)
8286 {
8287 word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 0);
8288 return *this;
8289 }
8290 volatile pmccntr_cfg_r &set_CYCLE_CNT_CFG_START(NPU_NAMESPACE::pmu_event value) volatile
8291 {
8292 word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 0);
8293 return *this;
8294 }
8295 CONSTEXPR NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_STOP() const
8296 {
8297 NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 16));
8298 return value;
8299 }
8300 NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_STOP() const volatile
8301 {
8302 NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 16));
8303 return value;
8304 }
8305 CONSTEXPR pmccntr_cfg_r &set_CYCLE_CNT_CFG_STOP(NPU_NAMESPACE::pmu_event value)
8306 {
8307 word0 = (((~((1U << 10) - 1)) << 16) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 16);
8308 return *this;
8309 }
8310 volatile pmccntr_cfg_r &set_CYCLE_CNT_CFG_STOP(NPU_NAMESPACE::pmu_event value) volatile
8311 {
8312 word0 = (((~((1U << 10) - 1)) << 16) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 16);
8313 return *this;
8314 }
8315#endif
8316};
8317
8318// pmcaxi_chan_r - Set which AXI channel to monitor for latency measurements in PMU
8319struct pmcaxi_chan_r
8320{
8321#ifndef __cplusplus
8322 union
8323 {
8324 struct
8325 {
8326 uint32_t CH_SEL : 4; // Channel select for latency measurements
8327 uint32_t reserved0 : 4;
8328 uint32_t AXI_CNT_SEL : 2; // AXI counter to monitor for latency measurements
8329 uint32_t BW_CH_SEL_EN : 1; // Bandwidth channel selector
8330 uint32_t reserved1 : 21;
8331 };
8332 uint32_t word;
8333 };
8334#else
8335 private:
8336 uint32_t word0;
8337
8338 public:
8339 CONSTEXPR pmcaxi_chan_r() : word0(0) {}
8340 CONSTEXPR pmcaxi_chan_r(uint32_t init) : word0(init) {}
8341 CONSTEXPR void operator=(uint32_t value)
8342 {
8343 word0 = value;
8344 }
8345 void operator=(uint32_t value) volatile
8346 {
8347 word0 = value;
8348 }
8349 CONSTEXPR operator uint32_t()
8350 {
8351 return word0;
8352 }
8353 operator uint32_t() volatile
8354 {
8355 return word0;
8356 }
8357 pmcaxi_chan_r copy() volatile
8358 {
8359 return *this;
8360 }
8361 CONSTEXPR NPU_NAMESPACE::pmu_axi_channel get_CH_SEL() const
8362 {
8363 NPU_NAMESPACE::pmu_axi_channel value =
8364 static_cast<NPU_NAMESPACE::pmu_axi_channel>(((1U << 4) - 1) & (word0 >> 0));
8365 return value;
8366 }
8367 NPU_NAMESPACE::pmu_axi_channel get_CH_SEL() const volatile
8368 {
8369 NPU_NAMESPACE::pmu_axi_channel value =
8370 static_cast<NPU_NAMESPACE::pmu_axi_channel>(((1U << 4) - 1) & (word0 >> 0));
8371 return value;
8372 }
8373 CONSTEXPR pmcaxi_chan_r &set_CH_SEL(NPU_NAMESPACE::pmu_axi_channel value)
8374 {
8375 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 0);
8376 return *this;
8377 }
8378 volatile pmcaxi_chan_r &set_CH_SEL(NPU_NAMESPACE::pmu_axi_channel value) volatile
8379 {
8380 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) & static_cast<uint32_t>(value)) << 0);
8381 return *this;
8382 }
8383 CONSTEXPR uint32_t get_AXI_CNT_SEL() const
8384 {
8385 uint32_t value = ((1U << 2) - 1) & (word0 >> 8);
8386 return value;
8387 }
8388 uint32_t get_AXI_CNT_SEL() const volatile
8389 {
8390 uint32_t value = ((1U << 2) - 1) & (word0 >> 8);
8391 return value;
8392 }
8393 CONSTEXPR pmcaxi_chan_r &set_AXI_CNT_SEL(uint32_t value)
8394 {
8395 word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & value) << 8);
8396 return *this;
8397 }
8398 volatile pmcaxi_chan_r &set_AXI_CNT_SEL(uint32_t value) volatile
8399 {
8400 word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) & value) << 8);
8401 return *this;
8402 }
8403 CONSTEXPR uint32_t get_BW_CH_SEL_EN() const
8404 {
8405 uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
8406 return value;
8407 }
8408 uint32_t get_BW_CH_SEL_EN() const volatile
8409 {
8410 uint32_t value = ((1U << 1) - 1) & (word0 >> 10);
8411 return value;
8412 }
8413 CONSTEXPR pmcaxi_chan_r &set_BW_CH_SEL_EN(uint32_t value)
8414 {
8415 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
8416 return *this;
8417 }
8418 volatile pmcaxi_chan_r &set_BW_CH_SEL_EN(uint32_t value) volatile
8419 {
8420 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) & value) << 10);
8421 return *this;
8422 }
8423#endif
8424};
8425
8426// kernel_x_r - Kernel X offset of in kernel decomposition
8427struct kernel_x_r
8428{
8429#ifndef __cplusplus
8430 union
8431 {
8432 struct
8433 {
8434 uint32_t value : 32; // 32-bit register value
8435 };
8436 uint32_t word;
8437 };
8438#else
8439 private:
8440 uint32_t word0;
8441
8442 public:
8443 CONSTEXPR kernel_x_r() : word0(0) {}
8444 CONSTEXPR kernel_x_r(uint32_t init) : word0(init) {}
8445 CONSTEXPR void operator=(uint32_t value)
8446 {
8447 word0 = value;
8448 }
8449 void operator=(uint32_t value) volatile
8450 {
8451 word0 = value;
8452 }
8453 CONSTEXPR operator uint32_t()
8454 {
8455 return word0;
8456 }
8457 operator uint32_t() volatile
8458 {
8459 return word0;
8460 }
8461 kernel_x_r copy() volatile
8462 {
8463 return *this;
8464 }
8465 CONSTEXPR uint32_t get_value() const
8466 {
8467 uint32_t value = word0;
8468 return value;
8469 }
8470 uint32_t get_value() const volatile
8471 {
8472 uint32_t value = word0;
8473 return value;
8474 }
8475 CONSTEXPR kernel_x_r &set_value(uint32_t value)
8476 {
8477 word0 = value;
8478 return *this;
8479 }
8480 volatile kernel_x_r &set_value(uint32_t value) volatile
8481 {
8482 word0 = value;
8483 return *this;
8484 }
8485#endif
8486};
8487
8488// kernel_y_r - Kernel Y offset of in kernel decomposition
8489struct kernel_y_r
8490{
8491#ifndef __cplusplus
8492 union
8493 {
8494 struct
8495 {
8496 uint32_t value : 32; // 32-bit register value
8497 };
8498 uint32_t word;
8499 };
8500#else
8501 private:
8502 uint32_t word0;
8503
8504 public:
8505 CONSTEXPR kernel_y_r() : word0(0) {}
8506 CONSTEXPR kernel_y_r(uint32_t init) : word0(init) {}
8507 CONSTEXPR void operator=(uint32_t value)
8508 {
8509 word0 = value;
8510 }
8511 void operator=(uint32_t value) volatile
8512 {
8513 word0 = value;
8514 }
8515 CONSTEXPR operator uint32_t()
8516 {
8517 return word0;
8518 }
8519 operator uint32_t() volatile
8520 {
8521 return word0;
8522 }
8523 kernel_y_r copy() volatile
8524 {
8525 return *this;
8526 }
8527 CONSTEXPR uint32_t get_value() const
8528 {
8529 uint32_t value = word0;
8530 return value;
8531 }
8532 uint32_t get_value() const volatile
8533 {
8534 uint32_t value = word0;
8535 return value;
8536 }
8537 CONSTEXPR kernel_y_r &set_value(uint32_t value)
8538 {
8539 word0 = value;
8540 return *this;
8541 }
8542 volatile kernel_y_r &set_value(uint32_t value) volatile
8543 {
8544 word0 = value;
8545 return *this;
8546 }
8547#endif
8548};
8549
8550// kernel_w_m1_r - Kernel (width-1) of current block
8551struct kernel_w_m1_r
8552{
8553#ifndef __cplusplus
8554 union
8555 {
8556 struct
8557 {
8558 uint32_t value : 32; // 32-bit register value
8559 };
8560 uint32_t word;
8561 };
8562#else
8563 private:
8564 uint32_t word0;
8565
8566 public:
8567 CONSTEXPR kernel_w_m1_r() : word0(0) {}
8568 CONSTEXPR kernel_w_m1_r(uint32_t init) : word0(init) {}
8569 CONSTEXPR void operator=(uint32_t value)
8570 {
8571 word0 = value;
8572 }
8573 void operator=(uint32_t value) volatile
8574 {
8575 word0 = value;
8576 }
8577 CONSTEXPR operator uint32_t()
8578 {
8579 return word0;
8580 }
8581 operator uint32_t() volatile
8582 {
8583 return word0;
8584 }
8585 kernel_w_m1_r copy() volatile
8586 {
8587 return *this;
8588 }
8589 CONSTEXPR uint32_t get_value() const
8590 {
8591 uint32_t value = word0;
8592 return value;
8593 }
8594 uint32_t get_value() const volatile
8595 {
8596 uint32_t value = word0;
8597 return value;
8598 }
8599 CONSTEXPR kernel_w_m1_r &set_value(uint32_t value)
8600 {
8601 word0 = value;
8602 return *this;
8603 }
8604 volatile kernel_w_m1_r &set_value(uint32_t value) volatile
8605 {
8606 word0 = value;
8607 return *this;
8608 }
8609#endif
8610};
8611
8612// kernel_h_m1_r - Kernel (height-1) of current block
8613struct kernel_h_m1_r
8614{
8615#ifndef __cplusplus
8616 union
8617 {
8618 struct
8619 {
8620 uint32_t value : 32; // 32-bit register value
8621 };
8622 uint32_t word;
8623 };
8624#else
8625 private:
8626 uint32_t word0;
8627
8628 public:
8629 CONSTEXPR kernel_h_m1_r() : word0(0) {}
8630 CONSTEXPR kernel_h_m1_r(uint32_t init) : word0(init) {}
8631 CONSTEXPR void operator=(uint32_t value)
8632 {
8633 word0 = value;
8634 }
8635 void operator=(uint32_t value) volatile
8636 {
8637 word0 = value;
8638 }
8639 CONSTEXPR operator uint32_t()
8640 {
8641 return word0;
8642 }
8643 operator uint32_t() volatile
8644 {
8645 return word0;
8646 }
8647 kernel_h_m1_r copy() volatile
8648 {
8649 return *this;
8650 }
8651 CONSTEXPR uint32_t get_value() const
8652 {
8653 uint32_t value = word0;
8654 return value;
8655 }
8656 uint32_t get_value() const volatile
8657 {
8658 uint32_t value = word0;
8659 return value;
8660 }
8661 CONSTEXPR kernel_h_m1_r &set_value(uint32_t value)
8662 {
8663 word0 = value;
8664 return *this;
8665 }
8666 volatile kernel_h_m1_r &set_value(uint32_t value) volatile
8667 {
8668 word0 = value;
8669 return *this;
8670 }
8671#endif
8672};
8673
8674// ofm_cblk_width_m1_r - OFM current block (width-1)
8676{
8677#ifndef __cplusplus
8678 union
8679 {
8680 struct
8681 {
8682 uint32_t value : 32; // 32-bit register value
8683 };
8684 uint32_t word;
8685 };
8686#else
8687 private:
8688 uint32_t word0;
8689
8690 public:
8691 CONSTEXPR ofm_cblk_width_m1_r() : word0(0) {}
8692 CONSTEXPR ofm_cblk_width_m1_r(uint32_t init) : word0(init) {}
8693 CONSTEXPR void operator=(uint32_t value)
8694 {
8695 word0 = value;
8696 }
8697 void operator=(uint32_t value) volatile
8698 {
8699 word0 = value;
8700 }
8701 CONSTEXPR operator uint32_t()
8702 {
8703 return word0;
8704 }
8705 operator uint32_t() volatile
8706 {
8707 return word0;
8708 }
8709 ofm_cblk_width_m1_r copy() volatile
8710 {
8711 return *this;
8712 }
8713 CONSTEXPR uint32_t get_value() const
8714 {
8715 uint32_t value = word0;
8716 return value;
8717 }
8718 uint32_t get_value() const volatile
8719 {
8720 uint32_t value = word0;
8721 return value;
8722 }
8723 CONSTEXPR ofm_cblk_width_m1_r &set_value(uint32_t value)
8724 {
8725 word0 = value;
8726 return *this;
8727 }
8728 volatile ofm_cblk_width_m1_r &set_value(uint32_t value) volatile
8729 {
8730 word0 = value;
8731 return *this;
8732 }
8733#endif
8734};
8735
8736// ofm_cblk_height_m1_r - OFM current block (height-1)
8738{
8739#ifndef __cplusplus
8740 union
8741 {
8742 struct
8743 {
8744 uint32_t value : 32; // 32-bit register value
8745 };
8746 uint32_t word;
8747 };
8748#else
8749 private:
8750 uint32_t word0;
8751
8752 public:
8753 CONSTEXPR ofm_cblk_height_m1_r() : word0(0) {}
8754 CONSTEXPR ofm_cblk_height_m1_r(uint32_t init) : word0(init) {}
8755 CONSTEXPR void operator=(uint32_t value)
8756 {
8757 word0 = value;
8758 }
8759 void operator=(uint32_t value) volatile
8760 {
8761 word0 = value;
8762 }
8763 CONSTEXPR operator uint32_t()
8764 {
8765 return word0;
8766 }
8767 operator uint32_t() volatile
8768 {
8769 return word0;
8770 }
8771 ofm_cblk_height_m1_r copy() volatile
8772 {
8773 return *this;
8774 }
8775 CONSTEXPR uint32_t get_value() const
8776 {
8777 uint32_t value = word0;
8778 return value;
8779 }
8780 uint32_t get_value() const volatile
8781 {
8782 uint32_t value = word0;
8783 return value;
8784 }
8785 CONSTEXPR ofm_cblk_height_m1_r &set_value(uint32_t value)
8786 {
8787 word0 = value;
8788 return *this;
8789 }
8790 volatile ofm_cblk_height_m1_r &set_value(uint32_t value) volatile
8791 {
8792 word0 = value;
8793 return *this;
8794 }
8795#endif
8796};
8797
8798// ofm_cblk_depth_m1_r - OFM current block (depth-1)
8800{
8801#ifndef __cplusplus
8802 union
8803 {
8804 struct
8805 {
8806 uint32_t value : 32; // 32-bit register value
8807 };
8808 uint32_t word;
8809 };
8810#else
8811 private:
8812 uint32_t word0;
8813
8814 public:
8815 CONSTEXPR ofm_cblk_depth_m1_r() : word0(0) {}
8816 CONSTEXPR ofm_cblk_depth_m1_r(uint32_t init) : word0(init) {}
8817 CONSTEXPR void operator=(uint32_t value)
8818 {
8819 word0 = value;
8820 }
8821 void operator=(uint32_t value) volatile
8822 {
8823 word0 = value;
8824 }
8825 CONSTEXPR operator uint32_t()
8826 {
8827 return word0;
8828 }
8829 operator uint32_t() volatile
8830 {
8831 return word0;
8832 }
8833 ofm_cblk_depth_m1_r copy() volatile
8834 {
8835 return *this;
8836 }
8837 CONSTEXPR uint32_t get_value() const
8838 {
8839 uint32_t value = word0;
8840 return value;
8841 }
8842 uint32_t get_value() const volatile
8843 {
8844 uint32_t value = word0;
8845 return value;
8846 }
8847 CONSTEXPR ofm_cblk_depth_m1_r &set_value(uint32_t value)
8848 {
8849 word0 = value;
8850 return *this;
8851 }
8852 volatile ofm_cblk_depth_m1_r &set_value(uint32_t value) volatile
8853 {
8854 word0 = value;
8855 return *this;
8856 }
8857#endif
8858};
8859
8860// ifm_cblk_depth_m1_r - IFM current block (depth-1)
8862{
8863#ifndef __cplusplus
8864 union
8865 {
8866 struct
8867 {
8868 uint32_t value : 32; // 32-bit register value
8869 };
8870 uint32_t word;
8871 };
8872#else
8873 private:
8874 uint32_t word0;
8875
8876 public:
8877 CONSTEXPR ifm_cblk_depth_m1_r() : word0(0) {}
8878 CONSTEXPR ifm_cblk_depth_m1_r(uint32_t init) : word0(init) {}
8879 CONSTEXPR void operator=(uint32_t value)
8880 {
8881 word0 = value;
8882 }
8883 void operator=(uint32_t value) volatile
8884 {
8885 word0 = value;
8886 }
8887 CONSTEXPR operator uint32_t()
8888 {
8889 return word0;
8890 }
8891 operator uint32_t() volatile
8892 {
8893 return word0;
8894 }
8895 ifm_cblk_depth_m1_r copy() volatile
8896 {
8897 return *this;
8898 }
8899 CONSTEXPR uint32_t get_value() const
8900 {
8901 uint32_t value = word0;
8902 return value;
8903 }
8904 uint32_t get_value() const volatile
8905 {
8906 uint32_t value = word0;
8907 return value;
8908 }
8909 CONSTEXPR ifm_cblk_depth_m1_r &set_value(uint32_t value)
8910 {
8911 word0 = value;
8912 return *this;
8913 }
8914 volatile ifm_cblk_depth_m1_r &set_value(uint32_t value) volatile
8915 {
8916 word0 = value;
8917 return *this;
8918 }
8919#endif
8920};
8921
8922// ofm_x_r - Block X coordinate in OFM
8923struct ofm_x_r
8924{
8925#ifndef __cplusplus
8926 union
8927 {
8928 struct
8929 {
8930 uint32_t value : 32; // 32-bit register value
8931 };
8932 uint32_t word;
8933 };
8934#else
8935 private:
8936 uint32_t word0;
8937
8938 public:
8939 CONSTEXPR ofm_x_r() : word0(0) {}
8940 CONSTEXPR ofm_x_r(uint32_t init) : word0(init) {}
8941 CONSTEXPR void operator=(uint32_t value)
8942 {
8943 word0 = value;
8944 }
8945 void operator=(uint32_t value) volatile
8946 {
8947 word0 = value;
8948 }
8949 CONSTEXPR operator uint32_t()
8950 {
8951 return word0;
8952 }
8953 operator uint32_t() volatile
8954 {
8955 return word0;
8956 }
8957 ofm_x_r copy() volatile
8958 {
8959 return *this;
8960 }
8961 CONSTEXPR uint32_t get_value() const
8962 {
8963 uint32_t value = word0;
8964 return value;
8965 }
8966 uint32_t get_value() const volatile
8967 {
8968 uint32_t value = word0;
8969 return value;
8970 }
8971 CONSTEXPR ofm_x_r &set_value(uint32_t value)
8972 {
8973 word0 = value;
8974 return *this;
8975 }
8976 volatile ofm_x_r &set_value(uint32_t value) volatile
8977 {
8978 word0 = value;
8979 return *this;
8980 }
8981#endif
8982};
8983
8984// ofm_y_r - Block Y coordinate in OFM
8985struct ofm_y_r
8986{
8987#ifndef __cplusplus
8988 union
8989 {
8990 struct
8991 {
8992 uint32_t value : 32; // 32-bit register value
8993 };
8994 uint32_t word;
8995 };
8996#else
8997 private:
8998 uint32_t word0;
8999
9000 public:
9001 CONSTEXPR ofm_y_r() : word0(0) {}
9002 CONSTEXPR ofm_y_r(uint32_t init) : word0(init) {}
9003 CONSTEXPR void operator=(uint32_t value)
9004 {
9005 word0 = value;
9006 }
9007 void operator=(uint32_t value) volatile
9008 {
9009 word0 = value;
9010 }
9011 CONSTEXPR operator uint32_t()
9012 {
9013 return word0;
9014 }
9015 operator uint32_t() volatile
9016 {
9017 return word0;
9018 }
9019 ofm_y_r copy() volatile
9020 {
9021 return *this;
9022 }
9023 CONSTEXPR uint32_t get_value() const
9024 {
9025 uint32_t value = word0;
9026 return value;
9027 }
9028 uint32_t get_value() const volatile
9029 {
9030 uint32_t value = word0;
9031 return value;
9032 }
9033 CONSTEXPR ofm_y_r &set_value(uint32_t value)
9034 {
9035 word0 = value;
9036 return *this;
9037 }
9038 volatile ofm_y_r &set_value(uint32_t value) volatile
9039 {
9040 word0 = value;
9041 return *this;
9042 }
9043#endif
9044};
9045
9046// ofm_z_r - Block Z (channel) coordinate in OFM
9047struct ofm_z_r
9048{
9049#ifndef __cplusplus
9050 union
9051 {
9052 struct
9053 {
9054 uint32_t value : 32; // 32-bit register value
9055 };
9056 uint32_t word;
9057 };
9058#else
9059 private:
9060 uint32_t word0;
9061
9062 public:
9063 CONSTEXPR ofm_z_r() : word0(0) {}
9064 CONSTEXPR ofm_z_r(uint32_t init) : word0(init) {}
9065 CONSTEXPR void operator=(uint32_t value)
9066 {
9067 word0 = value;
9068 }
9069 void operator=(uint32_t value) volatile
9070 {
9071 word0 = value;
9072 }
9073 CONSTEXPR operator uint32_t()
9074 {
9075 return word0;
9076 }
9077 operator uint32_t() volatile
9078 {
9079 return word0;
9080 }
9081 ofm_z_r copy() volatile
9082 {
9083 return *this;
9084 }
9085 CONSTEXPR uint32_t get_value() const
9086 {
9087 uint32_t value = word0;
9088 return value;
9089 }
9090 uint32_t get_value() const volatile
9091 {
9092 uint32_t value = word0;
9093 return value;
9094 }
9095 CONSTEXPR ofm_z_r &set_value(uint32_t value)
9096 {
9097 word0 = value;
9098 return *this;
9099 }
9100 volatile ofm_z_r &set_value(uint32_t value) volatile
9101 {
9102 word0 = value;
9103 return *this;
9104 }
9105#endif
9106};
9107
9108// ifm_z_r - Block Z (channel) coordinate in IFM
9109struct ifm_z_r
9110{
9111#ifndef __cplusplus
9112 union
9113 {
9114 struct
9115 {
9116 uint32_t value : 32; // 32-bit register value
9117 };
9118 uint32_t word;
9119 };
9120#else
9121 private:
9122 uint32_t word0;
9123
9124 public:
9125 CONSTEXPR ifm_z_r() : word0(0) {}
9126 CONSTEXPR ifm_z_r(uint32_t init) : word0(init) {}
9127 CONSTEXPR void operator=(uint32_t value)
9128 {
9129 word0 = value;
9130 }
9131 void operator=(uint32_t value) volatile
9132 {
9133 word0 = value;
9134 }
9135 CONSTEXPR operator uint32_t()
9136 {
9137 return word0;
9138 }
9139 operator uint32_t() volatile
9140 {
9141 return word0;
9142 }
9143 ifm_z_r copy() volatile
9144 {
9145 return *this;
9146 }
9147 CONSTEXPR uint32_t get_value() const
9148 {
9149 uint32_t value = word0;
9150 return value;
9151 }
9152 uint32_t get_value() const volatile
9153 {
9154 uint32_t value = word0;
9155 return value;
9156 }
9157 CONSTEXPR ifm_z_r &set_value(uint32_t value)
9158 {
9159 word0 = value;
9160 return *this;
9161 }
9162 volatile ifm_z_r &set_value(uint32_t value) volatile
9163 {
9164 word0 = value;
9165 return *this;
9166 }
9167#endif
9168};
9169
9170// pad_top_r - Block top pad
9171struct pad_top_r
9172{
9173#ifndef __cplusplus
9174 union
9175 {
9176 struct
9177 {
9178 uint32_t value : 32; // 32-bit register value
9179 };
9180 uint32_t word;
9181 };
9182#else
9183 private:
9184 uint32_t word0;
9185
9186 public:
9187 CONSTEXPR pad_top_r() : word0(0) {}
9188 CONSTEXPR pad_top_r(uint32_t init) : word0(init) {}
9189 CONSTEXPR void operator=(uint32_t value)
9190 {
9191 word0 = value;
9192 }
9193 void operator=(uint32_t value) volatile
9194 {
9195 word0 = value;
9196 }
9197 CONSTEXPR operator uint32_t()
9198 {
9199 return word0;
9200 }
9201 operator uint32_t() volatile
9202 {
9203 return word0;
9204 }
9205 pad_top_r copy() volatile
9206 {
9207 return *this;
9208 }
9209 CONSTEXPR uint32_t get_value() const
9210 {
9211 uint32_t value = word0;
9212 return value;
9213 }
9214 uint32_t get_value() const volatile
9215 {
9216 uint32_t value = word0;
9217 return value;
9218 }
9219 CONSTEXPR pad_top_r &set_value(uint32_t value)
9220 {
9221 word0 = value;
9222 return *this;
9223 }
9224 volatile pad_top_r &set_value(uint32_t value) volatile
9225 {
9226 word0 = value;
9227 return *this;
9228 }
9229#endif
9230};
9231
9232// pad_left_r - Block left pad
9233struct pad_left_r
9234{
9235#ifndef __cplusplus
9236 union
9237 {
9238 struct
9239 {
9240 uint32_t value : 32; // 32-bit register value
9241 };
9242 uint32_t word;
9243 };
9244#else
9245 private:
9246 uint32_t word0;
9247
9248 public:
9249 CONSTEXPR pad_left_r() : word0(0) {}
9250 CONSTEXPR pad_left_r(uint32_t init) : word0(init) {}
9251 CONSTEXPR void operator=(uint32_t value)
9252 {
9253 word0 = value;
9254 }
9255 void operator=(uint32_t value) volatile
9256 {
9257 word0 = value;
9258 }
9259 CONSTEXPR operator uint32_t()
9260 {
9261 return word0;
9262 }
9263 operator uint32_t() volatile
9264 {
9265 return word0;
9266 }
9267 pad_left_r copy() volatile
9268 {
9269 return *this;
9270 }
9271 CONSTEXPR uint32_t get_value() const
9272 {
9273 uint32_t value = word0;
9274 return value;
9275 }
9276 uint32_t get_value() const volatile
9277 {
9278 uint32_t value = word0;
9279 return value;
9280 }
9281 CONSTEXPR pad_left_r &set_value(uint32_t value)
9282 {
9283 word0 = value;
9284 return *this;
9285 }
9286 volatile pad_left_r &set_value(uint32_t value) volatile
9287 {
9288 word0 = value;
9289 return *this;
9290 }
9291#endif
9292};
9293
9294// ifm_cblk_width_r - IFM current block derived width
9295struct ifm_cblk_width_r
9296{
9297#ifndef __cplusplus
9298 union
9299 {
9300 struct
9301 {
9302 uint32_t value : 32; // 32-bit register value
9303 };
9304 uint32_t word;
9305 };
9306#else
9307 private:
9308 uint32_t word0;
9309
9310 public:
9311 CONSTEXPR ifm_cblk_width_r() : word0(0) {}
9312 CONSTEXPR ifm_cblk_width_r(uint32_t init) : word0(init) {}
9313 CONSTEXPR void operator=(uint32_t value)
9314 {
9315 word0 = value;
9316 }
9317 void operator=(uint32_t value) volatile
9318 {
9319 word0 = value;
9320 }
9321 CONSTEXPR operator uint32_t()
9322 {
9323 return word0;
9324 }
9325 operator uint32_t() volatile
9326 {
9327 return word0;
9328 }
9329 ifm_cblk_width_r copy() volatile
9330 {
9331 return *this;
9332 }
9333 CONSTEXPR uint32_t get_value() const
9334 {
9335 uint32_t value = word0;
9336 return value;
9337 }
9338 uint32_t get_value() const volatile
9339 {
9340 uint32_t value = word0;
9341 return value;
9342 }
9343 CONSTEXPR ifm_cblk_width_r &set_value(uint32_t value)
9344 {
9345 word0 = value;
9346 return *this;
9347 }
9348 volatile ifm_cblk_width_r &set_value(uint32_t value) volatile
9349 {
9350 word0 = value;
9351 return *this;
9352 }
9353#endif
9354};
9355
9356// ifm_cblk_height_r - IFM current block derived height
9357struct ifm_cblk_height_r
9358{
9359#ifndef __cplusplus
9360 union
9361 {
9362 struct
9363 {
9364 uint32_t value : 32; // 32-bit register value
9365 };
9366 uint32_t word;
9367 };
9368#else
9369 private:
9370 uint32_t word0;
9371
9372 public:
9373 CONSTEXPR ifm_cblk_height_r() : word0(0) {}
9374 CONSTEXPR ifm_cblk_height_r(uint32_t init) : word0(init) {}
9375 CONSTEXPR void operator=(uint32_t value)
9376 {
9377 word0 = value;
9378 }
9379 void operator=(uint32_t value) volatile
9380 {
9381 word0 = value;
9382 }
9383 CONSTEXPR operator uint32_t()
9384 {
9385 return word0;
9386 }
9387 operator uint32_t() volatile
9388 {
9389 return word0;
9390 }
9391 ifm_cblk_height_r copy() volatile
9392 {
9393 return *this;
9394 }
9395 CONSTEXPR uint32_t get_value() const
9396 {
9397 uint32_t value = word0;
9398 return value;
9399 }
9400 uint32_t get_value() const volatile
9401 {
9402 uint32_t value = word0;
9403 return value;
9404 }
9405 CONSTEXPR ifm_cblk_height_r &set_value(uint32_t value)
9406 {
9407 word0 = value;
9408 return *this;
9409 }
9410 volatile ifm_cblk_height_r &set_value(uint32_t value) volatile
9411 {
9412 word0 = value;
9413 return *this;
9414 }
9415#endif
9416};
9417
9418// dma_ifm_src_r - DMA IFM channel source position on AXI
9419struct dma_ifm_src_r
9420{
9421#ifndef __cplusplus
9422 union
9423 {
9424 struct
9425 {
9426 uint32_t offset_LO : 32; // Offset - LSB
9427 uint32_t offset_HI : 8; // Offset - MSB
9428 uint32_t reserved0 : 24;
9429 };
9430 uint32_t word[2];
9431 };
9432#else
9433 private:
9434 uint32_t word0;
9435 uint32_t word1;
9436
9437 public:
9438 CONSTEXPR dma_ifm_src_r() : word0(0), word1(0) {}
9439 CONSTEXPR dma_ifm_src_r(uint64_t init) :
9440 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9441 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9442 {
9443 }
9444 CONSTEXPR void operator=(uint64_t value)
9445 {
9446 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9447 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9448 }
9449 void operator=(uint64_t value) volatile
9450 {
9451 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9452 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9453 }
9454 CONSTEXPR operator uint64_t()
9455 {
9456 return (static_cast<uint64_t>(word1) << 32) | word0;
9457 }
9458 operator uint64_t() volatile
9459 {
9460 return (static_cast<uint64_t>(word1) << 32) | word0;
9461 }
9462 dma_ifm_src_r copy() volatile
9463 {
9464 return *this;
9465 }
9466#endif
9467};
9468
9469// dma_ifm_dst_r - DMA IFM channel destination position in SHRAM
9470struct dma_ifm_dst_r
9471{
9472#ifndef __cplusplus
9473 union
9474 {
9475 struct
9476 {
9477 uint32_t value : 32; // 32-bit register value
9478 };
9479 uint32_t word;
9480 };
9481#else
9482 private:
9483 uint32_t word0;
9484
9485 public:
9486 CONSTEXPR dma_ifm_dst_r() : word0(0) {}
9487 CONSTEXPR dma_ifm_dst_r(uint32_t init) : word0(init) {}
9488 CONSTEXPR void operator=(uint32_t value)
9489 {
9490 word0 = value;
9491 }
9492 void operator=(uint32_t value) volatile
9493 {
9494 word0 = value;
9495 }
9496 CONSTEXPR operator uint32_t()
9497 {
9498 return word0;
9499 }
9500 operator uint32_t() volatile
9501 {
9502 return word0;
9503 }
9504 dma_ifm_dst_r copy() volatile
9505 {
9506 return *this;
9507 }
9508 CONSTEXPR uint32_t get_value() const
9509 {
9510 uint32_t value = word0;
9511 return value;
9512 }
9513 uint32_t get_value() const volatile
9514 {
9515 uint32_t value = word0;
9516 return value;
9517 }
9518 CONSTEXPR dma_ifm_dst_r &set_value(uint32_t value)
9519 {
9520 word0 = value;
9521 return *this;
9522 }
9523 volatile dma_ifm_dst_r &set_value(uint32_t value) volatile
9524 {
9525 word0 = value;
9526 return *this;
9527 }
9528#endif
9529};
9530
9531// dma_ofm_src_r - DMA OFM channel source position in SHRAM
9532struct dma_ofm_src_r
9533{
9534#ifndef __cplusplus
9535 union
9536 {
9537 struct
9538 {
9539 uint32_t value : 32; // 32-bit register value
9540 };
9541 uint32_t word;
9542 };
9543#else
9544 private:
9545 uint32_t word0;
9546
9547 public:
9548 CONSTEXPR dma_ofm_src_r() : word0(0) {}
9549 CONSTEXPR dma_ofm_src_r(uint32_t init) : word0(init) {}
9550 CONSTEXPR void operator=(uint32_t value)
9551 {
9552 word0 = value;
9553 }
9554 void operator=(uint32_t value) volatile
9555 {
9556 word0 = value;
9557 }
9558 CONSTEXPR operator uint32_t()
9559 {
9560 return word0;
9561 }
9562 operator uint32_t() volatile
9563 {
9564 return word0;
9565 }
9566 dma_ofm_src_r copy() volatile
9567 {
9568 return *this;
9569 }
9570 CONSTEXPR uint32_t get_value() const
9571 {
9572 uint32_t value = word0;
9573 return value;
9574 }
9575 uint32_t get_value() const volatile
9576 {
9577 uint32_t value = word0;
9578 return value;
9579 }
9580 CONSTEXPR dma_ofm_src_r &set_value(uint32_t value)
9581 {
9582 word0 = value;
9583 return *this;
9584 }
9585 volatile dma_ofm_src_r &set_value(uint32_t value) volatile
9586 {
9587 word0 = value;
9588 return *this;
9589 }
9590#endif
9591};
9592
9593// dma_ofm_dst_r - DMA OFM channel destination position on AXI
9594struct dma_ofm_dst_r
9595{
9596#ifndef __cplusplus
9597 union
9598 {
9599 struct
9600 {
9601 uint32_t offset_LO : 32; // Offset - LSB
9602 uint32_t offset_HI : 8; // Offset - MSB
9603 uint32_t reserved0 : 24;
9604 };
9605 uint32_t word[2];
9606 };
9607#else
9608 private:
9609 uint32_t word0;
9610 uint32_t word1;
9611
9612 public:
9613 CONSTEXPR dma_ofm_dst_r() : word0(0), word1(0) {}
9614 CONSTEXPR dma_ofm_dst_r(uint64_t init) :
9615 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9616 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9617 {
9618 }
9619 CONSTEXPR void operator=(uint64_t value)
9620 {
9621 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9622 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9623 }
9624 void operator=(uint64_t value) volatile
9625 {
9626 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9627 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9628 }
9629 CONSTEXPR operator uint64_t()
9630 {
9631 return (static_cast<uint64_t>(word1) << 32) | word0;
9632 }
9633 operator uint64_t() volatile
9634 {
9635 return (static_cast<uint64_t>(word1) << 32) | word0;
9636 }
9637 dma_ofm_dst_r copy() volatile
9638 {
9639 return *this;
9640 }
9641#endif
9642};
9643
9644// dma_weight_src_r - DMA weight channel source position on AXI
9645struct dma_weight_src_r
9646{
9647#ifndef __cplusplus
9648 union
9649 {
9650 struct
9651 {
9652 uint32_t offset_LO : 32; // Offset - LSB
9653 uint32_t offset_HI : 8; // Offset - MSB
9654 uint32_t reserved0 : 24;
9655 };
9656 uint32_t word[2];
9657 };
9658#else
9659 private:
9660 uint32_t word0;
9661 uint32_t word1;
9662
9663 public:
9664 CONSTEXPR dma_weight_src_r() : word0(0), word1(0) {}
9665 CONSTEXPR dma_weight_src_r(uint64_t init) :
9666 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9667 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9668 {
9669 }
9670 CONSTEXPR void operator=(uint64_t value)
9671 {
9672 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9673 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9674 }
9675 void operator=(uint64_t value) volatile
9676 {
9677 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9678 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9679 }
9680 CONSTEXPR operator uint64_t()
9681 {
9682 return (static_cast<uint64_t>(word1) << 32) | word0;
9683 }
9684 operator uint64_t() volatile
9685 {
9686 return (static_cast<uint64_t>(word1) << 32) | word0;
9687 }
9688 dma_weight_src_r copy() volatile
9689 {
9690 return *this;
9691 }
9692#endif
9693};
9694
9695// dma_cmd_src_r - DMA command channel source position on AXI
9696struct dma_cmd_src_r
9697{
9698#ifndef __cplusplus
9699 union
9700 {
9701 struct
9702 {
9703 uint32_t offset_LO : 32; // Offset - LSB
9704 uint32_t offset_HI : 8; // Offset - MSB
9705 uint32_t reserved0 : 24;
9706 };
9707 uint32_t word[2];
9708 };
9709#else
9710 private:
9711 uint32_t word0;
9712 uint32_t word1;
9713
9714 public:
9715 CONSTEXPR dma_cmd_src_r() : word0(0), word1(0) {}
9716 CONSTEXPR dma_cmd_src_r(uint64_t init) :
9717 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9718 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9719 {
9720 }
9721 CONSTEXPR void operator=(uint64_t value)
9722 {
9723 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9724 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9725 }
9726 void operator=(uint64_t value) volatile
9727 {
9728 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9729 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9730 }
9731 CONSTEXPR operator uint64_t()
9732 {
9733 return (static_cast<uint64_t>(word1) << 32) | word0;
9734 }
9735 operator uint64_t() volatile
9736 {
9737 return (static_cast<uint64_t>(word1) << 32) | word0;
9738 }
9739 dma_cmd_src_r copy() volatile
9740 {
9741 return *this;
9742 }
9743#endif
9744};
9745
9746// dma_cmd_size_r - DMA command channel number of bytes buffered
9747struct dma_cmd_size_r
9748{
9749#ifndef __cplusplus
9750 union
9751 {
9752 struct
9753 {
9754 uint32_t value : 32; // 32-bit register value
9755 };
9756 uint32_t word;
9757 };
9758#else
9759 private:
9760 uint32_t word0;
9761
9762 public:
9763 CONSTEXPR dma_cmd_size_r() : word0(0) {}
9764 CONSTEXPR dma_cmd_size_r(uint32_t init) : word0(init) {}
9765 CONSTEXPR void operator=(uint32_t value)
9766 {
9767 word0 = value;
9768 }
9769 void operator=(uint32_t value) volatile
9770 {
9771 word0 = value;
9772 }
9773 CONSTEXPR operator uint32_t()
9774 {
9775 return word0;
9776 }
9777 operator uint32_t() volatile
9778 {
9779 return word0;
9780 }
9781 dma_cmd_size_r copy() volatile
9782 {
9783 return *this;
9784 }
9785 CONSTEXPR uint32_t get_value() const
9786 {
9787 uint32_t value = word0;
9788 return value;
9789 }
9790 uint32_t get_value() const volatile
9791 {
9792 uint32_t value = word0;
9793 return value;
9794 }
9795 CONSTEXPR dma_cmd_size_r &set_value(uint32_t value)
9796 {
9797 word0 = value;
9798 return *this;
9799 }
9800 volatile dma_cmd_size_r &set_value(uint32_t value) volatile
9801 {
9802 word0 = value;
9803 return *this;
9804 }
9805#endif
9806};
9807
9808// dma_m2m_src_r - DMA memory to memory source position on AXI
9809struct dma_m2m_src_r
9810{
9811#ifndef __cplusplus
9812 union
9813 {
9814 struct
9815 {
9816 uint32_t offset_LO : 32; // Offset - LSB
9817 uint32_t offset_HI : 8; // Offset - MSB
9818 uint32_t reserved0 : 24;
9819 };
9820 uint32_t word[2];
9821 };
9822#else
9823 private:
9824 uint32_t word0;
9825 uint32_t word1;
9826
9827 public:
9828 CONSTEXPR dma_m2m_src_r() : word0(0), word1(0) {}
9829 CONSTEXPR dma_m2m_src_r(uint64_t init) :
9830 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9831 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9832 {
9833 }
9834 CONSTEXPR void operator=(uint64_t value)
9835 {
9836 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9837 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9838 }
9839 void operator=(uint64_t value) volatile
9840 {
9841 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9842 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9843 }
9844 CONSTEXPR operator uint64_t()
9845 {
9846 return (static_cast<uint64_t>(word1) << 32) | word0;
9847 }
9848 operator uint64_t() volatile
9849 {
9850 return (static_cast<uint64_t>(word1) << 32) | word0;
9851 }
9852 dma_m2m_src_r copy() volatile
9853 {
9854 return *this;
9855 }
9856#endif
9857};
9858
9859// dma_m2m_dst_r - DMA memory to memory destination position on AXI
9860struct dma_m2m_dst_r
9861{
9862#ifndef __cplusplus
9863 union
9864 {
9865 struct
9866 {
9867 uint32_t offset_LO : 32; // Offset - LSB
9868 uint32_t offset_HI : 8; // Offset - MSB
9869 uint32_t reserved0 : 24;
9870 };
9871 uint32_t word[2];
9872 };
9873#else
9874 private:
9875 uint32_t word0;
9876 uint32_t word1;
9877
9878 public:
9879 CONSTEXPR dma_m2m_dst_r() : word0(0), word1(0) {}
9880 CONSTEXPR dma_m2m_dst_r(uint64_t init) :
9881 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9882 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9883 {
9884 }
9885 CONSTEXPR void operator=(uint64_t value)
9886 {
9887 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9888 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9889 }
9890 void operator=(uint64_t value) volatile
9891 {
9892 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
9893 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
9894 }
9895 CONSTEXPR operator uint64_t()
9896 {
9897 return (static_cast<uint64_t>(word1) << 32) | word0;
9898 }
9899 operator uint64_t() volatile
9900 {
9901 return (static_cast<uint64_t>(word1) << 32) | word0;
9902 }
9903 dma_m2m_dst_r copy() volatile
9904 {
9905 return *this;
9906 }
9907#endif
9908};
9909
9910// current_qread_r - QREAD position being issued (rather than completed)
9911struct current_qread_r
9912{
9913#ifndef __cplusplus
9914 union
9915 {
9916 struct
9917 {
9918 uint32_t value : 32; // 32-bit register value
9919 };
9920 uint32_t word;
9921 };
9922#else
9923 private:
9924 uint32_t word0;
9925
9926 public:
9927 CONSTEXPR current_qread_r() : word0(0) {}
9928 CONSTEXPR current_qread_r(uint32_t init) : word0(init) {}
9929 CONSTEXPR void operator=(uint32_t value)
9930 {
9931 word0 = value;
9932 }
9933 void operator=(uint32_t value) volatile
9934 {
9935 word0 = value;
9936 }
9937 CONSTEXPR operator uint32_t()
9938 {
9939 return word0;
9940 }
9941 operator uint32_t() volatile
9942 {
9943 return word0;
9944 }
9945 current_qread_r copy() volatile
9946 {
9947 return *this;
9948 }
9949 CONSTEXPR uint32_t get_value() const
9950 {
9951 uint32_t value = word0;
9952 return value;
9953 }
9954 uint32_t get_value() const volatile
9955 {
9956 uint32_t value = word0;
9957 return value;
9958 }
9959 CONSTEXPR current_qread_r &set_value(uint32_t value)
9960 {
9961 word0 = value;
9962 return *this;
9963 }
9964 volatile current_qread_r &set_value(uint32_t value) volatile
9965 {
9966 word0 = value;
9967 return *this;
9968 }
9969#endif
9970};
9971
9972// dma_scale_src_r - DMA scale and bias channel source position on AXI
9973struct dma_scale_src_r
9974{
9975#ifndef __cplusplus
9976 union
9977 {
9978 struct
9979 {
9980 uint32_t offset_LO : 32; // Offset - LSB
9981 uint32_t offset_HI : 8; // Offset - MSB
9982 uint32_t reserved0 : 24;
9983 };
9984 uint32_t word[2];
9985 };
9986#else
9987 private:
9988 uint32_t word0;
9989 uint32_t word1;
9990
9991 public:
9992 CONSTEXPR dma_scale_src_r() : word0(0), word1(0) {}
9993 CONSTEXPR dma_scale_src_r(uint64_t init) :
9994 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
9995 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
9996 {
9997 }
9998 CONSTEXPR void operator=(uint64_t value)
9999 {
10000 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
10001 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
10002 }
10003 void operator=(uint64_t value) volatile
10004 {
10005 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
10006 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
10007 }
10008 CONSTEXPR operator uint64_t()
10009 {
10010 return (static_cast<uint64_t>(word1) << 32) | word0;
10011 }
10012 operator uint64_t() volatile
10013 {
10014 return (static_cast<uint64_t>(word1) << 32) | word0;
10015 }
10016 dma_scale_src_r copy() volatile
10017 {
10018 return *this;
10019 }
10020#endif
10021};
10022
10023// current_block_r - 0-3. Current block bank being executed by the TSU or last one executed if TSU is stopped
10024struct current_block_r
10025{
10026#ifndef __cplusplus
10027 union
10028 {
10029 struct
10030 {
10031 uint32_t value : 32; // 32-bit register value
10032 };
10033 uint32_t word;
10034 };
10035#else
10036 private:
10037 uint32_t word0;
10038
10039 public:
10040 CONSTEXPR current_block_r() : word0(0) {}
10041 CONSTEXPR current_block_r(uint32_t init) : word0(init) {}
10042 CONSTEXPR void operator=(uint32_t value)
10043 {
10044 word0 = value;
10045 }
10046 void operator=(uint32_t value) volatile
10047 {
10048 word0 = value;
10049 }
10050 CONSTEXPR operator uint32_t()
10051 {
10052 return word0;
10053 }
10054 operator uint32_t() volatile
10055 {
10056 return word0;
10057 }
10058 current_block_r copy() volatile
10059 {
10060 return *this;
10061 }
10062 CONSTEXPR uint32_t get_value() const
10063 {
10064 uint32_t value = word0;
10065 return value;
10066 }
10067 uint32_t get_value() const volatile
10068 {
10069 uint32_t value = word0;
10070 return value;
10071 }
10072 CONSTEXPR current_block_r &set_value(uint32_t value)
10073 {
10074 word0 = value;
10075 return *this;
10076 }
10077 volatile current_block_r &set_value(uint32_t value) volatile
10078 {
10079 word0 = value;
10080 return *this;
10081 }
10082#endif
10083};
10084
10085// current_op_r - Current NPU OP command being executed by the TSU
10086struct current_op_r
10087{
10088#ifndef __cplusplus
10089 union
10090 {
10091 struct
10092 {
10093 uint32_t value : 32; // 32-bit register value
10094 };
10095 uint32_t word;
10096 };
10097#else
10098 private:
10099 uint32_t word0;
10100
10101 public:
10102 CONSTEXPR current_op_r() : word0(0) {}
10103 CONSTEXPR current_op_r(uint32_t init) : word0(init) {}
10104 CONSTEXPR void operator=(uint32_t value)
10105 {
10106 word0 = value;
10107 }
10108 void operator=(uint32_t value) volatile
10109 {
10110 word0 = value;
10111 }
10112 CONSTEXPR operator uint32_t()
10113 {
10114 return word0;
10115 }
10116 operator uint32_t() volatile
10117 {
10118 return word0;
10119 }
10120 current_op_r copy() volatile
10121 {
10122 return *this;
10123 }
10124 CONSTEXPR uint32_t get_value() const
10125 {
10126 uint32_t value = word0;
10127 return value;
10128 }
10129 uint32_t get_value() const volatile
10130 {
10131 uint32_t value = word0;
10132 return value;
10133 }
10134 CONSTEXPR current_op_r &set_value(uint32_t value)
10135 {
10136 word0 = value;
10137 return *this;
10138 }
10139 volatile current_op_r &set_value(uint32_t value) volatile
10140 {
10141 word0 = value;
10142 return *this;
10143 }
10144#endif
10145};
10146
10147// current_cmd_r - Current 32-bit command being parsed by the command stream parser
10148struct current_cmd_r
10149{
10150#ifndef __cplusplus
10151 union
10152 {
10153 struct
10154 {
10155 uint32_t value : 32; // 32-bit register value
10156 };
10157 uint32_t word;
10158 };
10159#else
10160 private:
10161 uint32_t word0;
10162
10163 public:
10164 CONSTEXPR current_cmd_r() : word0(0) {}
10165 CONSTEXPR current_cmd_r(uint32_t init) : word0(init) {}
10166 CONSTEXPR void operator=(uint32_t value)
10167 {
10168 word0 = value;
10169 }
10170 void operator=(uint32_t value) volatile
10171 {
10172 word0 = value;
10173 }
10174 CONSTEXPR operator uint32_t()
10175 {
10176 return word0;
10177 }
10178 operator uint32_t() volatile
10179 {
10180 return word0;
10181 }
10182 current_cmd_r copy() volatile
10183 {
10184 return *this;
10185 }
10186 CONSTEXPR uint32_t get_value() const
10187 {
10188 uint32_t value = word0;
10189 return value;
10190 }
10191 uint32_t get_value() const volatile
10192 {
10193 uint32_t value = word0;
10194 return value;
10195 }
10196 CONSTEXPR current_cmd_r &set_value(uint32_t value)
10197 {
10198 word0 = value;
10199 return *this;
10200 }
10201 volatile current_cmd_r &set_value(uint32_t value) volatile
10202 {
10203 word0 = value;
10204 return *this;
10205 }
10206#endif
10207};
10208
10209// pmevcntr_r - Performance monitor event 0 count register
10210struct pmevcntr_r
10211{
10212#ifndef __cplusplus
10213 union
10214 {
10215 struct
10216 {
10217 uint32_t count : 32; // Count word
10218 };
10219 uint32_t word;
10220 };
10221#else
10222 private:
10223 uint32_t word0;
10224
10225 public:
10226 CONSTEXPR pmevcntr_r() : word0(0) {}
10227 CONSTEXPR pmevcntr_r(uint32_t init) : word0(init) {}
10228 CONSTEXPR void operator=(uint32_t value)
10229 {
10230 word0 = value;
10231 }
10232 void operator=(uint32_t value) volatile
10233 {
10234 word0 = value;
10235 }
10236 CONSTEXPR operator uint32_t()
10237 {
10238 return word0;
10239 }
10240 operator uint32_t() volatile
10241 {
10242 return word0;
10243 }
10244 pmevcntr_r copy() volatile
10245 {
10246 return *this;
10247 }
10248 CONSTEXPR uint32_t get_count() const
10249 {
10250 uint32_t value = word0;
10251 return value;
10252 }
10253 uint32_t get_count() const volatile
10254 {
10255 uint32_t value = word0;
10256 return value;
10257 }
10258 CONSTEXPR pmevcntr_r &set_count(uint32_t value)
10259 {
10260 word0 = value;
10261 return *this;
10262 }
10263 volatile pmevcntr_r &set_count(uint32_t value) volatile
10264 {
10265 word0 = value;
10266 return *this;
10267 }
10268#endif
10269};
10270
10271// pmevtyper_r - Performance monitor event type register 0
10272struct pmevtyper_r
10273{
10274#ifndef __cplusplus
10275 union
10276 {
10277 struct
10278 {
10279 uint32_t EV_TYPE : 10; // Event Type
10280 uint32_t reserved0 : 22;
10281 };
10282 uint32_t word;
10283 };
10284#else
10285 private:
10286 uint32_t word0;
10287
10288 public:
10289 CONSTEXPR pmevtyper_r() : word0(0) {}
10290 CONSTEXPR pmevtyper_r(uint32_t init) : word0(init) {}
10291 CONSTEXPR void operator=(uint32_t value)
10292 {
10293 word0 = value;
10294 }
10295 void operator=(uint32_t value) volatile
10296 {
10297 word0 = value;
10298 }
10299 CONSTEXPR operator uint32_t()
10300 {
10301 return word0;
10302 }
10303 operator uint32_t() volatile
10304 {
10305 return word0;
10306 }
10307 pmevtyper_r copy() volatile
10308 {
10309 return *this;
10310 }
10311 CONSTEXPR NPU_NAMESPACE::pmu_event get_EV_TYPE() const
10312 {
10313 NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 0));
10314 return value;
10315 }
10316 NPU_NAMESPACE::pmu_event get_EV_TYPE() const volatile
10317 {
10318 NPU_NAMESPACE::pmu_event value = static_cast<NPU_NAMESPACE::pmu_event>(((1U << 10) - 1) & (word0 >> 0));
10319 return value;
10320 }
10321 CONSTEXPR pmevtyper_r &set_EV_TYPE(NPU_NAMESPACE::pmu_event value)
10322 {
10323 word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 0);
10324 return *this;
10325 }
10326 volatile pmevtyper_r &set_EV_TYPE(NPU_NAMESPACE::pmu_event value) volatile
10327 {
10328 word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) & static_cast<uint32_t>(value)) << 0);
10329 return *this;
10330 }
10331#endif
10332};
10333
10334// shared_buffer_r - Shared buffer debug access. Only valid in STOPPED state
10335struct shared_buffer_r
10336{
10337#ifndef __cplusplus
10338 union
10339 {
10340 struct
10341 {
10342 uint32_t mem_word : 32; // Memory word
10343 };
10344 uint32_t word;
10345 };
10346#else
10347 private:
10348 uint32_t word0;
10349
10350 public:
10351 CONSTEXPR shared_buffer_r() : word0(0) {}
10352 CONSTEXPR shared_buffer_r(uint32_t init) : word0(init) {}
10353 CONSTEXPR void operator=(uint32_t value)
10354 {
10355 word0 = value;
10356 }
10357 void operator=(uint32_t value) volatile
10358 {
10359 word0 = value;
10360 }
10361 CONSTEXPR operator uint32_t()
10362 {
10363 return word0;
10364 }
10365 operator uint32_t() volatile
10366 {
10367 return word0;
10368 }
10369 shared_buffer_r copy() volatile
10370 {
10371 return *this;
10372 }
10373 CONSTEXPR uint32_t get_mem_word() const
10374 {
10375 uint32_t value = word0;
10376 return value;
10377 }
10378 uint32_t get_mem_word() const volatile
10379 {
10380 uint32_t value = word0;
10381 return value;
10382 }
10383 CONSTEXPR shared_buffer_r &set_mem_word(uint32_t value)
10384 {
10385 word0 = value;
10386 return *this;
10387 }
10388 volatile shared_buffer_r &set_mem_word(uint32_t value) volatile
10389 {
10390 word0 = value;
10391 return *this;
10392 }
10393#endif
10394};
10395
10396// ifm_pad_top_r - None
10397struct ifm_pad_top_r
10398{
10399#ifndef __cplusplus
10400 union
10401 {
10402 struct
10403 {
10404 uint32_t value : 32; // 32-bit register value
10405 };
10406 uint32_t word;
10407 };
10408#else
10409 private:
10410 uint32_t word0;
10411
10412 public:
10413 CONSTEXPR ifm_pad_top_r() : word0(0) {}
10414 CONSTEXPR ifm_pad_top_r(uint32_t init) : word0(init) {}
10415 CONSTEXPR void operator=(uint32_t value)
10416 {
10417 word0 = value;
10418 }
10419 void operator=(uint32_t value) volatile
10420 {
10421 word0 = value;
10422 }
10423 CONSTEXPR operator uint32_t()
10424 {
10425 return word0;
10426 }
10427 operator uint32_t() volatile
10428 {
10429 return word0;
10430 }
10431 ifm_pad_top_r copy() volatile
10432 {
10433 return *this;
10434 }
10435 CONSTEXPR uint32_t get_value() const
10436 {
10437 uint32_t value = word0;
10438 return value;
10439 }
10440 uint32_t get_value() const volatile
10441 {
10442 uint32_t value = word0;
10443 return value;
10444 }
10445 CONSTEXPR ifm_pad_top_r &set_value(uint32_t value)
10446 {
10447 word0 = value;
10448 return *this;
10449 }
10450 volatile ifm_pad_top_r &set_value(uint32_t value) volatile
10451 {
10452 word0 = value;
10453 return *this;
10454 }
10455#endif
10456};
10457
10458// ifm_pad_left_r - None
10459struct ifm_pad_left_r
10460{
10461#ifndef __cplusplus
10462 union
10463 {
10464 struct
10465 {
10466 uint32_t value : 32; // 32-bit register value
10467 };
10468 uint32_t word;
10469 };
10470#else
10471 private:
10472 uint32_t word0;
10473
10474 public:
10475 CONSTEXPR ifm_pad_left_r() : word0(0) {}
10476 CONSTEXPR ifm_pad_left_r(uint32_t init) : word0(init) {}
10477 CONSTEXPR void operator=(uint32_t value)
10478 {
10479 word0 = value;
10480 }
10481 void operator=(uint32_t value) volatile
10482 {
10483 word0 = value;
10484 }
10485 CONSTEXPR operator uint32_t()
10486 {
10487 return word0;
10488 }
10489 operator uint32_t() volatile
10490 {
10491 return word0;
10492 }
10493 ifm_pad_left_r copy() volatile
10494 {
10495 return *this;
10496 }
10497 CONSTEXPR uint32_t get_value() const
10498 {
10499 uint32_t value = word0;
10500 return value;
10501 }
10502 uint32_t get_value() const volatile
10503 {
10504 uint32_t value = word0;
10505 return value;
10506 }
10507 CONSTEXPR ifm_pad_left_r &set_value(uint32_t value)
10508 {
10509 word0 = value;
10510 return *this;
10511 }
10512 volatile ifm_pad_left_r &set_value(uint32_t value) volatile
10513 {
10514 word0 = value;
10515 return *this;
10516 }
10517#endif
10518};
10519
10520// ifm_pad_right_r - None
10521struct ifm_pad_right_r
10522{
10523#ifndef __cplusplus
10524 union
10525 {
10526 struct
10527 {
10528 uint32_t value : 32; // 32-bit register value
10529 };
10530 uint32_t word;
10531 };
10532#else
10533 private:
10534 uint32_t word0;
10535
10536 public:
10537 CONSTEXPR ifm_pad_right_r() : word0(0) {}
10538 CONSTEXPR ifm_pad_right_r(uint32_t init) : word0(init) {}
10539 CONSTEXPR void operator=(uint32_t value)
10540 {
10541 word0 = value;
10542 }
10543 void operator=(uint32_t value) volatile
10544 {
10545 word0 = value;
10546 }
10547 CONSTEXPR operator uint32_t()
10548 {
10549 return word0;
10550 }
10551 operator uint32_t() volatile
10552 {
10553 return word0;
10554 }
10555 ifm_pad_right_r copy() volatile
10556 {
10557 return *this;
10558 }
10559 CONSTEXPR uint32_t get_value() const
10560 {
10561 uint32_t value = word0;
10562 return value;
10563 }
10564 uint32_t get_value() const volatile
10565 {
10566 uint32_t value = word0;
10567 return value;
10568 }
10569 CONSTEXPR ifm_pad_right_r &set_value(uint32_t value)
10570 {
10571 word0 = value;
10572 return *this;
10573 }
10574 volatile ifm_pad_right_r &set_value(uint32_t value) volatile
10575 {
10576 word0 = value;
10577 return *this;
10578 }
10579#endif
10580};
10581
10582// ifm_pad_bottom_r - None
10583struct ifm_pad_bottom_r
10584{
10585#ifndef __cplusplus
10586 union
10587 {
10588 struct
10589 {
10590 uint32_t value : 32; // 32-bit register value
10591 };
10592 uint32_t word;
10593 };
10594#else
10595 private:
10596 uint32_t word0;
10597
10598 public:
10599 CONSTEXPR ifm_pad_bottom_r() : word0(0) {}
10600 CONSTEXPR ifm_pad_bottom_r(uint32_t init) : word0(init) {}
10601 CONSTEXPR void operator=(uint32_t value)
10602 {
10603 word0 = value;
10604 }
10605 void operator=(uint32_t value) volatile
10606 {
10607 word0 = value;
10608 }
10609 CONSTEXPR operator uint32_t()
10610 {
10611 return word0;
10612 }
10613 operator uint32_t() volatile
10614 {
10615 return word0;
10616 }
10617 ifm_pad_bottom_r copy() volatile
10618 {
10619 return *this;
10620 }
10621 CONSTEXPR uint32_t get_value() const
10622 {
10623 uint32_t value = word0;
10624 return value;
10625 }
10626 uint32_t get_value() const volatile
10627 {
10628 uint32_t value = word0;
10629 return value;
10630 }
10631 CONSTEXPR ifm_pad_bottom_r &set_value(uint32_t value)
10632 {
10633 word0 = value;
10634 return *this;
10635 }
10636 volatile ifm_pad_bottom_r &set_value(uint32_t value) volatile
10637 {
10638 word0 = value;
10639 return *this;
10640 }
10641#endif
10642};
10643
10644// ifm_depth_m1_r - None
10645struct ifm_depth_m1_r
10646{
10647#ifndef __cplusplus
10648 union
10649 {
10650 struct
10651 {
10652 uint32_t value : 32; // 32-bit register value
10653 };
10654 uint32_t word;
10655 };
10656#else
10657 private:
10658 uint32_t word0;
10659
10660 public:
10661 CONSTEXPR ifm_depth_m1_r() : word0(0) {}
10662 CONSTEXPR ifm_depth_m1_r(uint32_t init) : word0(init) {}
10663 CONSTEXPR void operator=(uint32_t value)
10664 {
10665 word0 = value;
10666 }
10667 void operator=(uint32_t value) volatile
10668 {
10669 word0 = value;
10670 }
10671 CONSTEXPR operator uint32_t()
10672 {
10673 return word0;
10674 }
10675 operator uint32_t() volatile
10676 {
10677 return word0;
10678 }
10679 ifm_depth_m1_r copy() volatile
10680 {
10681 return *this;
10682 }
10683 CONSTEXPR uint32_t get_value() const
10684 {
10685 uint32_t value = word0;
10686 return value;
10687 }
10688 uint32_t get_value() const volatile
10689 {
10690 uint32_t value = word0;
10691 return value;
10692 }
10693 CONSTEXPR ifm_depth_m1_r &set_value(uint32_t value)
10694 {
10695 word0 = value;
10696 return *this;
10697 }
10698 volatile ifm_depth_m1_r &set_value(uint32_t value) volatile
10699 {
10700 word0 = value;
10701 return *this;
10702 }
10703#endif
10704};
10705
10706// ifm_precision_r - None
10707struct ifm_precision_r
10708{
10709#ifndef __cplusplus
10710 union
10711 {
10712 struct
10713 {
10714 uint32_t value : 32; // 32-bit register value
10715 };
10716 uint32_t word;
10717 };
10718#else
10719 private:
10720 uint32_t word0;
10721
10722 public:
10723 CONSTEXPR ifm_precision_r() : word0(0) {}
10724 CONSTEXPR ifm_precision_r(uint32_t init) : word0(init) {}
10725 CONSTEXPR void operator=(uint32_t value)
10726 {
10727 word0 = value;
10728 }
10729 void operator=(uint32_t value) volatile
10730 {
10731 word0 = value;
10732 }
10733 CONSTEXPR operator uint32_t()
10734 {
10735 return word0;
10736 }
10737 operator uint32_t() volatile
10738 {
10739 return word0;
10740 }
10741 ifm_precision_r copy() volatile
10742 {
10743 return *this;
10744 }
10745 CONSTEXPR uint32_t get_value() const
10746 {
10747 uint32_t value = word0;
10748 return value;
10749 }
10750 uint32_t get_value() const volatile
10751 {
10752 uint32_t value = word0;
10753 return value;
10754 }
10755 CONSTEXPR ifm_precision_r &set_value(uint32_t value)
10756 {
10757 word0 = value;
10758 return *this;
10759 }
10760 volatile ifm_precision_r &set_value(uint32_t value) volatile
10761 {
10762 word0 = value;
10763 return *this;
10764 }
10765#endif
10766};
10767
10768// ifm_upscale_r - None
10769struct ifm_upscale_r
10770{
10771#ifndef __cplusplus
10772 union
10773 {
10774 struct
10775 {
10776 uint32_t value : 32; // 32-bit register value
10777 };
10778 uint32_t word;
10779 };
10780#else
10781 private:
10782 uint32_t word0;
10783
10784 public:
10785 CONSTEXPR ifm_upscale_r() : word0(0) {}
10786 CONSTEXPR ifm_upscale_r(uint32_t init) : word0(init) {}
10787 CONSTEXPR void operator=(uint32_t value)
10788 {
10789 word0 = value;
10790 }
10791 void operator=(uint32_t value) volatile
10792 {
10793 word0 = value;
10794 }
10795 CONSTEXPR operator uint32_t()
10796 {
10797 return word0;
10798 }
10799 operator uint32_t() volatile
10800 {
10801 return word0;
10802 }
10803 ifm_upscale_r copy() volatile
10804 {
10805 return *this;
10806 }
10807 CONSTEXPR uint32_t get_value() const
10808 {
10809 uint32_t value = word0;
10810 return value;
10811 }
10812 uint32_t get_value() const volatile
10813 {
10814 uint32_t value = word0;
10815 return value;
10816 }
10817 CONSTEXPR ifm_upscale_r &set_value(uint32_t value)
10818 {
10819 word0 = value;
10820 return *this;
10821 }
10822 volatile ifm_upscale_r &set_value(uint32_t value) volatile
10823 {
10824 word0 = value;
10825 return *this;
10826 }
10827#endif
10828};
10829
10830// ifm_zero_point_r - None
10831struct ifm_zero_point_r
10832{
10833#ifndef __cplusplus
10834 union
10835 {
10836 struct
10837 {
10838 uint32_t value : 32; // 32-bit register value
10839 };
10840 uint32_t word;
10841 };
10842#else
10843 private:
10844 uint32_t word0;
10845
10846 public:
10847 CONSTEXPR ifm_zero_point_r() : word0(0) {}
10848 CONSTEXPR ifm_zero_point_r(uint32_t init) : word0(init) {}
10849 CONSTEXPR void operator=(uint32_t value)
10850 {
10851 word0 = value;
10852 }
10853 void operator=(uint32_t value) volatile
10854 {
10855 word0 = value;
10856 }
10857 CONSTEXPR operator uint32_t()
10858 {
10859 return word0;
10860 }
10861 operator uint32_t() volatile
10862 {
10863 return word0;
10864 }
10865 ifm_zero_point_r copy() volatile
10866 {
10867 return *this;
10868 }
10869 CONSTEXPR uint32_t get_value() const
10870 {
10871 uint32_t value = word0;
10872 return value;
10873 }
10874 uint32_t get_value() const volatile
10875 {
10876 uint32_t value = word0;
10877 return value;
10878 }
10879 CONSTEXPR ifm_zero_point_r &set_value(uint32_t value)
10880 {
10881 word0 = value;
10882 return *this;
10883 }
10884 volatile ifm_zero_point_r &set_value(uint32_t value) volatile
10885 {
10886 word0 = value;
10887 return *this;
10888 }
10889#endif
10890};
10891
10892// ifm_width0_m1_r - None
10893struct ifm_width0_m1_r
10894{
10895#ifndef __cplusplus
10896 union
10897 {
10898 struct
10899 {
10900 uint32_t value : 32; // 32-bit register value
10901 };
10902 uint32_t word;
10903 };
10904#else
10905 private:
10906 uint32_t word0;
10907
10908 public:
10909 CONSTEXPR ifm_width0_m1_r() : word0(0) {}
10910 CONSTEXPR ifm_width0_m1_r(uint32_t init) : word0(init) {}
10911 CONSTEXPR void operator=(uint32_t value)
10912 {
10913 word0 = value;
10914 }
10915 void operator=(uint32_t value) volatile
10916 {
10917 word0 = value;
10918 }
10919 CONSTEXPR operator uint32_t()
10920 {
10921 return word0;
10922 }
10923 operator uint32_t() volatile
10924 {
10925 return word0;
10926 }
10927 ifm_width0_m1_r copy() volatile
10928 {
10929 return *this;
10930 }
10931 CONSTEXPR uint32_t get_value() const
10932 {
10933 uint32_t value = word0;
10934 return value;
10935 }
10936 uint32_t get_value() const volatile
10937 {
10938 uint32_t value = word0;
10939 return value;
10940 }
10941 CONSTEXPR ifm_width0_m1_r &set_value(uint32_t value)
10942 {
10943 word0 = value;
10944 return *this;
10945 }
10946 volatile ifm_width0_m1_r &set_value(uint32_t value) volatile
10947 {
10948 word0 = value;
10949 return *this;
10950 }
10951#endif
10952};
10953
10954// ifm_height0_m1_r - None
10955struct ifm_height0_m1_r
10956{
10957#ifndef __cplusplus
10958 union
10959 {
10960 struct
10961 {
10962 uint32_t value : 32; // 32-bit register value
10963 };
10964 uint32_t word;
10965 };
10966#else
10967 private:
10968 uint32_t word0;
10969
10970 public:
10971 CONSTEXPR ifm_height0_m1_r() : word0(0) {}
10972 CONSTEXPR ifm_height0_m1_r(uint32_t init) : word0(init) {}
10973 CONSTEXPR void operator=(uint32_t value)
10974 {
10975 word0 = value;
10976 }
10977 void operator=(uint32_t value) volatile
10978 {
10979 word0 = value;
10980 }
10981 CONSTEXPR operator uint32_t()
10982 {
10983 return word0;
10984 }
10985 operator uint32_t() volatile
10986 {
10987 return word0;
10988 }
10989 ifm_height0_m1_r copy() volatile
10990 {
10991 return *this;
10992 }
10993 CONSTEXPR uint32_t get_value() const
10994 {
10995 uint32_t value = word0;
10996 return value;
10997 }
10998 uint32_t get_value() const volatile
10999 {
11000 uint32_t value = word0;
11001 return value;
11002 }
11003 CONSTEXPR ifm_height0_m1_r &set_value(uint32_t value)
11004 {
11005 word0 = value;
11006 return *this;
11007 }
11008 volatile ifm_height0_m1_r &set_value(uint32_t value) volatile
11009 {
11010 word0 = value;
11011 return *this;
11012 }
11013#endif
11014};
11015
11016// ifm_height1_m1_r - None
11017struct ifm_height1_m1_r
11018{
11019#ifndef __cplusplus
11020 union
11021 {
11022 struct
11023 {
11024 uint32_t value : 32; // 32-bit register value
11025 };
11026 uint32_t word;
11027 };
11028#else
11029 private:
11030 uint32_t word0;
11031
11032 public:
11033 CONSTEXPR ifm_height1_m1_r() : word0(0) {}
11034 CONSTEXPR ifm_height1_m1_r(uint32_t init) : word0(init) {}
11035 CONSTEXPR void operator=(uint32_t value)
11036 {
11037 word0 = value;
11038 }
11039 void operator=(uint32_t value) volatile
11040 {
11041 word0 = value;
11042 }
11043 CONSTEXPR operator uint32_t()
11044 {
11045 return word0;
11046 }
11047 operator uint32_t() volatile
11048 {
11049 return word0;
11050 }
11051 ifm_height1_m1_r copy() volatile
11052 {
11053 return *this;
11054 }
11055 CONSTEXPR uint32_t get_value() const
11056 {
11057 uint32_t value = word0;
11058 return value;
11059 }
11060 uint32_t get_value() const volatile
11061 {
11062 uint32_t value = word0;
11063 return value;
11064 }
11065 CONSTEXPR ifm_height1_m1_r &set_value(uint32_t value)
11066 {
11067 word0 = value;
11068 return *this;
11069 }
11070 volatile ifm_height1_m1_r &set_value(uint32_t value) volatile
11071 {
11072 word0 = value;
11073 return *this;
11074 }
11075#endif
11076};
11077
11078// ifm_ib_end_r - None
11079struct ifm_ib_end_r
11080{
11081#ifndef __cplusplus
11082 union
11083 {
11084 struct
11085 {
11086 uint32_t value : 32; // 32-bit register value
11087 };
11088 uint32_t word;
11089 };
11090#else
11091 private:
11092 uint32_t word0;
11093
11094 public:
11095 CONSTEXPR ifm_ib_end_r() : word0(0) {}
11096 CONSTEXPR ifm_ib_end_r(uint32_t init) : word0(init) {}
11097 CONSTEXPR void operator=(uint32_t value)
11098 {
11099 word0 = value;
11100 }
11101 void operator=(uint32_t value) volatile
11102 {
11103 word0 = value;
11104 }
11105 CONSTEXPR operator uint32_t()
11106 {
11107 return word0;
11108 }
11109 operator uint32_t() volatile
11110 {
11111 return word0;
11112 }
11113 ifm_ib_end_r copy() volatile
11114 {
11115 return *this;
11116 }
11117 CONSTEXPR uint32_t get_value() const
11118 {
11119 uint32_t value = word0;
11120 return value;
11121 }
11122 uint32_t get_value() const volatile
11123 {
11124 uint32_t value = word0;
11125 return value;
11126 }
11127 CONSTEXPR ifm_ib_end_r &set_value(uint32_t value)
11128 {
11129 word0 = value;
11130 return *this;
11131 }
11132 volatile ifm_ib_end_r &set_value(uint32_t value) volatile
11133 {
11134 word0 = value;
11135 return *this;
11136 }
11137#endif
11138};
11139
11140// ifm_region_r - None
11141struct ifm_region_r
11142{
11143#ifndef __cplusplus
11144 union
11145 {
11146 struct
11147 {
11148 uint32_t value : 32; // 32-bit register value
11149 };
11150 uint32_t word;
11151 };
11152#else
11153 private:
11154 uint32_t word0;
11155
11156 public:
11157 CONSTEXPR ifm_region_r() : word0(0) {}
11158 CONSTEXPR ifm_region_r(uint32_t init) : word0(init) {}
11159 CONSTEXPR void operator=(uint32_t value)
11160 {
11161 word0 = value;
11162 }
11163 void operator=(uint32_t value) volatile
11164 {
11165 word0 = value;
11166 }
11167 CONSTEXPR operator uint32_t()
11168 {
11169 return word0;
11170 }
11171 operator uint32_t() volatile
11172 {
11173 return word0;
11174 }
11175 ifm_region_r copy() volatile
11176 {
11177 return *this;
11178 }
11179 CONSTEXPR uint32_t get_value() const
11180 {
11181 uint32_t value = word0;
11182 return value;
11183 }
11184 uint32_t get_value() const volatile
11185 {
11186 uint32_t value = word0;
11187 return value;
11188 }
11189 CONSTEXPR ifm_region_r &set_value(uint32_t value)
11190 {
11191 word0 = value;
11192 return *this;
11193 }
11194 volatile ifm_region_r &set_value(uint32_t value) volatile
11195 {
11196 word0 = value;
11197 return *this;
11198 }
11199#endif
11200};
11201
11202// ofm_width_m1_r - None
11203struct ofm_width_m1_r
11204{
11205#ifndef __cplusplus
11206 union
11207 {
11208 struct
11209 {
11210 uint32_t value : 32; // 32-bit register value
11211 };
11212 uint32_t word;
11213 };
11214#else
11215 private:
11216 uint32_t word0;
11217
11218 public:
11219 CONSTEXPR ofm_width_m1_r() : word0(0) {}
11220 CONSTEXPR ofm_width_m1_r(uint32_t init) : word0(init) {}
11221 CONSTEXPR void operator=(uint32_t value)
11222 {
11223 word0 = value;
11224 }
11225 void operator=(uint32_t value) volatile
11226 {
11227 word0 = value;
11228 }
11229 CONSTEXPR operator uint32_t()
11230 {
11231 return word0;
11232 }
11233 operator uint32_t() volatile
11234 {
11235 return word0;
11236 }
11237 ofm_width_m1_r copy() volatile
11238 {
11239 return *this;
11240 }
11241 CONSTEXPR uint32_t get_value() const
11242 {
11243 uint32_t value = word0;
11244 return value;
11245 }
11246 uint32_t get_value() const volatile
11247 {
11248 uint32_t value = word0;
11249 return value;
11250 }
11251 CONSTEXPR ofm_width_m1_r &set_value(uint32_t value)
11252 {
11253 word0 = value;
11254 return *this;
11255 }
11256 volatile ofm_width_m1_r &set_value(uint32_t value) volatile
11257 {
11258 word0 = value;
11259 return *this;
11260 }
11261#endif
11262};
11263
11264// ofm_height_m1_r - None
11265struct ofm_height_m1_r
11266{
11267#ifndef __cplusplus
11268 union
11269 {
11270 struct
11271 {
11272 uint32_t value : 32; // 32-bit register value
11273 };
11274 uint32_t word;
11275 };
11276#else
11277 private:
11278 uint32_t word0;
11279
11280 public:
11281 CONSTEXPR ofm_height_m1_r() : word0(0) {}
11282 CONSTEXPR ofm_height_m1_r(uint32_t init) : word0(init) {}
11283 CONSTEXPR void operator=(uint32_t value)
11284 {
11285 word0 = value;
11286 }
11287 void operator=(uint32_t value) volatile
11288 {
11289 word0 = value;
11290 }
11291 CONSTEXPR operator uint32_t()
11292 {
11293 return word0;
11294 }
11295 operator uint32_t() volatile
11296 {
11297 return word0;
11298 }
11299 ofm_height_m1_r copy() volatile
11300 {
11301 return *this;
11302 }
11303 CONSTEXPR uint32_t get_value() const
11304 {
11305 uint32_t value = word0;
11306 return value;
11307 }
11308 uint32_t get_value() const volatile
11309 {
11310 uint32_t value = word0;
11311 return value;
11312 }
11313 CONSTEXPR ofm_height_m1_r &set_value(uint32_t value)
11314 {
11315 word0 = value;
11316 return *this;
11317 }
11318 volatile ofm_height_m1_r &set_value(uint32_t value) volatile
11319 {
11320 word0 = value;
11321 return *this;
11322 }
11323#endif
11324};
11325
11326// ofm_depth_m1_r - None
11327struct ofm_depth_m1_r
11328{
11329#ifndef __cplusplus
11330 union
11331 {
11332 struct
11333 {
11334 uint32_t value : 32; // 32-bit register value
11335 };
11336 uint32_t word;
11337 };
11338#else
11339 private:
11340 uint32_t word0;
11341
11342 public:
11343 CONSTEXPR ofm_depth_m1_r() : word0(0) {}
11344 CONSTEXPR ofm_depth_m1_r(uint32_t init) : word0(init) {}
11345 CONSTEXPR void operator=(uint32_t value)
11346 {
11347 word0 = value;
11348 }
11349 void operator=(uint32_t value) volatile
11350 {
11351 word0 = value;
11352 }
11353 CONSTEXPR operator uint32_t()
11354 {
11355 return word0;
11356 }
11357 operator uint32_t() volatile
11358 {
11359 return word0;
11360 }
11361 ofm_depth_m1_r copy() volatile
11362 {
11363 return *this;
11364 }
11365 CONSTEXPR uint32_t get_value() const
11366 {
11367 uint32_t value = word0;
11368 return value;
11369 }
11370 uint32_t get_value() const volatile
11371 {
11372 uint32_t value = word0;
11373 return value;
11374 }
11375 CONSTEXPR ofm_depth_m1_r &set_value(uint32_t value)
11376 {
11377 word0 = value;
11378 return *this;
11379 }
11380 volatile ofm_depth_m1_r &set_value(uint32_t value) volatile
11381 {
11382 word0 = value;
11383 return *this;
11384 }
11385#endif
11386};
11387
11388// ofm_precision_r - None
11389struct ofm_precision_r
11390{
11391#ifndef __cplusplus
11392 union
11393 {
11394 struct
11395 {
11396 uint32_t value : 32; // 32-bit register value
11397 };
11398 uint32_t word;
11399 };
11400#else
11401 private:
11402 uint32_t word0;
11403
11404 public:
11405 CONSTEXPR ofm_precision_r() : word0(0) {}
11406 CONSTEXPR ofm_precision_r(uint32_t init) : word0(init) {}
11407 CONSTEXPR void operator=(uint32_t value)
11408 {
11409 word0 = value;
11410 }
11411 void operator=(uint32_t value) volatile
11412 {
11413 word0 = value;
11414 }
11415 CONSTEXPR operator uint32_t()
11416 {
11417 return word0;
11418 }
11419 operator uint32_t() volatile
11420 {
11421 return word0;
11422 }
11423 ofm_precision_r copy() volatile
11424 {
11425 return *this;
11426 }
11427 CONSTEXPR uint32_t get_value() const
11428 {
11429 uint32_t value = word0;
11430 return value;
11431 }
11432 uint32_t get_value() const volatile
11433 {
11434 uint32_t value = word0;
11435 return value;
11436 }
11437 CONSTEXPR ofm_precision_r &set_value(uint32_t value)
11438 {
11439 word0 = value;
11440 return *this;
11441 }
11442 volatile ofm_precision_r &set_value(uint32_t value) volatile
11443 {
11444 word0 = value;
11445 return *this;
11446 }
11447#endif
11448};
11449
11450// ofm_blk_width_m1_r - None
11451struct ofm_blk_width_m1_r
11452{
11453#ifndef __cplusplus
11454 union
11455 {
11456 struct
11457 {
11458 uint32_t value : 32; // 32-bit register value
11459 };
11460 uint32_t word;
11461 };
11462#else
11463 private:
11464 uint32_t word0;
11465
11466 public:
11467 CONSTEXPR ofm_blk_width_m1_r() : word0(0) {}
11468 CONSTEXPR ofm_blk_width_m1_r(uint32_t init) : word0(init) {}
11469 CONSTEXPR void operator=(uint32_t value)
11470 {
11471 word0 = value;
11472 }
11473 void operator=(uint32_t value) volatile
11474 {
11475 word0 = value;
11476 }
11477 CONSTEXPR operator uint32_t()
11478 {
11479 return word0;
11480 }
11481 operator uint32_t() volatile
11482 {
11483 return word0;
11484 }
11485 ofm_blk_width_m1_r copy() volatile
11486 {
11487 return *this;
11488 }
11489 CONSTEXPR uint32_t get_value() const
11490 {
11491 uint32_t value = word0;
11492 return value;
11493 }
11494 uint32_t get_value() const volatile
11495 {
11496 uint32_t value = word0;
11497 return value;
11498 }
11499 CONSTEXPR ofm_blk_width_m1_r &set_value(uint32_t value)
11500 {
11501 word0 = value;
11502 return *this;
11503 }
11504 volatile ofm_blk_width_m1_r &set_value(uint32_t value) volatile
11505 {
11506 word0 = value;
11507 return *this;
11508 }
11509#endif
11510};
11511
11512// ofm_blk_height_m1_r - None
11514{
11515#ifndef __cplusplus
11516 union
11517 {
11518 struct
11519 {
11520 uint32_t value : 32; // 32-bit register value
11521 };
11522 uint32_t word;
11523 };
11524#else
11525 private:
11526 uint32_t word0;
11527
11528 public:
11529 CONSTEXPR ofm_blk_height_m1_r() : word0(0) {}
11530 CONSTEXPR ofm_blk_height_m1_r(uint32_t init) : word0(init) {}
11531 CONSTEXPR void operator=(uint32_t value)
11532 {
11533 word0 = value;
11534 }
11535 void operator=(uint32_t value) volatile
11536 {
11537 word0 = value;
11538 }
11539 CONSTEXPR operator uint32_t()
11540 {
11541 return word0;
11542 }
11543 operator uint32_t() volatile
11544 {
11545 return word0;
11546 }
11547 ofm_blk_height_m1_r copy() volatile
11548 {
11549 return *this;
11550 }
11551 CONSTEXPR uint32_t get_value() const
11552 {
11553 uint32_t value = word0;
11554 return value;
11555 }
11556 uint32_t get_value() const volatile
11557 {
11558 uint32_t value = word0;
11559 return value;
11560 }
11561 CONSTEXPR ofm_blk_height_m1_r &set_value(uint32_t value)
11562 {
11563 word0 = value;
11564 return *this;
11565 }
11566 volatile ofm_blk_height_m1_r &set_value(uint32_t value) volatile
11567 {
11568 word0 = value;
11569 return *this;
11570 }
11571#endif
11572};
11573
11574// ofm_blk_depth_m1_r - None
11575struct ofm_blk_depth_m1_r
11576{
11577#ifndef __cplusplus
11578 union
11579 {
11580 struct
11581 {
11582 uint32_t value : 32; // 32-bit register value
11583 };
11584 uint32_t word;
11585 };
11586#else
11587 private:
11588 uint32_t word0;
11589
11590 public:
11591 CONSTEXPR ofm_blk_depth_m1_r() : word0(0) {}
11592 CONSTEXPR ofm_blk_depth_m1_r(uint32_t init) : word0(init) {}
11593 CONSTEXPR void operator=(uint32_t value)
11594 {
11595 word0 = value;
11596 }
11597 void operator=(uint32_t value) volatile
11598 {
11599 word0 = value;
11600 }
11601 CONSTEXPR operator uint32_t()
11602 {
11603 return word0;
11604 }
11605 operator uint32_t() volatile
11606 {
11607 return word0;
11608 }
11609 ofm_blk_depth_m1_r copy() volatile
11610 {
11611 return *this;
11612 }
11613 CONSTEXPR uint32_t get_value() const
11614 {
11615 uint32_t value = word0;
11616 return value;
11617 }
11618 uint32_t get_value() const volatile
11619 {
11620 uint32_t value = word0;
11621 return value;
11622 }
11623 CONSTEXPR ofm_blk_depth_m1_r &set_value(uint32_t value)
11624 {
11625 word0 = value;
11626 return *this;
11627 }
11628 volatile ofm_blk_depth_m1_r &set_value(uint32_t value) volatile
11629 {
11630 word0 = value;
11631 return *this;
11632 }
11633#endif
11634};
11635
11636// ofm_zero_point_r - None
11637struct ofm_zero_point_r
11638{
11639#ifndef __cplusplus
11640 union
11641 {
11642 struct
11643 {
11644 uint32_t value : 32; // 32-bit register value
11645 };
11646 uint32_t word;
11647 };
11648#else
11649 private:
11650 uint32_t word0;
11651
11652 public:
11653 CONSTEXPR ofm_zero_point_r() : word0(0) {}
11654 CONSTEXPR ofm_zero_point_r(uint32_t init) : word0(init) {}
11655 CONSTEXPR void operator=(uint32_t value)
11656 {
11657 word0 = value;
11658 }
11659 void operator=(uint32_t value) volatile
11660 {
11661 word0 = value;
11662 }
11663 CONSTEXPR operator uint32_t()
11664 {
11665 return word0;
11666 }
11667 operator uint32_t() volatile
11668 {
11669 return word0;
11670 }
11671 ofm_zero_point_r copy() volatile
11672 {
11673 return *this;
11674 }
11675 CONSTEXPR uint32_t get_value() const
11676 {
11677 uint32_t value = word0;
11678 return value;
11679 }
11680 uint32_t get_value() const volatile
11681 {
11682 uint32_t value = word0;
11683 return value;
11684 }
11685 CONSTEXPR ofm_zero_point_r &set_value(uint32_t value)
11686 {
11687 word0 = value;
11688 return *this;
11689 }
11690 volatile ofm_zero_point_r &set_value(uint32_t value) volatile
11691 {
11692 word0 = value;
11693 return *this;
11694 }
11695#endif
11696};
11697
11698// ofm_width0_m1_r - None
11699struct ofm_width0_m1_r
11700{
11701#ifndef __cplusplus
11702 union
11703 {
11704 struct
11705 {
11706 uint32_t value : 32; // 32-bit register value
11707 };
11708 uint32_t word;
11709 };
11710#else
11711 private:
11712 uint32_t word0;
11713
11714 public:
11715 CONSTEXPR ofm_width0_m1_r() : word0(0) {}
11716 CONSTEXPR ofm_width0_m1_r(uint32_t init) : word0(init) {}
11717 CONSTEXPR void operator=(uint32_t value)
11718 {
11719 word0 = value;
11720 }
11721 void operator=(uint32_t value) volatile
11722 {
11723 word0 = value;
11724 }
11725 CONSTEXPR operator uint32_t()
11726 {
11727 return word0;
11728 }
11729 operator uint32_t() volatile
11730 {
11731 return word0;
11732 }
11733 ofm_width0_m1_r copy() volatile
11734 {
11735 return *this;
11736 }
11737 CONSTEXPR uint32_t get_value() const
11738 {
11739 uint32_t value = word0;
11740 return value;
11741 }
11742 uint32_t get_value() const volatile
11743 {
11744 uint32_t value = word0;
11745 return value;
11746 }
11747 CONSTEXPR ofm_width0_m1_r &set_value(uint32_t value)
11748 {
11749 word0 = value;
11750 return *this;
11751 }
11752 volatile ofm_width0_m1_r &set_value(uint32_t value) volatile
11753 {
11754 word0 = value;
11755 return *this;
11756 }
11757#endif
11758};
11759
11760// ofm_height0_m1_r - None
11761struct ofm_height0_m1_r
11762{
11763#ifndef __cplusplus
11764 union
11765 {
11766 struct
11767 {
11768 uint32_t value : 32; // 32-bit register value
11769 };
11770 uint32_t word;
11771 };
11772#else
11773 private:
11774 uint32_t word0;
11775
11776 public:
11777 CONSTEXPR ofm_height0_m1_r() : word0(0) {}
11778 CONSTEXPR ofm_height0_m1_r(uint32_t init) : word0(init) {}
11779 CONSTEXPR void operator=(uint32_t value)
11780 {
11781 word0 = value;
11782 }
11783 void operator=(uint32_t value) volatile
11784 {
11785 word0 = value;
11786 }
11787 CONSTEXPR operator uint32_t()
11788 {
11789 return word0;
11790 }
11791 operator uint32_t() volatile
11792 {
11793 return word0;
11794 }
11795 ofm_height0_m1_r copy() volatile
11796 {
11797 return *this;
11798 }
11799 CONSTEXPR uint32_t get_value() const
11800 {
11801 uint32_t value = word0;
11802 return value;
11803 }
11804 uint32_t get_value() const volatile
11805 {
11806 uint32_t value = word0;
11807 return value;
11808 }
11809 CONSTEXPR ofm_height0_m1_r &set_value(uint32_t value)
11810 {
11811 word0 = value;
11812 return *this;
11813 }
11814 volatile ofm_height0_m1_r &set_value(uint32_t value) volatile
11815 {
11816 word0 = value;
11817 return *this;
11818 }
11819#endif
11820};
11821
11822// ofm_height1_m1_r - None
11823struct ofm_height1_m1_r
11824{
11825#ifndef __cplusplus
11826 union
11827 {
11828 struct
11829 {
11830 uint32_t value : 32; // 32-bit register value
11831 };
11832 uint32_t word;
11833 };
11834#else
11835 private:
11836 uint32_t word0;
11837
11838 public:
11839 CONSTEXPR ofm_height1_m1_r() : word0(0) {}
11840 CONSTEXPR ofm_height1_m1_r(uint32_t init) : word0(init) {}
11841 CONSTEXPR void operator=(uint32_t value)
11842 {
11843 word0 = value;
11844 }
11845 void operator=(uint32_t value) volatile
11846 {
11847 word0 = value;
11848 }
11849 CONSTEXPR operator uint32_t()
11850 {
11851 return word0;
11852 }
11853 operator uint32_t() volatile
11854 {
11855 return word0;
11856 }
11857 ofm_height1_m1_r copy() volatile
11858 {
11859 return *this;
11860 }
11861 CONSTEXPR uint32_t get_value() const
11862 {
11863 uint32_t value = word0;
11864 return value;
11865 }
11866 uint32_t get_value() const volatile
11867 {
11868 uint32_t value = word0;
11869 return value;
11870 }
11871 CONSTEXPR ofm_height1_m1_r &set_value(uint32_t value)
11872 {
11873 word0 = value;
11874 return *this;
11875 }
11876 volatile ofm_height1_m1_r &set_value(uint32_t value) volatile
11877 {
11878 word0 = value;
11879 return *this;
11880 }
11881#endif
11882};
11883
11884// ofm_region_r - None
11885struct ofm_region_r
11886{
11887#ifndef __cplusplus
11888 union
11889 {
11890 struct
11891 {
11892 uint32_t value : 32; // 32-bit register value
11893 };
11894 uint32_t word;
11895 };
11896#else
11897 private:
11898 uint32_t word0;
11899
11900 public:
11901 CONSTEXPR ofm_region_r() : word0(0) {}
11902 CONSTEXPR ofm_region_r(uint32_t init) : word0(init) {}
11903 CONSTEXPR void operator=(uint32_t value)
11904 {
11905 word0 = value;
11906 }
11907 void operator=(uint32_t value) volatile
11908 {
11909 word0 = value;
11910 }
11911 CONSTEXPR operator uint32_t()
11912 {
11913 return word0;
11914 }
11915 operator uint32_t() volatile
11916 {
11917 return word0;
11918 }
11919 ofm_region_r copy() volatile
11920 {
11921 return *this;
11922 }
11923 CONSTEXPR uint32_t get_value() const
11924 {
11925 uint32_t value = word0;
11926 return value;
11927 }
11928 uint32_t get_value() const volatile
11929 {
11930 uint32_t value = word0;
11931 return value;
11932 }
11933 CONSTEXPR ofm_region_r &set_value(uint32_t value)
11934 {
11935 word0 = value;
11936 return *this;
11937 }
11938 volatile ofm_region_r &set_value(uint32_t value) volatile
11939 {
11940 word0 = value;
11941 return *this;
11942 }
11943#endif
11944};
11945
11946// kernel_width_m1_r - None
11947struct kernel_width_m1_r
11948{
11949#ifndef __cplusplus
11950 union
11951 {
11952 struct
11953 {
11954 uint32_t value : 32; // 32-bit register value
11955 };
11956 uint32_t word;
11957 };
11958#else
11959 private:
11960 uint32_t word0;
11961
11962 public:
11963 CONSTEXPR kernel_width_m1_r() : word0(0) {}
11964 CONSTEXPR kernel_width_m1_r(uint32_t init) : word0(init) {}
11965 CONSTEXPR void operator=(uint32_t value)
11966 {
11967 word0 = value;
11968 }
11969 void operator=(uint32_t value) volatile
11970 {
11971 word0 = value;
11972 }
11973 CONSTEXPR operator uint32_t()
11974 {
11975 return word0;
11976 }
11977 operator uint32_t() volatile
11978 {
11979 return word0;
11980 }
11981 kernel_width_m1_r copy() volatile
11982 {
11983 return *this;
11984 }
11985 CONSTEXPR uint32_t get_value() const
11986 {
11987 uint32_t value = word0;
11988 return value;
11989 }
11990 uint32_t get_value() const volatile
11991 {
11992 uint32_t value = word0;
11993 return value;
11994 }
11995 CONSTEXPR kernel_width_m1_r &set_value(uint32_t value)
11996 {
11997 word0 = value;
11998 return *this;
11999 }
12000 volatile kernel_width_m1_r &set_value(uint32_t value) volatile
12001 {
12002 word0 = value;
12003 return *this;
12004 }
12005#endif
12006};
12007
12008// kernel_height_m1_r - None
12009struct kernel_height_m1_r
12010{
12011#ifndef __cplusplus
12012 union
12013 {
12014 struct
12015 {
12016 uint32_t value : 32; // 32-bit register value
12017 };
12018 uint32_t word;
12019 };
12020#else
12021 private:
12022 uint32_t word0;
12023
12024 public:
12025 CONSTEXPR kernel_height_m1_r() : word0(0) {}
12026 CONSTEXPR kernel_height_m1_r(uint32_t init) : word0(init) {}
12027 CONSTEXPR void operator=(uint32_t value)
12028 {
12029 word0 = value;
12030 }
12031 void operator=(uint32_t value) volatile
12032 {
12033 word0 = value;
12034 }
12035 CONSTEXPR operator uint32_t()
12036 {
12037 return word0;
12038 }
12039 operator uint32_t() volatile
12040 {
12041 return word0;
12042 }
12043 kernel_height_m1_r copy() volatile
12044 {
12045 return *this;
12046 }
12047 CONSTEXPR uint32_t get_value() const
12048 {
12049 uint32_t value = word0;
12050 return value;
12051 }
12052 uint32_t get_value() const volatile
12053 {
12054 uint32_t value = word0;
12055 return value;
12056 }
12057 CONSTEXPR kernel_height_m1_r &set_value(uint32_t value)
12058 {
12059 word0 = value;
12060 return *this;
12061 }
12062 volatile kernel_height_m1_r &set_value(uint32_t value) volatile
12063 {
12064 word0 = value;
12065 return *this;
12066 }
12067#endif
12068};
12069
12070// kernel_stride_r - None
12071struct kernel_stride_r
12072{
12073#ifndef __cplusplus
12074 union
12075 {
12076 struct
12077 {
12078 uint32_t value : 32; // 32-bit register value
12079 };
12080 uint32_t word;
12081 };
12082#else
12083 private:
12084 uint32_t word0;
12085
12086 public:
12087 CONSTEXPR kernel_stride_r() : word0(0) {}
12088 CONSTEXPR kernel_stride_r(uint32_t init) : word0(init) {}
12089 CONSTEXPR void operator=(uint32_t value)
12090 {
12091 word0 = value;
12092 }
12093 void operator=(uint32_t value) volatile
12094 {
12095 word0 = value;
12096 }
12097 CONSTEXPR operator uint32_t()
12098 {
12099 return word0;
12100 }
12101 operator uint32_t() volatile
12102 {
12103 return word0;
12104 }
12105 kernel_stride_r copy() volatile
12106 {
12107 return *this;
12108 }
12109 CONSTEXPR uint32_t get_value() const
12110 {
12111 uint32_t value = word0;
12112 return value;
12113 }
12114 uint32_t get_value() const volatile
12115 {
12116 uint32_t value = word0;
12117 return value;
12118 }
12119 CONSTEXPR kernel_stride_r &set_value(uint32_t value)
12120 {
12121 word0 = value;
12122 return *this;
12123 }
12124 volatile kernel_stride_r &set_value(uint32_t value) volatile
12125 {
12126 word0 = value;
12127 return *this;
12128 }
12129#endif
12130};
12131
12132// parallel_mode_r - None
12134{
12135#ifndef __cplusplus
12136 union
12137 {
12138 struct
12139 {
12140 uint32_t value : 32; // 32-bit register value
12141 };
12142 uint32_t word;
12143 };
12144#else
12145 private:
12146 uint32_t word0;
12147
12148 public:
12149 CONSTEXPR parallel_mode_r() : word0(0) {}
12150 CONSTEXPR parallel_mode_r(uint32_t init) : word0(init) {}
12151 CONSTEXPR void operator=(uint32_t value)
12152 {
12153 word0 = value;
12154 }
12155 void operator=(uint32_t value) volatile
12156 {
12157 word0 = value;
12158 }
12159 CONSTEXPR operator uint32_t()
12160 {
12161 return word0;
12162 }
12163 operator uint32_t() volatile
12164 {
12165 return word0;
12166 }
12167 parallel_mode_r copy() volatile
12168 {
12169 return *this;
12170 }
12171 CONSTEXPR uint32_t get_value() const
12172 {
12173 uint32_t value = word0;
12174 return value;
12175 }
12176 uint32_t get_value() const volatile
12177 {
12178 uint32_t value = word0;
12179 return value;
12180 }
12181 CONSTEXPR parallel_mode_r &set_value(uint32_t value)
12182 {
12183 word0 = value;
12184 return *this;
12185 }
12186 volatile parallel_mode_r &set_value(uint32_t value) volatile
12187 {
12188 word0 = value;
12189 return *this;
12190 }
12191#endif
12192};
12193
12194// acc_format_r - None
12195struct acc_format_r
12196{
12197#ifndef __cplusplus
12198 union
12199 {
12200 struct
12201 {
12202 uint32_t value : 32; // 32-bit register value
12203 };
12204 uint32_t word;
12205 };
12206#else
12207 private:
12208 uint32_t word0;
12209
12210 public:
12211 CONSTEXPR acc_format_r() : word0(0) {}
12212 CONSTEXPR acc_format_r(uint32_t init) : word0(init) {}
12213 CONSTEXPR void operator=(uint32_t value)
12214 {
12215 word0 = value;
12216 }
12217 void operator=(uint32_t value) volatile
12218 {
12219 word0 = value;
12220 }
12221 CONSTEXPR operator uint32_t()
12222 {
12223 return word0;
12224 }
12225 operator uint32_t() volatile
12226 {
12227 return word0;
12228 }
12229 acc_format_r copy() volatile
12230 {
12231 return *this;
12232 }
12233 CONSTEXPR uint32_t get_value() const
12234 {
12235 uint32_t value = word0;
12236 return value;
12237 }
12238 uint32_t get_value() const volatile
12239 {
12240 uint32_t value = word0;
12241 return value;
12242 }
12243 CONSTEXPR acc_format_r &set_value(uint32_t value)
12244 {
12245 word0 = value;
12246 return *this;
12247 }
12248 volatile acc_format_r &set_value(uint32_t value) volatile
12249 {
12250 word0 = value;
12251 return *this;
12252 }
12253#endif
12254};
12255
12256// activation_r - None
12257struct activation_r
12258{
12259#ifndef __cplusplus
12260 union
12261 {
12262 struct
12263 {
12264 uint32_t value : 32; // 32-bit register value
12265 };
12266 uint32_t word;
12267 };
12268#else
12269 private:
12270 uint32_t word0;
12271
12272 public:
12273 CONSTEXPR activation_r() : word0(0) {}
12274 CONSTEXPR activation_r(uint32_t init) : word0(init) {}
12275 CONSTEXPR void operator=(uint32_t value)
12276 {
12277 word0 = value;
12278 }
12279 void operator=(uint32_t value) volatile
12280 {
12281 word0 = value;
12282 }
12283 CONSTEXPR operator uint32_t()
12284 {
12285 return word0;
12286 }
12287 operator uint32_t() volatile
12288 {
12289 return word0;
12290 }
12291 activation_r copy() volatile
12292 {
12293 return *this;
12294 }
12295 CONSTEXPR uint32_t get_value() const
12296 {
12297 uint32_t value = word0;
12298 return value;
12299 }
12300 uint32_t get_value() const volatile
12301 {
12302 uint32_t value = word0;
12303 return value;
12304 }
12305 CONSTEXPR activation_r &set_value(uint32_t value)
12306 {
12307 word0 = value;
12308 return *this;
12309 }
12310 volatile activation_r &set_value(uint32_t value) volatile
12311 {
12312 word0 = value;
12313 return *this;
12314 }
12315#endif
12316};
12317
12318// activation_min_r - None
12319struct activation_min_r
12320{
12321#ifndef __cplusplus
12322 union
12323 {
12324 struct
12325 {
12326 uint32_t value : 32; // 32-bit register value
12327 };
12328 uint32_t word;
12329 };
12330#else
12331 private:
12332 uint32_t word0;
12333
12334 public:
12335 CONSTEXPR activation_min_r() : word0(0) {}
12336 CONSTEXPR activation_min_r(uint32_t init) : word0(init) {}
12337 CONSTEXPR void operator=(uint32_t value)
12338 {
12339 word0 = value;
12340 }
12341 void operator=(uint32_t value) volatile
12342 {
12343 word0 = value;
12344 }
12345 CONSTEXPR operator uint32_t()
12346 {
12347 return word0;
12348 }
12349 operator uint32_t() volatile
12350 {
12351 return word0;
12352 }
12353 activation_min_r copy() volatile
12354 {
12355 return *this;
12356 }
12357 CONSTEXPR uint32_t get_value() const
12358 {
12359 uint32_t value = word0;
12360 return value;
12361 }
12362 uint32_t get_value() const volatile
12363 {
12364 uint32_t value = word0;
12365 return value;
12366 }
12367 CONSTEXPR activation_min_r &set_value(uint32_t value)
12368 {
12369 word0 = value;
12370 return *this;
12371 }
12372 volatile activation_min_r &set_value(uint32_t value) volatile
12373 {
12374 word0 = value;
12375 return *this;
12376 }
12377#endif
12378};
12379
12380// activation_max_r - None
12381struct activation_max_r
12382{
12383#ifndef __cplusplus
12384 union
12385 {
12386 struct
12387 {
12388 uint32_t value : 32; // 32-bit register value
12389 };
12390 uint32_t word;
12391 };
12392#else
12393 private:
12394 uint32_t word0;
12395
12396 public:
12397 CONSTEXPR activation_max_r() : word0(0) {}
12398 CONSTEXPR activation_max_r(uint32_t init) : word0(init) {}
12399 CONSTEXPR void operator=(uint32_t value)
12400 {
12401 word0 = value;
12402 }
12403 void operator=(uint32_t value) volatile
12404 {
12405 word0 = value;
12406 }
12407 CONSTEXPR operator uint32_t()
12408 {
12409 return word0;
12410 }
12411 operator uint32_t() volatile
12412 {
12413 return word0;
12414 }
12415 activation_max_r copy() volatile
12416 {
12417 return *this;
12418 }
12419 CONSTEXPR uint32_t get_value() const
12420 {
12421 uint32_t value = word0;
12422 return value;
12423 }
12424 uint32_t get_value() const volatile
12425 {
12426 uint32_t value = word0;
12427 return value;
12428 }
12429 CONSTEXPR activation_max_r &set_value(uint32_t value)
12430 {
12431 word0 = value;
12432 return *this;
12433 }
12434 volatile activation_max_r &set_value(uint32_t value) volatile
12435 {
12436 word0 = value;
12437 return *this;
12438 }
12439#endif
12440};
12441
12442// weight_region_r - None
12443struct weight_region_r
12444{
12445#ifndef __cplusplus
12446 union
12447 {
12448 struct
12449 {
12450 uint32_t value : 32; // 32-bit register value
12451 };
12452 uint32_t word;
12453 };
12454#else
12455 private:
12456 uint32_t word0;
12457
12458 public:
12459 CONSTEXPR weight_region_r() : word0(0) {}
12460 CONSTEXPR weight_region_r(uint32_t init) : word0(init) {}
12461 CONSTEXPR void operator=(uint32_t value)
12462 {
12463 word0 = value;
12464 }
12465 void operator=(uint32_t value) volatile
12466 {
12467 word0 = value;
12468 }
12469 CONSTEXPR operator uint32_t()
12470 {
12471 return word0;
12472 }
12473 operator uint32_t() volatile
12474 {
12475 return word0;
12476 }
12477 weight_region_r copy() volatile
12478 {
12479 return *this;
12480 }
12481 CONSTEXPR uint32_t get_value() const
12482 {
12483 uint32_t value = word0;
12484 return value;
12485 }
12486 uint32_t get_value() const volatile
12487 {
12488 uint32_t value = word0;
12489 return value;
12490 }
12491 CONSTEXPR weight_region_r &set_value(uint32_t value)
12492 {
12493 word0 = value;
12494 return *this;
12495 }
12496 volatile weight_region_r &set_value(uint32_t value) volatile
12497 {
12498 word0 = value;
12499 return *this;
12500 }
12501#endif
12502};
12503
12504// scale_region_r - None
12505struct scale_region_r
12506{
12507#ifndef __cplusplus
12508 union
12509 {
12510 struct
12511 {
12512 uint32_t value : 32; // 32-bit register value
12513 };
12514 uint32_t word;
12515 };
12516#else
12517 private:
12518 uint32_t word0;
12519
12520 public:
12521 CONSTEXPR scale_region_r() : word0(0) {}
12522 CONSTEXPR scale_region_r(uint32_t init) : word0(init) {}
12523 CONSTEXPR void operator=(uint32_t value)
12524 {
12525 word0 = value;
12526 }
12527 void operator=(uint32_t value) volatile
12528 {
12529 word0 = value;
12530 }
12531 CONSTEXPR operator uint32_t()
12532 {
12533 return word0;
12534 }
12535 operator uint32_t() volatile
12536 {
12537 return word0;
12538 }
12539 scale_region_r copy() volatile
12540 {
12541 return *this;
12542 }
12543 CONSTEXPR uint32_t get_value() const
12544 {
12545 uint32_t value = word0;
12546 return value;
12547 }
12548 uint32_t get_value() const volatile
12549 {
12550 uint32_t value = word0;
12551 return value;
12552 }
12553 CONSTEXPR scale_region_r &set_value(uint32_t value)
12554 {
12555 word0 = value;
12556 return *this;
12557 }
12558 volatile scale_region_r &set_value(uint32_t value) volatile
12559 {
12560 word0 = value;
12561 return *this;
12562 }
12563#endif
12564};
12565
12566// ab_start_r - None
12567struct ab_start_r
12568{
12569#ifndef __cplusplus
12570 union
12571 {
12572 struct
12573 {
12574 uint32_t value : 32; // 32-bit register value
12575 };
12576 uint32_t word;
12577 };
12578#else
12579 private:
12580 uint32_t word0;
12581
12582 public:
12583 CONSTEXPR ab_start_r() : word0(0) {}
12584 CONSTEXPR ab_start_r(uint32_t init) : word0(init) {}
12585 CONSTEXPR void operator=(uint32_t value)
12586 {
12587 word0 = value;
12588 }
12589 void operator=(uint32_t value) volatile
12590 {
12591 word0 = value;
12592 }
12593 CONSTEXPR operator uint32_t()
12594 {
12595 return word0;
12596 }
12597 operator uint32_t() volatile
12598 {
12599 return word0;
12600 }
12601 ab_start_r copy() volatile
12602 {
12603 return *this;
12604 }
12605 CONSTEXPR uint32_t get_value() const
12606 {
12607 uint32_t value = word0;
12608 return value;
12609 }
12610 uint32_t get_value() const volatile
12611 {
12612 uint32_t value = word0;
12613 return value;
12614 }
12615 CONSTEXPR ab_start_r &set_value(uint32_t value)
12616 {
12617 word0 = value;
12618 return *this;
12619 }
12620 volatile ab_start_r &set_value(uint32_t value) volatile
12621 {
12622 word0 = value;
12623 return *this;
12624 }
12625#endif
12626};
12627
12628// blockdep_r - None
12629struct blockdep_r
12630{
12631#ifndef __cplusplus
12632 union
12633 {
12634 struct
12635 {
12636 uint32_t value : 32; // 32-bit register value
12637 };
12638 uint32_t word;
12639 };
12640#else
12641 private:
12642 uint32_t word0;
12643
12644 public:
12645 CONSTEXPR blockdep_r() : word0(0) {}
12646 CONSTEXPR blockdep_r(uint32_t init) : word0(init) {}
12647 CONSTEXPR void operator=(uint32_t value)
12648 {
12649 word0 = value;
12650 }
12651 void operator=(uint32_t value) volatile
12652 {
12653 word0 = value;
12654 }
12655 CONSTEXPR operator uint32_t()
12656 {
12657 return word0;
12658 }
12659 operator uint32_t() volatile
12660 {
12661 return word0;
12662 }
12663 blockdep_r copy() volatile
12664 {
12665 return *this;
12666 }
12667 CONSTEXPR uint32_t get_value() const
12668 {
12669 uint32_t value = word0;
12670 return value;
12671 }
12672 uint32_t get_value() const volatile
12673 {
12674 uint32_t value = word0;
12675 return value;
12676 }
12677 CONSTEXPR blockdep_r &set_value(uint32_t value)
12678 {
12679 word0 = value;
12680 return *this;
12681 }
12682 volatile blockdep_r &set_value(uint32_t value) volatile
12683 {
12684 word0 = value;
12685 return *this;
12686 }
12687#endif
12688};
12689
12690// dma0_src_region_r - None
12691struct dma0_src_region_r
12692{
12693#ifndef __cplusplus
12694 union
12695 {
12696 struct
12697 {
12698 uint32_t value : 32; // 32-bit register value
12699 };
12700 uint32_t word;
12701 };
12702#else
12703 private:
12704 uint32_t word0;
12705
12706 public:
12707 CONSTEXPR dma0_src_region_r() : word0(0) {}
12708 CONSTEXPR dma0_src_region_r(uint32_t init) : word0(init) {}
12709 CONSTEXPR void operator=(uint32_t value)
12710 {
12711 word0 = value;
12712 }
12713 void operator=(uint32_t value) volatile
12714 {
12715 word0 = value;
12716 }
12717 CONSTEXPR operator uint32_t()
12718 {
12719 return word0;
12720 }
12721 operator uint32_t() volatile
12722 {
12723 return word0;
12724 }
12725 dma0_src_region_r copy() volatile
12726 {
12727 return *this;
12728 }
12729 CONSTEXPR uint32_t get_value() const
12730 {
12731 uint32_t value = word0;
12732 return value;
12733 }
12734 uint32_t get_value() const volatile
12735 {
12736 uint32_t value = word0;
12737 return value;
12738 }
12739 CONSTEXPR dma0_src_region_r &set_value(uint32_t value)
12740 {
12741 word0 = value;
12742 return *this;
12743 }
12744 volatile dma0_src_region_r &set_value(uint32_t value) volatile
12745 {
12746 word0 = value;
12747 return *this;
12748 }
12749#endif
12750};
12751
12752// dma0_dst_region_r - None
12753struct dma0_dst_region_r
12754{
12755#ifndef __cplusplus
12756 union
12757 {
12758 struct
12759 {
12760 uint32_t value : 32; // 32-bit register value
12761 };
12762 uint32_t word;
12763 };
12764#else
12765 private:
12766 uint32_t word0;
12767
12768 public:
12769 CONSTEXPR dma0_dst_region_r() : word0(0) {}
12770 CONSTEXPR dma0_dst_region_r(uint32_t init) : word0(init) {}
12771 CONSTEXPR void operator=(uint32_t value)
12772 {
12773 word0 = value;
12774 }
12775 void operator=(uint32_t value) volatile
12776 {
12777 word0 = value;
12778 }
12779 CONSTEXPR operator uint32_t()
12780 {
12781 return word0;
12782 }
12783 operator uint32_t() volatile
12784 {
12785 return word0;
12786 }
12787 dma0_dst_region_r copy() volatile
12788 {
12789 return *this;
12790 }
12791 CONSTEXPR uint32_t get_value() const
12792 {
12793 uint32_t value = word0;
12794 return value;
12795 }
12796 uint32_t get_value() const volatile
12797 {
12798 uint32_t value = word0;
12799 return value;
12800 }
12801 CONSTEXPR dma0_dst_region_r &set_value(uint32_t value)
12802 {
12803 word0 = value;
12804 return *this;
12805 }
12806 volatile dma0_dst_region_r &set_value(uint32_t value) volatile
12807 {
12808 word0 = value;
12809 return *this;
12810 }
12811#endif
12812};
12813
12814// dma0_size0_r - None
12815struct dma0_size0_r
12816{
12817#ifndef __cplusplus
12818 union
12819 {
12820 struct
12821 {
12822 uint32_t value : 32; // 32-bit register value
12823 };
12824 uint32_t word;
12825 };
12826#else
12827 private:
12828 uint32_t word0;
12829
12830 public:
12831 CONSTEXPR dma0_size0_r() : word0(0) {}
12832 CONSTEXPR dma0_size0_r(uint32_t init) : word0(init) {}
12833 CONSTEXPR void operator=(uint32_t value)
12834 {
12835 word0 = value;
12836 }
12837 void operator=(uint32_t value) volatile
12838 {
12839 word0 = value;
12840 }
12841 CONSTEXPR operator uint32_t()
12842 {
12843 return word0;
12844 }
12845 operator uint32_t() volatile
12846 {
12847 return word0;
12848 }
12849 dma0_size0_r copy() volatile
12850 {
12851 return *this;
12852 }
12853 CONSTEXPR uint32_t get_value() const
12854 {
12855 uint32_t value = word0;
12856 return value;
12857 }
12858 uint32_t get_value() const volatile
12859 {
12860 uint32_t value = word0;
12861 return value;
12862 }
12863 CONSTEXPR dma0_size0_r &set_value(uint32_t value)
12864 {
12865 word0 = value;
12866 return *this;
12867 }
12868 volatile dma0_size0_r &set_value(uint32_t value) volatile
12869 {
12870 word0 = value;
12871 return *this;
12872 }
12873#endif
12874};
12875
12876// dma0_size1_r - None
12877struct dma0_size1_r
12878{
12879#ifndef __cplusplus
12880 union
12881 {
12882 struct
12883 {
12884 uint32_t value : 32; // 32-bit register value
12885 };
12886 uint32_t word;
12887 };
12888#else
12889 private:
12890 uint32_t word0;
12891
12892 public:
12893 CONSTEXPR dma0_size1_r() : word0(0) {}
12894 CONSTEXPR dma0_size1_r(uint32_t init) : word0(init) {}
12895 CONSTEXPR void operator=(uint32_t value)
12896 {
12897 word0 = value;
12898 }
12899 void operator=(uint32_t value) volatile
12900 {
12901 word0 = value;
12902 }
12903 CONSTEXPR operator uint32_t()
12904 {
12905 return word0;
12906 }
12907 operator uint32_t() volatile
12908 {
12909 return word0;
12910 }
12911 dma0_size1_r copy() volatile
12912 {
12913 return *this;
12914 }
12915 CONSTEXPR uint32_t get_value() const
12916 {
12917 uint32_t value = word0;
12918 return value;
12919 }
12920 uint32_t get_value() const volatile
12921 {
12922 uint32_t value = word0;
12923 return value;
12924 }
12925 CONSTEXPR dma0_size1_r &set_value(uint32_t value)
12926 {
12927 word0 = value;
12928 return *this;
12929 }
12930 volatile dma0_size1_r &set_value(uint32_t value) volatile
12931 {
12932 word0 = value;
12933 return *this;
12934 }
12935#endif
12936};
12937
12938// ifm2_broadcast_r - None
12939struct ifm2_broadcast_r
12940{
12941#ifndef __cplusplus
12942 union
12943 {
12944 struct
12945 {
12946 uint32_t value : 32; // 32-bit register value
12947 };
12948 uint32_t word;
12949 };
12950#else
12951 private:
12952 uint32_t word0;
12953
12954 public:
12955 CONSTEXPR ifm2_broadcast_r() : word0(0) {}
12956 CONSTEXPR ifm2_broadcast_r(uint32_t init) : word0(init) {}
12957 CONSTEXPR void operator=(uint32_t value)
12958 {
12959 word0 = value;
12960 }
12961 void operator=(uint32_t value) volatile
12962 {
12963 word0 = value;
12964 }
12965 CONSTEXPR operator uint32_t()
12966 {
12967 return word0;
12968 }
12969 operator uint32_t() volatile
12970 {
12971 return word0;
12972 }
12973 ifm2_broadcast_r copy() volatile
12974 {
12975 return *this;
12976 }
12977 CONSTEXPR uint32_t get_value() const
12978 {
12979 uint32_t value = word0;
12980 return value;
12981 }
12982 uint32_t get_value() const volatile
12983 {
12984 uint32_t value = word0;
12985 return value;
12986 }
12987 CONSTEXPR ifm2_broadcast_r &set_value(uint32_t value)
12988 {
12989 word0 = value;
12990 return *this;
12991 }
12992 volatile ifm2_broadcast_r &set_value(uint32_t value) volatile
12993 {
12994 word0 = value;
12995 return *this;
12996 }
12997#endif
12998};
12999
13000// ifm2_scalar_r - None
13001struct ifm2_scalar_r
13002{
13003#ifndef __cplusplus
13004 union
13005 {
13006 struct
13007 {
13008 uint32_t value : 32; // 32-bit register value
13009 };
13010 uint32_t word;
13011 };
13012#else
13013 private:
13014 uint32_t word0;
13015
13016 public:
13017 CONSTEXPR ifm2_scalar_r() : word0(0) {}
13018 CONSTEXPR ifm2_scalar_r(uint32_t init) : word0(init) {}
13019 CONSTEXPR void operator=(uint32_t value)
13020 {
13021 word0 = value;
13022 }
13023 void operator=(uint32_t value) volatile
13024 {
13025 word0 = value;
13026 }
13027 CONSTEXPR operator uint32_t()
13028 {
13029 return word0;
13030 }
13031 operator uint32_t() volatile
13032 {
13033 return word0;
13034 }
13035 ifm2_scalar_r copy() volatile
13036 {
13037 return *this;
13038 }
13039 CONSTEXPR uint32_t get_value() const
13040 {
13041 uint32_t value = word0;
13042 return value;
13043 }
13044 uint32_t get_value() const volatile
13045 {
13046 uint32_t value = word0;
13047 return value;
13048 }
13049 CONSTEXPR ifm2_scalar_r &set_value(uint32_t value)
13050 {
13051 word0 = value;
13052 return *this;
13053 }
13054 volatile ifm2_scalar_r &set_value(uint32_t value) volatile
13055 {
13056 word0 = value;
13057 return *this;
13058 }
13059#endif
13060};
13061
13062// ifm2_precision_r - None
13063struct ifm2_precision_r
13064{
13065#ifndef __cplusplus
13066 union
13067 {
13068 struct
13069 {
13070 uint32_t value : 32; // 32-bit register value
13071 };
13072 uint32_t word;
13073 };
13074#else
13075 private:
13076 uint32_t word0;
13077
13078 public:
13079 CONSTEXPR ifm2_precision_r() : word0(0) {}
13080 CONSTEXPR ifm2_precision_r(uint32_t init) : word0(init) {}
13081 CONSTEXPR void operator=(uint32_t value)
13082 {
13083 word0 = value;
13084 }
13085 void operator=(uint32_t value) volatile
13086 {
13087 word0 = value;
13088 }
13089 CONSTEXPR operator uint32_t()
13090 {
13091 return word0;
13092 }
13093 operator uint32_t() volatile
13094 {
13095 return word0;
13096 }
13097 ifm2_precision_r copy() volatile
13098 {
13099 return *this;
13100 }
13101 CONSTEXPR uint32_t get_value() const
13102 {
13103 uint32_t value = word0;
13104 return value;
13105 }
13106 uint32_t get_value() const volatile
13107 {
13108 uint32_t value = word0;
13109 return value;
13110 }
13111 CONSTEXPR ifm2_precision_r &set_value(uint32_t value)
13112 {
13113 word0 = value;
13114 return *this;
13115 }
13116 volatile ifm2_precision_r &set_value(uint32_t value) volatile
13117 {
13118 word0 = value;
13119 return *this;
13120 }
13121#endif
13122};
13123
13124// ifm2_zero_point_r - None
13125struct ifm2_zero_point_r
13126{
13127#ifndef __cplusplus
13128 union
13129 {
13130 struct
13131 {
13132 uint32_t value : 32; // 32-bit register value
13133 };
13134 uint32_t word;
13135 };
13136#else
13137 private:
13138 uint32_t word0;
13139
13140 public:
13141 CONSTEXPR ifm2_zero_point_r() : word0(0) {}
13142 CONSTEXPR ifm2_zero_point_r(uint32_t init) : word0(init) {}
13143 CONSTEXPR void operator=(uint32_t value)
13144 {
13145 word0 = value;
13146 }
13147 void operator=(uint32_t value) volatile
13148 {
13149 word0 = value;
13150 }
13151 CONSTEXPR operator uint32_t()
13152 {
13153 return word0;
13154 }
13155 operator uint32_t() volatile
13156 {
13157 return word0;
13158 }
13159 ifm2_zero_point_r copy() volatile
13160 {
13161 return *this;
13162 }
13163 CONSTEXPR uint32_t get_value() const
13164 {
13165 uint32_t value = word0;
13166 return value;
13167 }
13168 uint32_t get_value() const volatile
13169 {
13170 uint32_t value = word0;
13171 return value;
13172 }
13173 CONSTEXPR ifm2_zero_point_r &set_value(uint32_t value)
13174 {
13175 word0 = value;
13176 return *this;
13177 }
13178 volatile ifm2_zero_point_r &set_value(uint32_t value) volatile
13179 {
13180 word0 = value;
13181 return *this;
13182 }
13183#endif
13184};
13185
13186// ifm2_width0_m1_r - None
13187struct ifm2_width0_m1_r
13188{
13189#ifndef __cplusplus
13190 union
13191 {
13192 struct
13193 {
13194 uint32_t value : 32; // 32-bit register value
13195 };
13196 uint32_t word;
13197 };
13198#else
13199 private:
13200 uint32_t word0;
13201
13202 public:
13203 CONSTEXPR ifm2_width0_m1_r() : word0(0) {}
13204 CONSTEXPR ifm2_width0_m1_r(uint32_t init) : word0(init) {}
13205 CONSTEXPR void operator=(uint32_t value)
13206 {
13207 word0 = value;
13208 }
13209 void operator=(uint32_t value) volatile
13210 {
13211 word0 = value;
13212 }
13213 CONSTEXPR operator uint32_t()
13214 {
13215 return word0;
13216 }
13217 operator uint32_t() volatile
13218 {
13219 return word0;
13220 }
13221 ifm2_width0_m1_r copy() volatile
13222 {
13223 return *this;
13224 }
13225 CONSTEXPR uint32_t get_value() const
13226 {
13227 uint32_t value = word0;
13228 return value;
13229 }
13230 uint32_t get_value() const volatile
13231 {
13232 uint32_t value = word0;
13233 return value;
13234 }
13235 CONSTEXPR ifm2_width0_m1_r &set_value(uint32_t value)
13236 {
13237 word0 = value;
13238 return *this;
13239 }
13240 volatile ifm2_width0_m1_r &set_value(uint32_t value) volatile
13241 {
13242 word0 = value;
13243 return *this;
13244 }
13245#endif
13246};
13247
13248// ifm2_height0_m1_r - None
13249struct ifm2_height0_m1_r
13250{
13251#ifndef __cplusplus
13252 union
13253 {
13254 struct
13255 {
13256 uint32_t value : 32; // 32-bit register value
13257 };
13258 uint32_t word;
13259 };
13260#else
13261 private:
13262 uint32_t word0;
13263
13264 public:
13265 CONSTEXPR ifm2_height0_m1_r() : word0(0) {}
13266 CONSTEXPR ifm2_height0_m1_r(uint32_t init) : word0(init) {}
13267 CONSTEXPR void operator=(uint32_t value)
13268 {
13269 word0 = value;
13270 }
13271 void operator=(uint32_t value) volatile
13272 {
13273 word0 = value;
13274 }
13275 CONSTEXPR operator uint32_t()
13276 {
13277 return word0;
13278 }
13279 operator uint32_t() volatile
13280 {
13281 return word0;
13282 }
13283 ifm2_height0_m1_r copy() volatile
13284 {
13285 return *this;
13286 }
13287 CONSTEXPR uint32_t get_value() const
13288 {
13289 uint32_t value = word0;
13290 return value;
13291 }
13292 uint32_t get_value() const volatile
13293 {
13294 uint32_t value = word0;
13295 return value;
13296 }
13297 CONSTEXPR ifm2_height0_m1_r &set_value(uint32_t value)
13298 {
13299 word0 = value;
13300 return *this;
13301 }
13302 volatile ifm2_height0_m1_r &set_value(uint32_t value) volatile
13303 {
13304 word0 = value;
13305 return *this;
13306 }
13307#endif
13308};
13309
13310// ifm2_height1_m1_r - None
13311struct ifm2_height1_m1_r
13312{
13313#ifndef __cplusplus
13314 union
13315 {
13316 struct
13317 {
13318 uint32_t value : 32; // 32-bit register value
13319 };
13320 uint32_t word;
13321 };
13322#else
13323 private:
13324 uint32_t word0;
13325
13326 public:
13327 CONSTEXPR ifm2_height1_m1_r() : word0(0) {}
13328 CONSTEXPR ifm2_height1_m1_r(uint32_t init) : word0(init) {}
13329 CONSTEXPR void operator=(uint32_t value)
13330 {
13331 word0 = value;
13332 }
13333 void operator=(uint32_t value) volatile
13334 {
13335 word0 = value;
13336 }
13337 CONSTEXPR operator uint32_t()
13338 {
13339 return word0;
13340 }
13341 operator uint32_t() volatile
13342 {
13343 return word0;
13344 }
13345 ifm2_height1_m1_r copy() volatile
13346 {
13347 return *this;
13348 }
13349 CONSTEXPR uint32_t get_value() const
13350 {
13351 uint32_t value = word0;
13352 return value;
13353 }
13354 uint32_t get_value() const volatile
13355 {
13356 uint32_t value = word0;
13357 return value;
13358 }
13359 CONSTEXPR ifm2_height1_m1_r &set_value(uint32_t value)
13360 {
13361 word0 = value;
13362 return *this;
13363 }
13364 volatile ifm2_height1_m1_r &set_value(uint32_t value) volatile
13365 {
13366 word0 = value;
13367 return *this;
13368 }
13369#endif
13370};
13371
13372// ifm2_ib_start_r - None
13373struct ifm2_ib_start_r
13374{
13375#ifndef __cplusplus
13376 union
13377 {
13378 struct
13379 {
13380 uint32_t value : 32; // 32-bit register value
13381 };
13382 uint32_t word;
13383 };
13384#else
13385 private:
13386 uint32_t word0;
13387
13388 public:
13389 CONSTEXPR ifm2_ib_start_r() : word0(0) {}
13390 CONSTEXPR ifm2_ib_start_r(uint32_t init) : word0(init) {}
13391 CONSTEXPR void operator=(uint32_t value)
13392 {
13393 word0 = value;
13394 }
13395 void operator=(uint32_t value) volatile
13396 {
13397 word0 = value;
13398 }
13399 CONSTEXPR operator uint32_t()
13400 {
13401 return word0;
13402 }
13403 operator uint32_t() volatile
13404 {
13405 return word0;
13406 }
13407 ifm2_ib_start_r copy() volatile
13408 {
13409 return *this;
13410 }
13411 CONSTEXPR uint32_t get_value() const
13412 {
13413 uint32_t value = word0;
13414 return value;
13415 }
13416 uint32_t get_value() const volatile
13417 {
13418 uint32_t value = word0;
13419 return value;
13420 }
13421 CONSTEXPR ifm2_ib_start_r &set_value(uint32_t value)
13422 {
13423 word0 = value;
13424 return *this;
13425 }
13426 volatile ifm2_ib_start_r &set_value(uint32_t value) volatile
13427 {
13428 word0 = value;
13429 return *this;
13430 }
13431#endif
13432};
13433
13434// ifm2_region_r - None
13435struct ifm2_region_r
13436{
13437#ifndef __cplusplus
13438 union
13439 {
13440 struct
13441 {
13442 uint32_t value : 32; // 32-bit register value
13443 };
13444 uint32_t word;
13445 };
13446#else
13447 private:
13448 uint32_t word0;
13449
13450 public:
13451 CONSTEXPR ifm2_region_r() : word0(0) {}
13452 CONSTEXPR ifm2_region_r(uint32_t init) : word0(init) {}
13453 CONSTEXPR void operator=(uint32_t value)
13454 {
13455 word0 = value;
13456 }
13457 void operator=(uint32_t value) volatile
13458 {
13459 word0 = value;
13460 }
13461 CONSTEXPR operator uint32_t()
13462 {
13463 return word0;
13464 }
13465 operator uint32_t() volatile
13466 {
13467 return word0;
13468 }
13469 ifm2_region_r copy() volatile
13470 {
13471 return *this;
13472 }
13473 CONSTEXPR uint32_t get_value() const
13474 {
13475 uint32_t value = word0;
13476 return value;
13477 }
13478 uint32_t get_value() const volatile
13479 {
13480 uint32_t value = word0;
13481 return value;
13482 }
13483 CONSTEXPR ifm2_region_r &set_value(uint32_t value)
13484 {
13485 word0 = value;
13486 return *this;
13487 }
13488 volatile ifm2_region_r &set_value(uint32_t value) volatile
13489 {
13490 word0 = value;
13491 return *this;
13492 }
13493#endif
13494};
13495
13496// ifm_base0_r - None
13497struct ifm_base0_r
13498{
13499#ifndef __cplusplus
13500 union
13501 {
13502 struct
13503 {
13504 uint32_t value_LO : 32; // 64-bit register value - LSB
13505 uint32_t value_HI : 32; // 64-bit register value - MSB
13506 };
13507 uint32_t word[2];
13508 };
13509#else
13510 private:
13511 uint32_t word0;
13512 uint32_t word1;
13513
13514 public:
13515 CONSTEXPR ifm_base0_r() : word0(0), word1(0) {}
13516 CONSTEXPR ifm_base0_r(uint64_t init) :
13517 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13518 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13519 {
13520 }
13521 CONSTEXPR void operator=(uint64_t value)
13522 {
13523 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13524 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13525 }
13526 void operator=(uint64_t value) volatile
13527 {
13528 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13529 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13530 }
13531 CONSTEXPR operator uint64_t()
13532 {
13533 return (static_cast<uint64_t>(word1) << 32) | word0;
13534 }
13535 operator uint64_t() volatile
13536 {
13537 return (static_cast<uint64_t>(word1) << 32) | word0;
13538 }
13539 ifm_base0_r copy() volatile
13540 {
13541 return *this;
13542 }
13543#endif
13544};
13545
13546// ifm_base1_r - None
13547struct ifm_base1_r
13548{
13549#ifndef __cplusplus
13550 union
13551 {
13552 struct
13553 {
13554 uint32_t value_LO : 32; // 64-bit register value - LSB
13555 uint32_t value_HI : 32; // 64-bit register value - MSB
13556 };
13557 uint32_t word[2];
13558 };
13559#else
13560 private:
13561 uint32_t word0;
13562 uint32_t word1;
13563
13564 public:
13565 CONSTEXPR ifm_base1_r() : word0(0), word1(0) {}
13566 CONSTEXPR ifm_base1_r(uint64_t init) :
13567 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13568 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13569 {
13570 }
13571 CONSTEXPR void operator=(uint64_t value)
13572 {
13573 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13574 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13575 }
13576 void operator=(uint64_t value) volatile
13577 {
13578 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13579 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13580 }
13581 CONSTEXPR operator uint64_t()
13582 {
13583 return (static_cast<uint64_t>(word1) << 32) | word0;
13584 }
13585 operator uint64_t() volatile
13586 {
13587 return (static_cast<uint64_t>(word1) << 32) | word0;
13588 }
13589 ifm_base1_r copy() volatile
13590 {
13591 return *this;
13592 }
13593#endif
13594};
13595
13596// ifm_base2_r - None
13597struct ifm_base2_r
13598{
13599#ifndef __cplusplus
13600 union
13601 {
13602 struct
13603 {
13604 uint32_t value_LO : 32; // 64-bit register value - LSB
13605 uint32_t value_HI : 32; // 64-bit register value - MSB
13606 };
13607 uint32_t word[2];
13608 };
13609#else
13610 private:
13611 uint32_t word0;
13612 uint32_t word1;
13613
13614 public:
13615 CONSTEXPR ifm_base2_r() : word0(0), word1(0) {}
13616 CONSTEXPR ifm_base2_r(uint64_t init) :
13617 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13618 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13619 {
13620 }
13621 CONSTEXPR void operator=(uint64_t value)
13622 {
13623 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13624 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13625 }
13626 void operator=(uint64_t value) volatile
13627 {
13628 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13629 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13630 }
13631 CONSTEXPR operator uint64_t()
13632 {
13633 return (static_cast<uint64_t>(word1) << 32) | word0;
13634 }
13635 operator uint64_t() volatile
13636 {
13637 return (static_cast<uint64_t>(word1) << 32) | word0;
13638 }
13639 ifm_base2_r copy() volatile
13640 {
13641 return *this;
13642 }
13643#endif
13644};
13645
13646// ifm_base3_r - None
13647struct ifm_base3_r
13648{
13649#ifndef __cplusplus
13650 union
13651 {
13652 struct
13653 {
13654 uint32_t value_LO : 32; // 64-bit register value - LSB
13655 uint32_t value_HI : 32; // 64-bit register value - MSB
13656 };
13657 uint32_t word[2];
13658 };
13659#else
13660 private:
13661 uint32_t word0;
13662 uint32_t word1;
13663
13664 public:
13665 CONSTEXPR ifm_base3_r() : word0(0), word1(0) {}
13666 CONSTEXPR ifm_base3_r(uint64_t init) :
13667 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13668 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13669 {
13670 }
13671 CONSTEXPR void operator=(uint64_t value)
13672 {
13673 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13674 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13675 }
13676 void operator=(uint64_t value) volatile
13677 {
13678 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13679 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13680 }
13681 CONSTEXPR operator uint64_t()
13682 {
13683 return (static_cast<uint64_t>(word1) << 32) | word0;
13684 }
13685 operator uint64_t() volatile
13686 {
13687 return (static_cast<uint64_t>(word1) << 32) | word0;
13688 }
13689 ifm_base3_r copy() volatile
13690 {
13691 return *this;
13692 }
13693#endif
13694};
13695
13696// ifm_stride_x_r - None
13697struct ifm_stride_x_r
13698{
13699#ifndef __cplusplus
13700 union
13701 {
13702 struct
13703 {
13704 uint32_t value_LO : 32; // 64-bit register value - LSB
13705 uint32_t value_HI : 32; // 64-bit register value - MSB
13706 };
13707 uint32_t word[2];
13708 };
13709#else
13710 private:
13711 uint32_t word0;
13712 uint32_t word1;
13713
13714 public:
13715 CONSTEXPR ifm_stride_x_r() : word0(0), word1(0) {}
13716 CONSTEXPR ifm_stride_x_r(uint64_t init) :
13717 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13718 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13719 {
13720 }
13721 CONSTEXPR void operator=(uint64_t value)
13722 {
13723 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13724 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13725 }
13726 void operator=(uint64_t value) volatile
13727 {
13728 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13729 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13730 }
13731 CONSTEXPR operator uint64_t()
13732 {
13733 return (static_cast<uint64_t>(word1) << 32) | word0;
13734 }
13735 operator uint64_t() volatile
13736 {
13737 return (static_cast<uint64_t>(word1) << 32) | word0;
13738 }
13739 ifm_stride_x_r copy() volatile
13740 {
13741 return *this;
13742 }
13743#endif
13744};
13745
13746// ifm_stride_y_r - None
13747struct ifm_stride_y_r
13748{
13749#ifndef __cplusplus
13750 union
13751 {
13752 struct
13753 {
13754 uint32_t value_LO : 32; // 64-bit register value - LSB
13755 uint32_t value_HI : 32; // 64-bit register value - MSB
13756 };
13757 uint32_t word[2];
13758 };
13759#else
13760 private:
13761 uint32_t word0;
13762 uint32_t word1;
13763
13764 public:
13765 CONSTEXPR ifm_stride_y_r() : word0(0), word1(0) {}
13766 CONSTEXPR ifm_stride_y_r(uint64_t init) :
13767 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13768 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13769 {
13770 }
13771 CONSTEXPR void operator=(uint64_t value)
13772 {
13773 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13774 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13775 }
13776 void operator=(uint64_t value) volatile
13777 {
13778 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13779 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13780 }
13781 CONSTEXPR operator uint64_t()
13782 {
13783 return (static_cast<uint64_t>(word1) << 32) | word0;
13784 }
13785 operator uint64_t() volatile
13786 {
13787 return (static_cast<uint64_t>(word1) << 32) | word0;
13788 }
13789 ifm_stride_y_r copy() volatile
13790 {
13791 return *this;
13792 }
13793#endif
13794};
13795
13796// ifm_stride_c_r - None
13797struct ifm_stride_c_r
13798{
13799#ifndef __cplusplus
13800 union
13801 {
13802 struct
13803 {
13804 uint32_t value_LO : 32; // 64-bit register value - LSB
13805 uint32_t value_HI : 32; // 64-bit register value - MSB
13806 };
13807 uint32_t word[2];
13808 };
13809#else
13810 private:
13811 uint32_t word0;
13812 uint32_t word1;
13813
13814 public:
13815 CONSTEXPR ifm_stride_c_r() : word0(0), word1(0) {}
13816 CONSTEXPR ifm_stride_c_r(uint64_t init) :
13817 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13818 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13819 {
13820 }
13821 CONSTEXPR void operator=(uint64_t value)
13822 {
13823 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13824 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13825 }
13826 void operator=(uint64_t value) volatile
13827 {
13828 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13829 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13830 }
13831 CONSTEXPR operator uint64_t()
13832 {
13833 return (static_cast<uint64_t>(word1) << 32) | word0;
13834 }
13835 operator uint64_t() volatile
13836 {
13837 return (static_cast<uint64_t>(word1) << 32) | word0;
13838 }
13839 ifm_stride_c_r copy() volatile
13840 {
13841 return *this;
13842 }
13843#endif
13844};
13845
13846// ofm_base0_r - None
13847struct ofm_base0_r
13848{
13849#ifndef __cplusplus
13850 union
13851 {
13852 struct
13853 {
13854 uint32_t value_LO : 32; // 64-bit register value - LSB
13855 uint32_t value_HI : 32; // 64-bit register value - MSB
13856 };
13857 uint32_t word[2];
13858 };
13859#else
13860 private:
13861 uint32_t word0;
13862 uint32_t word1;
13863
13864 public:
13865 CONSTEXPR ofm_base0_r() : word0(0), word1(0) {}
13866 CONSTEXPR ofm_base0_r(uint64_t init) :
13867 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13868 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13869 {
13870 }
13871 CONSTEXPR void operator=(uint64_t value)
13872 {
13873 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13874 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13875 }
13876 void operator=(uint64_t value) volatile
13877 {
13878 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13879 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13880 }
13881 CONSTEXPR operator uint64_t()
13882 {
13883 return (static_cast<uint64_t>(word1) << 32) | word0;
13884 }
13885 operator uint64_t() volatile
13886 {
13887 return (static_cast<uint64_t>(word1) << 32) | word0;
13888 }
13889 ofm_base0_r copy() volatile
13890 {
13891 return *this;
13892 }
13893#endif
13894};
13895
13896// ofm_base1_r - None
13897struct ofm_base1_r
13898{
13899#ifndef __cplusplus
13900 union
13901 {
13902 struct
13903 {
13904 uint32_t value_LO : 32; // 64-bit register value - LSB
13905 uint32_t value_HI : 32; // 64-bit register value - MSB
13906 };
13907 uint32_t word[2];
13908 };
13909#else
13910 private:
13911 uint32_t word0;
13912 uint32_t word1;
13913
13914 public:
13915 CONSTEXPR ofm_base1_r() : word0(0), word1(0) {}
13916 CONSTEXPR ofm_base1_r(uint64_t init) :
13917 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13918 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13919 {
13920 }
13921 CONSTEXPR void operator=(uint64_t value)
13922 {
13923 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13924 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13925 }
13926 void operator=(uint64_t value) volatile
13927 {
13928 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13929 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13930 }
13931 CONSTEXPR operator uint64_t()
13932 {
13933 return (static_cast<uint64_t>(word1) << 32) | word0;
13934 }
13935 operator uint64_t() volatile
13936 {
13937 return (static_cast<uint64_t>(word1) << 32) | word0;
13938 }
13939 ofm_base1_r copy() volatile
13940 {
13941 return *this;
13942 }
13943#endif
13944};
13945
13946// ofm_base2_r - None
13947struct ofm_base2_r
13948{
13949#ifndef __cplusplus
13950 union
13951 {
13952 struct
13953 {
13954 uint32_t value_LO : 32; // 64-bit register value - LSB
13955 uint32_t value_HI : 32; // 64-bit register value - MSB
13956 };
13957 uint32_t word[2];
13958 };
13959#else
13960 private:
13961 uint32_t word0;
13962 uint32_t word1;
13963
13964 public:
13965 CONSTEXPR ofm_base2_r() : word0(0), word1(0) {}
13966 CONSTEXPR ofm_base2_r(uint64_t init) :
13967 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
13968 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
13969 {
13970 }
13971 CONSTEXPR void operator=(uint64_t value)
13972 {
13973 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13974 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13975 }
13976 void operator=(uint64_t value) volatile
13977 {
13978 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
13979 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
13980 }
13981 CONSTEXPR operator uint64_t()
13982 {
13983 return (static_cast<uint64_t>(word1) << 32) | word0;
13984 }
13985 operator uint64_t() volatile
13986 {
13987 return (static_cast<uint64_t>(word1) << 32) | word0;
13988 }
13989 ofm_base2_r copy() volatile
13990 {
13991 return *this;
13992 }
13993#endif
13994};
13995
13996// ofm_base3_r - None
13997struct ofm_base3_r
13998{
13999#ifndef __cplusplus
14000 union
14001 {
14002 struct
14003 {
14004 uint32_t value_LO : 32; // 64-bit register value - LSB
14005 uint32_t value_HI : 32; // 64-bit register value - MSB
14006 };
14007 uint32_t word[2];
14008 };
14009#else
14010 private:
14011 uint32_t word0;
14012 uint32_t word1;
14013
14014 public:
14015 CONSTEXPR ofm_base3_r() : word0(0), word1(0) {}
14016 CONSTEXPR ofm_base3_r(uint64_t init) :
14017 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14018 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14019 {
14020 }
14021 CONSTEXPR void operator=(uint64_t value)
14022 {
14023 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14024 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14025 }
14026 void operator=(uint64_t value) volatile
14027 {
14028 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14029 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14030 }
14031 CONSTEXPR operator uint64_t()
14032 {
14033 return (static_cast<uint64_t>(word1) << 32) | word0;
14034 }
14035 operator uint64_t() volatile
14036 {
14037 return (static_cast<uint64_t>(word1) << 32) | word0;
14038 }
14039 ofm_base3_r copy() volatile
14040 {
14041 return *this;
14042 }
14043#endif
14044};
14045
14046// ofm_stride_x_r - None
14047struct ofm_stride_x_r
14048{
14049#ifndef __cplusplus
14050 union
14051 {
14052 struct
14053 {
14054 uint32_t value_LO : 32; // 64-bit register value - LSB
14055 uint32_t value_HI : 32; // 64-bit register value - MSB
14056 };
14057 uint32_t word[2];
14058 };
14059#else
14060 private:
14061 uint32_t word0;
14062 uint32_t word1;
14063
14064 public:
14065 CONSTEXPR ofm_stride_x_r() : word0(0), word1(0) {}
14066 CONSTEXPR ofm_stride_x_r(uint64_t init) :
14067 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14068 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14069 {
14070 }
14071 CONSTEXPR void operator=(uint64_t value)
14072 {
14073 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14074 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14075 }
14076 void operator=(uint64_t value) volatile
14077 {
14078 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14079 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14080 }
14081 CONSTEXPR operator uint64_t()
14082 {
14083 return (static_cast<uint64_t>(word1) << 32) | word0;
14084 }
14085 operator uint64_t() volatile
14086 {
14087 return (static_cast<uint64_t>(word1) << 32) | word0;
14088 }
14089 ofm_stride_x_r copy() volatile
14090 {
14091 return *this;
14092 }
14093#endif
14094};
14095
14096// ofm_stride_y_r - None
14097struct ofm_stride_y_r
14098{
14099#ifndef __cplusplus
14100 union
14101 {
14102 struct
14103 {
14104 uint32_t value_LO : 32; // 64-bit register value - LSB
14105 uint32_t value_HI : 32; // 64-bit register value - MSB
14106 };
14107 uint32_t word[2];
14108 };
14109#else
14110 private:
14111 uint32_t word0;
14112 uint32_t word1;
14113
14114 public:
14115 CONSTEXPR ofm_stride_y_r() : word0(0), word1(0) {}
14116 CONSTEXPR ofm_stride_y_r(uint64_t init) :
14117 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14118 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14119 {
14120 }
14121 CONSTEXPR void operator=(uint64_t value)
14122 {
14123 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14124 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14125 }
14126 void operator=(uint64_t value) volatile
14127 {
14128 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14129 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14130 }
14131 CONSTEXPR operator uint64_t()
14132 {
14133 return (static_cast<uint64_t>(word1) << 32) | word0;
14134 }
14135 operator uint64_t() volatile
14136 {
14137 return (static_cast<uint64_t>(word1) << 32) | word0;
14138 }
14139 ofm_stride_y_r copy() volatile
14140 {
14141 return *this;
14142 }
14143#endif
14144};
14145
14146// ofm_stride_c_r - None
14147struct ofm_stride_c_r
14148{
14149#ifndef __cplusplus
14150 union
14151 {
14152 struct
14153 {
14154 uint32_t value_LO : 32; // 64-bit register value - LSB
14155 uint32_t value_HI : 32; // 64-bit register value - MSB
14156 };
14157 uint32_t word[2];
14158 };
14159#else
14160 private:
14161 uint32_t word0;
14162 uint32_t word1;
14163
14164 public:
14165 CONSTEXPR ofm_stride_c_r() : word0(0), word1(0) {}
14166 CONSTEXPR ofm_stride_c_r(uint64_t init) :
14167 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14168 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14169 {
14170 }
14171 CONSTEXPR void operator=(uint64_t value)
14172 {
14173 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14174 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14175 }
14176 void operator=(uint64_t value) volatile
14177 {
14178 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14179 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14180 }
14181 CONSTEXPR operator uint64_t()
14182 {
14183 return (static_cast<uint64_t>(word1) << 32) | word0;
14184 }
14185 operator uint64_t() volatile
14186 {
14187 return (static_cast<uint64_t>(word1) << 32) | word0;
14188 }
14189 ofm_stride_c_r copy() volatile
14190 {
14191 return *this;
14192 }
14193#endif
14194};
14195
14196// weight_base_r - None
14197struct weight_base_r
14198{
14199#ifndef __cplusplus
14200 union
14201 {
14202 struct
14203 {
14204 uint32_t value_LO : 32; // 64-bit register value - LSB
14205 uint32_t value_HI : 32; // 64-bit register value - MSB
14206 };
14207 uint32_t word[2];
14208 };
14209#else
14210 private:
14211 uint32_t word0;
14212 uint32_t word1;
14213
14214 public:
14215 CONSTEXPR weight_base_r() : word0(0), word1(0) {}
14216 CONSTEXPR weight_base_r(uint64_t init) :
14217 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14218 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14219 {
14220 }
14221 CONSTEXPR void operator=(uint64_t value)
14222 {
14223 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14224 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14225 }
14226 void operator=(uint64_t value) volatile
14227 {
14228 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14229 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14230 }
14231 CONSTEXPR operator uint64_t()
14232 {
14233 return (static_cast<uint64_t>(word1) << 32) | word0;
14234 }
14235 operator uint64_t() volatile
14236 {
14237 return (static_cast<uint64_t>(word1) << 32) | word0;
14238 }
14239 weight_base_r copy() volatile
14240 {
14241 return *this;
14242 }
14243#endif
14244};
14245
14246// weight_length_r - None
14247struct weight_length_r
14248{
14249#ifndef __cplusplus
14250 union
14251 {
14252 struct
14253 {
14254 uint32_t value_LO : 32; // 64-bit register value - LSB
14255 uint32_t value_HI : 32; // 64-bit register value - MSB
14256 };
14257 uint32_t word[2];
14258 };
14259#else
14260 private:
14261 uint32_t word0;
14262 uint32_t word1;
14263
14264 public:
14265 CONSTEXPR weight_length_r() : word0(0), word1(0) {}
14266 CONSTEXPR weight_length_r(uint64_t init) :
14267 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14268 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14269 {
14270 }
14271 CONSTEXPR void operator=(uint64_t value)
14272 {
14273 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14274 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14275 }
14276 void operator=(uint64_t value) volatile
14277 {
14278 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14279 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14280 }
14281 CONSTEXPR operator uint64_t()
14282 {
14283 return (static_cast<uint64_t>(word1) << 32) | word0;
14284 }
14285 operator uint64_t() volatile
14286 {
14287 return (static_cast<uint64_t>(word1) << 32) | word0;
14288 }
14289 weight_length_r copy() volatile
14290 {
14291 return *this;
14292 }
14293#endif
14294};
14295
14296// scale_base_r - None
14297struct scale_base_r
14298{
14299#ifndef __cplusplus
14300 union
14301 {
14302 struct
14303 {
14304 uint32_t value_LO : 32; // 64-bit register value - LSB
14305 uint32_t value_HI : 32; // 64-bit register value - MSB
14306 };
14307 uint32_t word[2];
14308 };
14309#else
14310 private:
14311 uint32_t word0;
14312 uint32_t word1;
14313
14314 public:
14315 CONSTEXPR scale_base_r() : word0(0), word1(0) {}
14316 CONSTEXPR scale_base_r(uint64_t init) :
14317 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14318 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14319 {
14320 }
14321 CONSTEXPR void operator=(uint64_t value)
14322 {
14323 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14324 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14325 }
14326 void operator=(uint64_t value) volatile
14327 {
14328 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14329 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14330 }
14331 CONSTEXPR operator uint64_t()
14332 {
14333 return (static_cast<uint64_t>(word1) << 32) | word0;
14334 }
14335 operator uint64_t() volatile
14336 {
14337 return (static_cast<uint64_t>(word1) << 32) | word0;
14338 }
14339 scale_base_r copy() volatile
14340 {
14341 return *this;
14342 }
14343#endif
14344};
14345
14346// scale_length_r - None
14347struct scale_length_r
14348{
14349#ifndef __cplusplus
14350 union
14351 {
14352 struct
14353 {
14354 uint32_t value_LO : 32; // 64-bit register value - LSB
14355 uint32_t value_HI : 32; // 64-bit register value - MSB
14356 };
14357 uint32_t word[2];
14358 };
14359#else
14360 private:
14361 uint32_t word0;
14362 uint32_t word1;
14363
14364 public:
14365 CONSTEXPR scale_length_r() : word0(0), word1(0) {}
14366 CONSTEXPR scale_length_r(uint64_t init) :
14367 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14368 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14369 {
14370 }
14371 CONSTEXPR void operator=(uint64_t value)
14372 {
14373 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14374 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14375 }
14376 void operator=(uint64_t value) volatile
14377 {
14378 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14379 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14380 }
14381 CONSTEXPR operator uint64_t()
14382 {
14383 return (static_cast<uint64_t>(word1) << 32) | word0;
14384 }
14385 operator uint64_t() volatile
14386 {
14387 return (static_cast<uint64_t>(word1) << 32) | word0;
14388 }
14389 scale_length_r copy() volatile
14390 {
14391 return *this;
14392 }
14393#endif
14394};
14395
14396// ofm_scale_r - None
14397struct ofm_scale_r
14398{
14399#ifndef __cplusplus
14400 union
14401 {
14402 struct
14403 {
14404 uint32_t value : 32; // 32-bit register value
14405 };
14406 uint32_t word;
14407 };
14408#else
14409 private:
14410 uint32_t word0;
14411
14412 public:
14413 CONSTEXPR ofm_scale_r() : word0(0) {}
14414 CONSTEXPR ofm_scale_r(uint32_t init) : word0(init) {}
14415 CONSTEXPR void operator=(uint32_t value)
14416 {
14417 word0 = value;
14418 }
14419 void operator=(uint32_t value) volatile
14420 {
14421 word0 = value;
14422 }
14423 CONSTEXPR operator uint32_t()
14424 {
14425 return word0;
14426 }
14427 operator uint32_t() volatile
14428 {
14429 return word0;
14430 }
14431 ofm_scale_r copy() volatile
14432 {
14433 return *this;
14434 }
14435 CONSTEXPR uint32_t get_value() const
14436 {
14437 uint32_t value = word0;
14438 return value;
14439 }
14440 uint32_t get_value() const volatile
14441 {
14442 uint32_t value = word0;
14443 return value;
14444 }
14445 CONSTEXPR ofm_scale_r &set_value(uint32_t value)
14446 {
14447 word0 = value;
14448 return *this;
14449 }
14450 volatile ofm_scale_r &set_value(uint32_t value) volatile
14451 {
14452 word0 = value;
14453 return *this;
14454 }
14455#endif
14456};
14457
14458// ofm_scale_shift_r - None
14459struct ofm_scale_shift_r
14460{
14461#ifndef __cplusplus
14462 union
14463 {
14464 struct
14465 {
14466 uint32_t value : 32; // 32-bit register value
14467 };
14468 uint32_t word;
14469 };
14470#else
14471 private:
14472 uint32_t word0;
14473
14474 public:
14475 CONSTEXPR ofm_scale_shift_r() : word0(0) {}
14476 CONSTEXPR ofm_scale_shift_r(uint32_t init) : word0(init) {}
14477 CONSTEXPR void operator=(uint32_t value)
14478 {
14479 word0 = value;
14480 }
14481 void operator=(uint32_t value) volatile
14482 {
14483 word0 = value;
14484 }
14485 CONSTEXPR operator uint32_t()
14486 {
14487 return word0;
14488 }
14489 operator uint32_t() volatile
14490 {
14491 return word0;
14492 }
14493 ofm_scale_shift_r copy() volatile
14494 {
14495 return *this;
14496 }
14497 CONSTEXPR uint32_t get_value() const
14498 {
14499 uint32_t value = word0;
14500 return value;
14501 }
14502 uint32_t get_value() const volatile
14503 {
14504 uint32_t value = word0;
14505 return value;
14506 }
14507 CONSTEXPR ofm_scale_shift_r &set_value(uint32_t value)
14508 {
14509 word0 = value;
14510 return *this;
14511 }
14512 volatile ofm_scale_shift_r &set_value(uint32_t value) volatile
14513 {
14514 word0 = value;
14515 return *this;
14516 }
14517#endif
14518};
14519
14520// opa_scale_r - None
14521struct opa_scale_r
14522{
14523#ifndef __cplusplus
14524 union
14525 {
14526 struct
14527 {
14528 uint32_t value : 32; // 32-bit register value
14529 };
14530 uint32_t word;
14531 };
14532#else
14533 private:
14534 uint32_t word0;
14535
14536 public:
14537 CONSTEXPR opa_scale_r() : word0(0) {}
14538 CONSTEXPR opa_scale_r(uint32_t init) : word0(init) {}
14539 CONSTEXPR void operator=(uint32_t value)
14540 {
14541 word0 = value;
14542 }
14543 void operator=(uint32_t value) volatile
14544 {
14545 word0 = value;
14546 }
14547 CONSTEXPR operator uint32_t()
14548 {
14549 return word0;
14550 }
14551 operator uint32_t() volatile
14552 {
14553 return word0;
14554 }
14555 opa_scale_r copy() volatile
14556 {
14557 return *this;
14558 }
14559 CONSTEXPR uint32_t get_value() const
14560 {
14561 uint32_t value = word0;
14562 return value;
14563 }
14564 uint32_t get_value() const volatile
14565 {
14566 uint32_t value = word0;
14567 return value;
14568 }
14569 CONSTEXPR opa_scale_r &set_value(uint32_t value)
14570 {
14571 word0 = value;
14572 return *this;
14573 }
14574 volatile opa_scale_r &set_value(uint32_t value) volatile
14575 {
14576 word0 = value;
14577 return *this;
14578 }
14579#endif
14580};
14581
14582// opa_scale_shift_r - None
14583struct opa_scale_shift_r
14584{
14585#ifndef __cplusplus
14586 union
14587 {
14588 struct
14589 {
14590 uint32_t value : 32; // 32-bit register value
14591 };
14592 uint32_t word;
14593 };
14594#else
14595 private:
14596 uint32_t word0;
14597
14598 public:
14599 CONSTEXPR opa_scale_shift_r() : word0(0) {}
14600 CONSTEXPR opa_scale_shift_r(uint32_t init) : word0(init) {}
14601 CONSTEXPR void operator=(uint32_t value)
14602 {
14603 word0 = value;
14604 }
14605 void operator=(uint32_t value) volatile
14606 {
14607 word0 = value;
14608 }
14609 CONSTEXPR operator uint32_t()
14610 {
14611 return word0;
14612 }
14613 operator uint32_t() volatile
14614 {
14615 return word0;
14616 }
14617 opa_scale_shift_r copy() volatile
14618 {
14619 return *this;
14620 }
14621 CONSTEXPR uint32_t get_value() const
14622 {
14623 uint32_t value = word0;
14624 return value;
14625 }
14626 uint32_t get_value() const volatile
14627 {
14628 uint32_t value = word0;
14629 return value;
14630 }
14631 CONSTEXPR opa_scale_shift_r &set_value(uint32_t value)
14632 {
14633 word0 = value;
14634 return *this;
14635 }
14636 volatile opa_scale_shift_r &set_value(uint32_t value) volatile
14637 {
14638 word0 = value;
14639 return *this;
14640 }
14641#endif
14642};
14643
14644// opb_scale_r - None
14645struct opb_scale_r
14646{
14647#ifndef __cplusplus
14648 union
14649 {
14650 struct
14651 {
14652 uint32_t value : 32; // 32-bit register value
14653 };
14654 uint32_t word;
14655 };
14656#else
14657 private:
14658 uint32_t word0;
14659
14660 public:
14661 CONSTEXPR opb_scale_r() : word0(0) {}
14662 CONSTEXPR opb_scale_r(uint32_t init) : word0(init) {}
14663 CONSTEXPR void operator=(uint32_t value)
14664 {
14665 word0 = value;
14666 }
14667 void operator=(uint32_t value) volatile
14668 {
14669 word0 = value;
14670 }
14671 CONSTEXPR operator uint32_t()
14672 {
14673 return word0;
14674 }
14675 operator uint32_t() volatile
14676 {
14677 return word0;
14678 }
14679 opb_scale_r copy() volatile
14680 {
14681 return *this;
14682 }
14683 CONSTEXPR uint32_t get_value() const
14684 {
14685 uint32_t value = word0;
14686 return value;
14687 }
14688 uint32_t get_value() const volatile
14689 {
14690 uint32_t value = word0;
14691 return value;
14692 }
14693 CONSTEXPR opb_scale_r &set_value(uint32_t value)
14694 {
14695 word0 = value;
14696 return *this;
14697 }
14698 volatile opb_scale_r &set_value(uint32_t value) volatile
14699 {
14700 word0 = value;
14701 return *this;
14702 }
14703#endif
14704};
14705
14706// dma0_src_r - None
14707struct dma0_src_r
14708{
14709#ifndef __cplusplus
14710 union
14711 {
14712 struct
14713 {
14714 uint32_t value_LO : 32; // 64-bit register value - LSB
14715 uint32_t value_HI : 32; // 64-bit register value - MSB
14716 };
14717 uint32_t word[2];
14718 };
14719#else
14720 private:
14721 uint32_t word0;
14722 uint32_t word1;
14723
14724 public:
14725 CONSTEXPR dma0_src_r() : word0(0), word1(0) {}
14726 CONSTEXPR dma0_src_r(uint64_t init) :
14727 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14728 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14729 {
14730 }
14731 CONSTEXPR void operator=(uint64_t value)
14732 {
14733 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14734 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14735 }
14736 void operator=(uint64_t value) volatile
14737 {
14738 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14739 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14740 }
14741 CONSTEXPR operator uint64_t()
14742 {
14743 return (static_cast<uint64_t>(word1) << 32) | word0;
14744 }
14745 operator uint64_t() volatile
14746 {
14747 return (static_cast<uint64_t>(word1) << 32) | word0;
14748 }
14749 dma0_src_r copy() volatile
14750 {
14751 return *this;
14752 }
14753#endif
14754};
14755
14756// dma0_dst_r - None
14757struct dma0_dst_r
14758{
14759#ifndef __cplusplus
14760 union
14761 {
14762 struct
14763 {
14764 uint32_t value_LO : 32; // 64-bit register value - LSB
14765 uint32_t value_HI : 32; // 64-bit register value - MSB
14766 };
14767 uint32_t word[2];
14768 };
14769#else
14770 private:
14771 uint32_t word0;
14772 uint32_t word1;
14773
14774 public:
14775 CONSTEXPR dma0_dst_r() : word0(0), word1(0) {}
14776 CONSTEXPR dma0_dst_r(uint64_t init) :
14777 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14778 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14779 {
14780 }
14781 CONSTEXPR void operator=(uint64_t value)
14782 {
14783 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14784 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14785 }
14786 void operator=(uint64_t value) volatile
14787 {
14788 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14789 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14790 }
14791 CONSTEXPR operator uint64_t()
14792 {
14793 return (static_cast<uint64_t>(word1) << 32) | word0;
14794 }
14795 operator uint64_t() volatile
14796 {
14797 return (static_cast<uint64_t>(word1) << 32) | word0;
14798 }
14799 dma0_dst_r copy() volatile
14800 {
14801 return *this;
14802 }
14803#endif
14804};
14805
14806// dma0_len_r - None
14807struct dma0_len_r
14808{
14809#ifndef __cplusplus
14810 union
14811 {
14812 struct
14813 {
14814 uint32_t value_LO : 32; // 64-bit register value - LSB
14815 uint32_t value_HI : 32; // 64-bit register value - MSB
14816 };
14817 uint32_t word[2];
14818 };
14819#else
14820 private:
14821 uint32_t word0;
14822 uint32_t word1;
14823
14824 public:
14825 CONSTEXPR dma0_len_r() : word0(0), word1(0) {}
14826 CONSTEXPR dma0_len_r(uint64_t init) :
14827 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14828 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14829 {
14830 }
14831 CONSTEXPR void operator=(uint64_t value)
14832 {
14833 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14834 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14835 }
14836 void operator=(uint64_t value) volatile
14837 {
14838 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14839 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14840 }
14841 CONSTEXPR operator uint64_t()
14842 {
14843 return (static_cast<uint64_t>(word1) << 32) | word0;
14844 }
14845 operator uint64_t() volatile
14846 {
14847 return (static_cast<uint64_t>(word1) << 32) | word0;
14848 }
14849 dma0_len_r copy() volatile
14850 {
14851 return *this;
14852 }
14853#endif
14854};
14855
14856// dma0_skip0_r - None
14858{
14859#ifndef __cplusplus
14860 union
14861 {
14862 struct
14863 {
14864 uint32_t value_LO : 32; // 64-bit register value - LSB
14865 uint32_t value_HI : 32; // 64-bit register value - MSB
14866 };
14867 uint32_t word[2];
14868 };
14869#else
14870 private:
14871 uint32_t word0;
14872 uint32_t word1;
14873
14874 public:
14875 CONSTEXPR dma0_skip0_r() : word0(0), word1(0) {}
14876 CONSTEXPR dma0_skip0_r(uint64_t init) :
14877 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14878 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14879 {
14880 }
14881 CONSTEXPR void operator=(uint64_t value)
14882 {
14883 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14884 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14885 }
14886 void operator=(uint64_t value) volatile
14887 {
14888 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14889 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14890 }
14891 CONSTEXPR operator uint64_t()
14892 {
14893 return (static_cast<uint64_t>(word1) << 32) | word0;
14894 }
14895 operator uint64_t() volatile
14896 {
14897 return (static_cast<uint64_t>(word1) << 32) | word0;
14898 }
14899 dma0_skip0_r copy() volatile
14900 {
14901 return *this;
14902 }
14903#endif
14904};
14905
14906// dma0_skip1_r - None
14908{
14909#ifndef __cplusplus
14910 union
14911 {
14912 struct
14913 {
14914 uint32_t value_LO : 32; // 64-bit register value - LSB
14915 uint32_t value_HI : 32; // 64-bit register value - MSB
14916 };
14917 uint32_t word[2];
14918 };
14919#else
14920 private:
14921 uint32_t word0;
14922 uint32_t word1;
14923
14924 public:
14925 CONSTEXPR dma0_skip1_r() : word0(0), word1(0) {}
14926 CONSTEXPR dma0_skip1_r(uint64_t init) :
14927 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14928 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14929 {
14930 }
14931 CONSTEXPR void operator=(uint64_t value)
14932 {
14933 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14934 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14935 }
14936 void operator=(uint64_t value) volatile
14937 {
14938 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14939 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14940 }
14941 CONSTEXPR operator uint64_t()
14942 {
14943 return (static_cast<uint64_t>(word1) << 32) | word0;
14944 }
14945 operator uint64_t() volatile
14946 {
14947 return (static_cast<uint64_t>(word1) << 32) | word0;
14948 }
14949 dma0_skip1_r copy() volatile
14950 {
14951 return *this;
14952 }
14953#endif
14954};
14955
14956// ifm2_base0_r - None
14957struct ifm2_base0_r
14958{
14959#ifndef __cplusplus
14960 union
14961 {
14962 struct
14963 {
14964 uint32_t value_LO : 32; // 64-bit register value - LSB
14965 uint32_t value_HI : 32; // 64-bit register value - MSB
14966 };
14967 uint32_t word[2];
14968 };
14969#else
14970 private:
14971 uint32_t word0;
14972 uint32_t word1;
14973
14974 public:
14975 CONSTEXPR ifm2_base0_r() : word0(0), word1(0) {}
14976 CONSTEXPR ifm2_base0_r(uint64_t init) :
14977 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
14978 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
14979 {
14980 }
14981 CONSTEXPR void operator=(uint64_t value)
14982 {
14983 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14984 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14985 }
14986 void operator=(uint64_t value) volatile
14987 {
14988 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
14989 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
14990 }
14991 CONSTEXPR operator uint64_t()
14992 {
14993 return (static_cast<uint64_t>(word1) << 32) | word0;
14994 }
14995 operator uint64_t() volatile
14996 {
14997 return (static_cast<uint64_t>(word1) << 32) | word0;
14998 }
14999 ifm2_base0_r copy() volatile
15000 {
15001 return *this;
15002 }
15003#endif
15004};
15005
15006// ifm2_base1_r - None
15007struct ifm2_base1_r
15008{
15009#ifndef __cplusplus
15010 union
15011 {
15012 struct
15013 {
15014 uint32_t value_LO : 32; // 64-bit register value - LSB
15015 uint32_t value_HI : 32; // 64-bit register value - MSB
15016 };
15017 uint32_t word[2];
15018 };
15019#else
15020 private:
15021 uint32_t word0;
15022 uint32_t word1;
15023
15024 public:
15025 CONSTEXPR ifm2_base1_r() : word0(0), word1(0) {}
15026 CONSTEXPR ifm2_base1_r(uint64_t init) :
15027 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15028 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15029 {
15030 }
15031 CONSTEXPR void operator=(uint64_t value)
15032 {
15033 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15034 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15035 }
15036 void operator=(uint64_t value) volatile
15037 {
15038 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15039 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15040 }
15041 CONSTEXPR operator uint64_t()
15042 {
15043 return (static_cast<uint64_t>(word1) << 32) | word0;
15044 }
15045 operator uint64_t() volatile
15046 {
15047 return (static_cast<uint64_t>(word1) << 32) | word0;
15048 }
15049 ifm2_base1_r copy() volatile
15050 {
15051 return *this;
15052 }
15053#endif
15054};
15055
15056// ifm2_base2_r - None
15057struct ifm2_base2_r
15058{
15059#ifndef __cplusplus
15060 union
15061 {
15062 struct
15063 {
15064 uint32_t value_LO : 32; // 64-bit register value - LSB
15065 uint32_t value_HI : 32; // 64-bit register value - MSB
15066 };
15067 uint32_t word[2];
15068 };
15069#else
15070 private:
15071 uint32_t word0;
15072 uint32_t word1;
15073
15074 public:
15075 CONSTEXPR ifm2_base2_r() : word0(0), word1(0) {}
15076 CONSTEXPR ifm2_base2_r(uint64_t init) :
15077 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15078 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15079 {
15080 }
15081 CONSTEXPR void operator=(uint64_t value)
15082 {
15083 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15084 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15085 }
15086 void operator=(uint64_t value) volatile
15087 {
15088 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15089 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15090 }
15091 CONSTEXPR operator uint64_t()
15092 {
15093 return (static_cast<uint64_t>(word1) << 32) | word0;
15094 }
15095 operator uint64_t() volatile
15096 {
15097 return (static_cast<uint64_t>(word1) << 32) | word0;
15098 }
15099 ifm2_base2_r copy() volatile
15100 {
15101 return *this;
15102 }
15103#endif
15104};
15105
15106// ifm2_base3_r - None
15107struct ifm2_base3_r
15108{
15109#ifndef __cplusplus
15110 union
15111 {
15112 struct
15113 {
15114 uint32_t value_LO : 32; // 64-bit register value - LSB
15115 uint32_t value_HI : 32; // 64-bit register value - MSB
15116 };
15117 uint32_t word[2];
15118 };
15119#else
15120 private:
15121 uint32_t word0;
15122 uint32_t word1;
15123
15124 public:
15125 CONSTEXPR ifm2_base3_r() : word0(0), word1(0) {}
15126 CONSTEXPR ifm2_base3_r(uint64_t init) :
15127 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15128 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15129 {
15130 }
15131 CONSTEXPR void operator=(uint64_t value)
15132 {
15133 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15134 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15135 }
15136 void operator=(uint64_t value) volatile
15137 {
15138 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15139 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15140 }
15141 CONSTEXPR operator uint64_t()
15142 {
15143 return (static_cast<uint64_t>(word1) << 32) | word0;
15144 }
15145 operator uint64_t() volatile
15146 {
15147 return (static_cast<uint64_t>(word1) << 32) | word0;
15148 }
15149 ifm2_base3_r copy() volatile
15150 {
15151 return *this;
15152 }
15153#endif
15154};
15155
15156// ifm2_stride_x_r - None
15157struct ifm2_stride_x_r
15158{
15159#ifndef __cplusplus
15160 union
15161 {
15162 struct
15163 {
15164 uint32_t value_LO : 32; // 64-bit register value - LSB
15165 uint32_t value_HI : 32; // 64-bit register value - MSB
15166 };
15167 uint32_t word[2];
15168 };
15169#else
15170 private:
15171 uint32_t word0;
15172 uint32_t word1;
15173
15174 public:
15175 CONSTEXPR ifm2_stride_x_r() : word0(0), word1(0) {}
15176 CONSTEXPR ifm2_stride_x_r(uint64_t init) :
15177 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15178 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15179 {
15180 }
15181 CONSTEXPR void operator=(uint64_t value)
15182 {
15183 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15184 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15185 }
15186 void operator=(uint64_t value) volatile
15187 {
15188 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15189 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15190 }
15191 CONSTEXPR operator uint64_t()
15192 {
15193 return (static_cast<uint64_t>(word1) << 32) | word0;
15194 }
15195 operator uint64_t() volatile
15196 {
15197 return (static_cast<uint64_t>(word1) << 32) | word0;
15198 }
15199 ifm2_stride_x_r copy() volatile
15200 {
15201 return *this;
15202 }
15203#endif
15204};
15205
15206// ifm2_stride_y_r - None
15207struct ifm2_stride_y_r
15208{
15209#ifndef __cplusplus
15210 union
15211 {
15212 struct
15213 {
15214 uint32_t value_LO : 32; // 64-bit register value - LSB
15215 uint32_t value_HI : 32; // 64-bit register value - MSB
15216 };
15217 uint32_t word[2];
15218 };
15219#else
15220 private:
15221 uint32_t word0;
15222 uint32_t word1;
15223
15224 public:
15225 CONSTEXPR ifm2_stride_y_r() : word0(0), word1(0) {}
15226 CONSTEXPR ifm2_stride_y_r(uint64_t init) :
15227 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15228 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15229 {
15230 }
15231 CONSTEXPR void operator=(uint64_t value)
15232 {
15233 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15234 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15235 }
15236 void operator=(uint64_t value) volatile
15237 {
15238 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15239 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15240 }
15241 CONSTEXPR operator uint64_t()
15242 {
15243 return (static_cast<uint64_t>(word1) << 32) | word0;
15244 }
15245 operator uint64_t() volatile
15246 {
15247 return (static_cast<uint64_t>(word1) << 32) | word0;
15248 }
15249 ifm2_stride_y_r copy() volatile
15250 {
15251 return *this;
15252 }
15253#endif
15254};
15255
15256// ifm2_stride_c_r - None
15257struct ifm2_stride_c_r
15258{
15259#ifndef __cplusplus
15260 union
15261 {
15262 struct
15263 {
15264 uint32_t value_LO : 32; // 64-bit register value - LSB
15265 uint32_t value_HI : 32; // 64-bit register value - MSB
15266 };
15267 uint32_t word[2];
15268 };
15269#else
15270 private:
15271 uint32_t word0;
15272 uint32_t word1;
15273
15274 public:
15275 CONSTEXPR ifm2_stride_c_r() : word0(0), word1(0) {}
15276 CONSTEXPR ifm2_stride_c_r(uint64_t init) :
15277 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15278 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15279 {
15280 }
15281 CONSTEXPR void operator=(uint64_t value)
15282 {
15283 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15284 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15285 }
15286 void operator=(uint64_t value) volatile
15287 {
15288 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15289 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15290 }
15291 CONSTEXPR operator uint64_t()
15292 {
15293 return (static_cast<uint64_t>(word1) << 32) | word0;
15294 }
15295 operator uint64_t() volatile
15296 {
15297 return (static_cast<uint64_t>(word1) << 32) | word0;
15298 }
15299 ifm2_stride_c_r copy() volatile
15300 {
15301 return *this;
15302 }
15303#endif
15304};
15305
15306// weight1_base_r - None
15308{
15309#ifndef __cplusplus
15310 union
15311 {
15312 struct
15313 {
15314 uint32_t value_LO : 32; // 64-bit register value - LSB
15315 uint32_t value_HI : 32; // 64-bit register value - MSB
15316 };
15317 uint32_t word[2];
15318 };
15319#else
15320 private:
15321 uint32_t word0;
15322 uint32_t word1;
15323
15324 public:
15325 CONSTEXPR weight1_base_r() : word0(0), word1(0) {}
15326 CONSTEXPR weight1_base_r(uint64_t init) :
15327 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15328 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15329 {
15330 }
15331 CONSTEXPR void operator=(uint64_t value)
15332 {
15333 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15334 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15335 }
15336 void operator=(uint64_t value) volatile
15337 {
15338 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15339 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15340 }
15341 CONSTEXPR operator uint64_t()
15342 {
15343 return (static_cast<uint64_t>(word1) << 32) | word0;
15344 }
15345 operator uint64_t() volatile
15346 {
15347 return (static_cast<uint64_t>(word1) << 32) | word0;
15348 }
15349 weight1_base_r copy() volatile
15350 {
15351 return *this;
15352 }
15353#endif
15354};
15355
15356// weight1_length_r - None
15358{
15359#ifndef __cplusplus
15360 union
15361 {
15362 struct
15363 {
15364 uint32_t value_LO : 32; // 64-bit register value - LSB
15365 uint32_t value_HI : 32; // 64-bit register value - MSB
15366 };
15367 uint32_t word[2];
15368 };
15369#else
15370 private:
15371 uint32_t word0;
15372 uint32_t word1;
15373
15374 public:
15375 CONSTEXPR weight1_length_r() : word0(0), word1(0) {}
15376 CONSTEXPR weight1_length_r(uint64_t init) :
15377 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15378 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15379 {
15380 }
15381 CONSTEXPR void operator=(uint64_t value)
15382 {
15383 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15384 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15385 }
15386 void operator=(uint64_t value) volatile
15387 {
15388 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15389 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15390 }
15391 CONSTEXPR operator uint64_t()
15392 {
15393 return (static_cast<uint64_t>(word1) << 32) | word0;
15394 }
15395 operator uint64_t() volatile
15396 {
15397 return (static_cast<uint64_t>(word1) << 32) | word0;
15398 }
15399 weight1_length_r copy() volatile
15400 {
15401 return *this;
15402 }
15403#endif
15404};
15405
15406// scale1_base_r - None
15408{
15409#ifndef __cplusplus
15410 union
15411 {
15412 struct
15413 {
15414 uint32_t value_LO : 32; // 64-bit register value - LSB
15415 uint32_t value_HI : 32; // 64-bit register value - MSB
15416 };
15417 uint32_t word[2];
15418 };
15419#else
15420 private:
15421 uint32_t word0;
15422 uint32_t word1;
15423
15424 public:
15425 CONSTEXPR scale1_base_r() : word0(0), word1(0) {}
15426 CONSTEXPR scale1_base_r(uint64_t init) :
15427 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15428 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15429 {
15430 }
15431 CONSTEXPR void operator=(uint64_t value)
15432 {
15433 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15434 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15435 }
15436 void operator=(uint64_t value) volatile
15437 {
15438 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15439 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15440 }
15441 CONSTEXPR operator uint64_t()
15442 {
15443 return (static_cast<uint64_t>(word1) << 32) | word0;
15444 }
15445 operator uint64_t() volatile
15446 {
15447 return (static_cast<uint64_t>(word1) << 32) | word0;
15448 }
15449 scale1_base_r copy() volatile
15450 {
15451 return *this;
15452 }
15453#endif
15454};
15455
15456// scale1_length_r - None
15458{
15459#ifndef __cplusplus
15460 union
15461 {
15462 struct
15463 {
15464 uint32_t value_LO : 32; // 64-bit register value - LSB
15465 uint32_t value_HI : 32; // 64-bit register value - MSB
15466 };
15467 uint32_t word[2];
15468 };
15469#else
15470 private:
15471 uint32_t word0;
15472 uint32_t word1;
15473
15474 public:
15475 CONSTEXPR scale1_length_r() : word0(0), word1(0) {}
15476 CONSTEXPR scale1_length_r(uint64_t init) :
15477 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::max())),
15478 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::max()))
15479 {
15480 }
15481 CONSTEXPR void operator=(uint64_t value)
15482 {
15483 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15484 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15485 }
15486 void operator=(uint64_t value) volatile
15487 {
15488 word0 = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
15489 word1 = static_cast<uint32_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
15490 }
15491 CONSTEXPR operator uint64_t()
15492 {
15493 return (static_cast<uint64_t>(word1) << 32) | word0;
15494 }
15495 operator uint64_t() volatile
15496 {
15497 return (static_cast<uint64_t>(word1) << 32) | word0;
15498 }
15499 scale1_length_r copy() volatile
15500 {
15501 return *this;
15502 }
15503#endif
15504};
15505
15506// revision_r - Internal FPGA build revision: first 32-bits of the Ultan Git hash used for the build
15507struct revision_r
15508{
15509#ifndef __cplusplus
15510 union
15511 {
15512 struct
15513 {
15514 uint32_t value : 32; // 32-bit register value
15515 };
15516 uint32_t word;
15517 };
15518#else
15519 private:
15520 uint32_t word0;
15521
15522 public:
15523 CONSTEXPR revision_r() : word0(0) {}
15524 CONSTEXPR revision_r(uint32_t init) : word0(init) {}
15525 CONSTEXPR void operator=(uint32_t value)
15526 {
15527 word0 = value;
15528 }
15529 void operator=(uint32_t value) volatile
15530 {
15531 word0 = value;
15532 }
15533 CONSTEXPR operator uint32_t()
15534 {
15535 return word0;
15536 }
15537 operator uint32_t() volatile
15538 {
15539 return word0;
15540 }
15541 revision_r copy() volatile
15542 {
15543 return *this;
15544 }
15545 CONSTEXPR uint32_t get_value() const
15546 {
15547 uint32_t value = word0;
15548 return value;
15549 }
15550 uint32_t get_value() const volatile
15551 {
15552 uint32_t value = word0;
15553 return value;
15554 }
15555 CONSTEXPR revision_r &set_value(uint32_t value)
15556 {
15557 word0 = value;
15558 return *this;
15559 }
15560 volatile revision_r &set_value(uint32_t value) volatile
15561 {
15562 word0 = value;
15563 return *this;
15564 }
15565#endif
15566};
15567
15568// pid4_r - Peripheral ID byte 4 (Arm=code 4)
15569struct pid4_r
15570{
15571#ifndef __cplusplus
15572 union
15573 {
15574 struct
15575 {
15576 uint32_t PID4 : 32; // Byte 4 of Peripheral ID (Lower 8 bits valid)
15577 };
15578 uint32_t word;
15579 };
15580#else
15581 private:
15582 uint32_t word0;
15583
15584 public:
15585 CONSTEXPR pid4_r() : word0(4) {}
15586 CONSTEXPR pid4_r(uint32_t init) : word0(init) {}
15587 CONSTEXPR void operator=(uint32_t value)
15588 {
15589 word0 = value;
15590 }
15591 void operator=(uint32_t value) volatile
15592 {
15593 word0 = value;
15594 }
15595 CONSTEXPR operator uint32_t()
15596 {
15597 return word0;
15598 }
15599 operator uint32_t() volatile
15600 {
15601 return word0;
15602 }
15603 pid4_r copy() volatile
15604 {
15605 return *this;
15606 }
15607 CONSTEXPR uint32_t get_PID4() const
15608 {
15609 uint32_t value = word0;
15610 return value;
15611 }
15612 uint32_t get_PID4() const volatile
15613 {
15614 uint32_t value = word0;
15615 return value;
15616 }
15617 CONSTEXPR pid4_r &set_PID4(uint32_t value)
15618 {
15619 word0 = value;
15620 return *this;
15621 }
15622 volatile pid4_r &set_PID4(uint32_t value) volatile
15623 {
15624 word0 = value;
15625 return *this;
15626 }
15627#endif
15628};
15629
15630// pid5_r - Peripheral ID byte 5 (reserved)
15631struct pid5_r
15632{
15633#ifndef __cplusplus
15634 union
15635 {
15636 struct
15637 {
15638 uint32_t PID5 : 32; // Byte 5 of Peripheral ID (Lower 8 bits valid)
15639 };
15640 uint32_t word;
15641 };
15642#else
15643 private:
15644 uint32_t word0;
15645
15646 public:
15647 CONSTEXPR pid5_r() : word0(0) {}
15648 CONSTEXPR pid5_r(uint32_t init) : word0(init) {}
15649 CONSTEXPR void operator=(uint32_t value)
15650 {
15651 word0 = value;
15652 }
15653 void operator=(uint32_t value) volatile
15654 {
15655 word0 = value;
15656 }
15657 CONSTEXPR operator uint32_t()
15658 {
15659 return word0;
15660 }
15661 operator uint32_t() volatile
15662 {
15663 return word0;
15664 }
15665 pid5_r copy() volatile
15666 {
15667 return *this;
15668 }
15669 CONSTEXPR uint32_t get_PID5() const
15670 {
15671 uint32_t value = word0;
15672 return value;
15673 }
15674 uint32_t get_PID5() const volatile
15675 {
15676 uint32_t value = word0;
15677 return value;
15678 }
15679 CONSTEXPR pid5_r &set_PID5(uint32_t value)
15680 {
15681 word0 = value;
15682 return *this;
15683 }
15684 volatile pid5_r &set_PID5(uint32_t value) volatile
15685 {
15686 word0 = value;
15687 return *this;
15688 }
15689#endif
15690};
15691
15692// pid6_r - Peripheral ID byte 6 (reserved)
15693struct pid6_r
15694{
15695#ifndef __cplusplus
15696 union
15697 {
15698 struct
15699 {
15700 uint32_t PID6 : 32; // Byte 6 of Peripheral ID (Lower 8 bits valid)
15701 };
15702 uint32_t word;
15703 };
15704#else
15705 private:
15706 uint32_t word0;
15707
15708 public:
15709 CONSTEXPR pid6_r() : word0(0) {}
15710 CONSTEXPR pid6_r(uint32_t init) : word0(init) {}
15711 CONSTEXPR void operator=(uint32_t value)
15712 {
15713 word0 = value;
15714 }
15715 void operator=(uint32_t value) volatile
15716 {
15717 word0 = value;
15718 }
15719 CONSTEXPR operator uint32_t()
15720 {
15721 return word0;
15722 }
15723 operator uint32_t() volatile
15724 {
15725 return word0;
15726 }
15727 pid6_r copy() volatile
15728 {
15729 return *this;
15730 }
15731 CONSTEXPR uint32_t get_PID6() const
15732 {
15733 uint32_t value = word0;
15734 return value;
15735 }
15736 uint32_t get_PID6() const volatile
15737 {
15738 uint32_t value = word0;
15739 return value;
15740 }
15741 CONSTEXPR pid6_r &set_PID6(uint32_t value)
15742 {
15743 word0 = value;
15744 return *this;
15745 }
15746 volatile pid6_r &set_PID6(uint32_t value) volatile
15747 {
15748 word0 = value;
15749 return *this;
15750 }
15751#endif
15752};
15753
15754// pid7_r - Peripheral ID byte 7 (reserved)
15755struct pid7_r
15756{
15757#ifndef __cplusplus
15758 union
15759 {
15760 struct
15761 {
15762 uint32_t PID7 : 32; // Byte 7 of Peripheral ID (Lower 8 bits valid)
15763 };
15764 uint32_t word;
15765 };
15766#else
15767 private:
15768 uint32_t word0;
15769
15770 public:
15771 CONSTEXPR pid7_r() : word0(0) {}
15772 CONSTEXPR pid7_r(uint32_t init) : word0(init) {}
15773 CONSTEXPR void operator=(uint32_t value)
15774 {
15775 word0 = value;
15776 }
15777 void operator=(uint32_t value) volatile
15778 {
15779 word0 = value;
15780 }
15781 CONSTEXPR operator uint32_t()
15782 {
15783 return word0;
15784 }
15785 operator uint32_t() volatile
15786 {
15787 return word0;
15788 }
15789 pid7_r copy() volatile
15790 {
15791 return *this;
15792 }
15793 CONSTEXPR uint32_t get_PID7() const
15794 {
15795 uint32_t value = word0;
15796 return value;
15797 }
15798 uint32_t get_PID7() const volatile
15799 {
15800 uint32_t value = word0;
15801 return value;
15802 }
15803 CONSTEXPR pid7_r &set_PID7(uint32_t value)
15804 {
15805 word0 = value;
15806 return *this;
15807 }
15808 volatile pid7_r &set_PID7(uint32_t value) volatile
15809 {
15810 word0 = value;
15811 return *this;
15812 }
15813#endif
15814};
15815
15816// pid0_r - Peripheral ID byte 0. This is bits[7:0] of the part number
15817struct pid0_r
15818{
15819#ifndef __cplusplus
15820 union
15821 {
15822 struct
15823 {
15824 uint32_t PID0 : 32; // Byte 0 of Peripheral ID (Lower 8 bits valid)
15825 };
15826 uint32_t word;
15827 };
15828#else
15829 private:
15830 uint32_t word0;
15831
15832 public:
15833 CONSTEXPR pid0_r() : word0(129) {}
15834 CONSTEXPR pid0_r(uint32_t init) : word0(init) {}
15835 CONSTEXPR void operator=(uint32_t value)
15836 {
15837 word0 = value;
15838 }
15839 void operator=(uint32_t value) volatile
15840 {
15841 word0 = value;
15842 }
15843 CONSTEXPR operator uint32_t()
15844 {
15845 return word0;
15846 }
15847 operator uint32_t() volatile
15848 {
15849 return word0;
15850 }
15851 pid0_r copy() volatile
15852 {
15853 return *this;
15854 }
15855 CONSTEXPR uint32_t get_PID0() const
15856 {
15857 uint32_t value = word0;
15858 return value;
15859 }
15860 uint32_t get_PID0() const volatile
15861 {
15862 uint32_t value = word0;
15863 return value;
15864 }
15865 CONSTEXPR pid0_r &set_PID0(uint32_t value)
15866 {
15867 word0 = value;
15868 return *this;
15869 }
15870 volatile pid0_r &set_PID0(uint32_t value) volatile
15871 {
15872 word0 = value;
15873 return *this;
15874 }
15875#endif
15876};
15877
15878// pid1_r - Peripheral ID byte 1. This is bits[11:8] of the part number in bits[3:0], and bits[3:0] of the Arm ID in
15879// bits[7:4]
15880struct pid1_r
15881{
15882#ifndef __cplusplus
15883 union
15884 {
15885 struct
15886 {
15887 uint32_t PID1 : 32; // Byte 1 of Peripheral ID (Lower 8 bits valid)
15888 };
15889 uint32_t word;
15890 };
15891#else
15892 private:
15893 uint32_t word0;
15894
15895 public:
15896 CONSTEXPR pid1_r() : word0(181) {}
15897 CONSTEXPR pid1_r(uint32_t init) : word0(init) {}
15898 CONSTEXPR void operator=(uint32_t value)
15899 {
15900 word0 = value;
15901 }
15902 void operator=(uint32_t value) volatile
15903 {
15904 word0 = value;
15905 }
15906 CONSTEXPR operator uint32_t()
15907 {
15908 return word0;
15909 }
15910 operator uint32_t() volatile
15911 {
15912 return word0;
15913 }
15914 pid1_r copy() volatile
15915 {
15916 return *this;
15917 }
15918 CONSTEXPR uint32_t get_PID1() const
15919 {
15920 uint32_t value = word0;
15921 return value;
15922 }
15923 uint32_t get_PID1() const volatile
15924 {
15925 uint32_t value = word0;
15926 return value;
15927 }
15928 CONSTEXPR pid1_r &set_PID1(uint32_t value)
15929 {
15930 word0 = value;
15931 return *this;
15932 }
15933 volatile pid1_r &set_PID1(uint32_t value) volatile
15934 {
15935 word0 = value;
15936 return *this;
15937 }
15938#endif
15939};
15940
15941// pid2_r - Peripheral ID byte 2. This is bits[6:4] of the Arm ID in bits[2:0], and bit 3 indicates format B
15942struct pid2_r
15943{
15944#ifndef __cplusplus
15945 union
15946 {
15947 struct
15948 {
15949 uint32_t PID2 : 32; // Byte 2 of Peripheral ID (Lower 8 bits valid)
15950 };
15951 uint32_t word;
15952 };
15953#else
15954 private:
15955 uint32_t word0;
15956
15957 public:
15958 CONSTEXPR pid2_r() : word0(11) {}
15959 CONSTEXPR pid2_r(uint32_t init) : word0(init) {}
15960 CONSTEXPR void operator=(uint32_t value)
15961 {
15962 word0 = value;
15963 }
15964 void operator=(uint32_t value) volatile
15965 {
15966 word0 = value;
15967 }
15968 CONSTEXPR operator uint32_t()
15969 {
15970 return word0;
15971 }
15972 operator uint32_t() volatile
15973 {
15974 return word0;
15975 }
15976 pid2_r copy() volatile
15977 {
15978 return *this;
15979 }
15980 CONSTEXPR uint32_t get_PID2() const
15981 {
15982 uint32_t value = word0;
15983 return value;
15984 }
15985 uint32_t get_PID2() const volatile
15986 {
15987 uint32_t value = word0;
15988 return value;
15989 }
15990 CONSTEXPR pid2_r &set_PID2(uint32_t value)
15991 {
15992 word0 = value;
15993 return *this;
15994 }
15995 volatile pid2_r &set_PID2(uint32_t value) volatile
15996 {
15997 word0 = value;
15998 return *this;
15999 }
16000#endif
16001};
16002
16003// pid3_r - Peripheral ID byte 3
16004struct pid3_r
16005{
16006#ifndef __cplusplus
16007 union
16008 {
16009 struct
16010 {
16011 uint32_t PID3 : 32; // Byte 1 of Peripheral ID (Lower 8 bits valid)
16012 };
16013 uint32_t word;
16014 };
16015#else
16016 private:
16017 uint32_t word0;
16018
16019 public:
16020 CONSTEXPR pid3_r() : word0(0) {}
16021 CONSTEXPR pid3_r(uint32_t init) : word0(init) {}
16022 CONSTEXPR void operator=(uint32_t value)
16023 {
16024 word0 = value;
16025 }
16026 void operator=(uint32_t value) volatile
16027 {
16028 word0 = value;
16029 }
16030 CONSTEXPR operator uint32_t()
16031 {
16032 return word0;
16033 }
16034 operator uint32_t() volatile
16035 {
16036 return word0;
16037 }
16038 pid3_r copy() volatile
16039 {
16040 return *this;
16041 }
16042 CONSTEXPR uint32_t get_PID3() const
16043 {
16044 uint32_t value = word0;
16045 return value;
16046 }
16047 uint32_t get_PID3() const volatile
16048 {
16049 uint32_t value = word0;
16050 return value;
16051 }
16052 CONSTEXPR pid3_r &set_PID3(uint32_t value)
16053 {
16054 word0 = value;
16055 return *this;
16056 }
16057 volatile pid3_r &set_PID3(uint32_t value) volatile
16058 {
16059 word0 = value;
16060 return *this;
16061 }
16062#endif
16063};
16064
16065// cid0_r - Component ID byte 0
16066struct cid0_r
16067{
16068#ifndef __cplusplus
16069 union
16070 {
16071 struct
16072 {
16073 uint32_t CID0 : 32; // Byte 0 of Component ID (Lower 8 bits valid)
16074 };
16075 uint32_t word;
16076 };
16077#else
16078 private:
16079 uint32_t word0;
16080
16081 public:
16082 CONSTEXPR cid0_r() : word0(13) {}
16083 CONSTEXPR cid0_r(uint32_t init) : word0(init) {}
16084 CONSTEXPR void operator=(uint32_t value)
16085 {
16086 word0 = value;
16087 }
16088 void operator=(uint32_t value) volatile
16089 {
16090 word0 = value;
16091 }
16092 CONSTEXPR operator uint32_t()
16093 {
16094 return word0;
16095 }
16096 operator uint32_t() volatile
16097 {
16098 return word0;
16099 }
16100 cid0_r copy() volatile
16101 {
16102 return *this;
16103 }
16104 CONSTEXPR uint32_t get_CID0() const
16105 {
16106 uint32_t value = word0;
16107 return value;
16108 }
16109 uint32_t get_CID0() const volatile
16110 {
16111 uint32_t value = word0;
16112 return value;
16113 }
16114 CONSTEXPR cid0_r &set_CID0(uint32_t value)
16115 {
16116 word0 = value;
16117 return *this;
16118 }
16119 volatile cid0_r &set_CID0(uint32_t value) volatile
16120 {
16121 word0 = value;
16122 return *this;
16123 }
16124#endif
16125};
16126
16127// cid1_r - Component ID byte 1
16128struct cid1_r
16129{
16130#ifndef __cplusplus
16131 union
16132 {
16133 struct
16134 {
16135 uint32_t CID1 : 32; // Byte 1 of Component ID (Lower 8 bits valid)
16136 };
16137 uint32_t word;
16138 };
16139#else
16140 private:
16141 uint32_t word0;
16142
16143 public:
16144 CONSTEXPR cid1_r() : word0(240) {}
16145 CONSTEXPR cid1_r(uint32_t init) : word0(init) {}
16146 CONSTEXPR void operator=(uint32_t value)
16147 {
16148 word0 = value;
16149 }
16150 void operator=(uint32_t value) volatile
16151 {
16152 word0 = value;
16153 }
16154 CONSTEXPR operator uint32_t()
16155 {
16156 return word0;
16157 }
16158 operator uint32_t() volatile
16159 {
16160 return word0;
16161 }
16162 cid1_r copy() volatile
16163 {
16164 return *this;
16165 }
16166 CONSTEXPR uint32_t get_CID1() const
16167 {
16168 uint32_t value = word0;
16169 return value;
16170 }
16171 uint32_t get_CID1() const volatile
16172 {
16173 uint32_t value = word0;
16174 return value;
16175 }
16176 CONSTEXPR cid1_r &set_CID1(uint32_t value)
16177 {
16178 word0 = value;
16179 return *this;
16180 }
16181 volatile cid1_r &set_CID1(uint32_t value) volatile
16182 {
16183 word0 = value;
16184 return *this;
16185 }
16186#endif
16187};
16188
16189// cid2_r - Component ID byte 2
16190struct cid2_r
16191{
16192#ifndef __cplusplus
16193 union
16194 {
16195 struct
16196 {
16197 uint32_t CID2 : 32; // Byte 2 of Component ID (Lower 8 bits valid)
16198 };
16199 uint32_t word;
16200 };
16201#else
16202 private:
16203 uint32_t word0;
16204
16205 public:
16206 CONSTEXPR cid2_r() : word0(5) {}
16207 CONSTEXPR cid2_r(uint32_t init) : word0(init) {}
16208 CONSTEXPR void operator=(uint32_t value)
16209 {
16210 word0 = value;
16211 }
16212 void operator=(uint32_t value) volatile
16213 {
16214 word0 = value;
16215 }
16216 CONSTEXPR operator uint32_t()
16217 {
16218 return word0;
16219 }
16220 operator uint32_t() volatile
16221 {
16222 return word0;
16223 }
16224 cid2_r copy() volatile
16225 {
16226 return *this;
16227 }
16228 CONSTEXPR uint32_t get_CID2() const
16229 {
16230 uint32_t value = word0;
16231 return value;
16232 }
16233 uint32_t get_CID2() const volatile
16234 {
16235 uint32_t value = word0;
16236 return value;
16237 }
16238 CONSTEXPR cid2_r &set_CID2(uint32_t value)
16239 {
16240 word0 = value;
16241 return *this;
16242 }
16243 volatile cid2_r &set_CID2(uint32_t value) volatile
16244 {
16245 word0 = value;
16246 return *this;
16247 }
16248#endif
16249};
16250
16251// cid3_r - Component ID byte 3
16252struct cid3_r
16253{
16254#ifndef __cplusplus
16255 union
16256 {
16257 struct
16258 {
16259 uint32_t CID3 : 32; // Byte 3 of Component ID (Lower 8 bits valid)
16260 };
16261 uint32_t word;
16262 };
16263#else
16264 private:
16265 uint32_t word0;
16266
16267 public:
16268 CONSTEXPR cid3_r() : word0(177) {}
16269 CONSTEXPR cid3_r(uint32_t init) : word0(init) {}
16270 CONSTEXPR void operator=(uint32_t value)
16271 {
16272 word0 = value;
16273 }
16274 void operator=(uint32_t value) volatile
16275 {
16276 word0 = value;
16277 }
16278 CONSTEXPR operator uint32_t()
16279 {
16280 return word0;
16281 }
16282 operator uint32_t() volatile
16283 {
16284 return word0;
16285 }
16286 cid3_r copy() volatile
16287 {
16288 return *this;
16289 }
16290 CONSTEXPR uint32_t get_CID3() const
16291 {
16292 uint32_t value = word0;
16293 return value;
16294 }
16295 uint32_t get_CID3() const volatile
16296 {
16297 uint32_t value = word0;
16298 return value;
16299 }
16300 CONSTEXPR cid3_r &set_CID3(uint32_t value)
16301 {
16302 word0 = value;
16303 return *this;
16304 }
16305 volatile cid3_r &set_CID3(uint32_t value) volatile
16306 {
16307 word0 = value;
16308 return *this;
16309 }
16310#endif
16311};
16312
16313struct NPU_REG
16314{
16315 STRUCT id_r ID; // 0x0000
16316 STRUCT status_r STATUS; // 0x0004
16317 STRUCT cmd_r CMD; // 0x0008
16318 STRUCT reset_r RESET; // 0x000C
16319 STRUCT qbase_r QBASE; // 0x0010
16320 STRUCT qread_r QREAD; // 0x0018
16321 STRUCT qconfig_r QCONFIG; // 0x001C
16322 STRUCT qsize_r QSIZE; // 0x0020
16323 STRUCT prot_r PROT; // 0x0024
16324 STRUCT config_r CONFIG; // 0x0028
16325 STRUCT lock_r LOCK; // 0x002C
16326 uint32_t unused0[3];
16327 STRUCT regioncfg_r REGIONCFG; // 0x003C
16328 STRUCT axi_limit0_r AXI_LIMIT0; // 0x0040
16329 STRUCT axi_limit1_r AXI_LIMIT1; // 0x0044
16330 STRUCT axi_limit2_r AXI_LIMIT2; // 0x0048
16331 STRUCT axi_limit3_r AXI_LIMIT3; // 0x004C
16332 uint32_t unused1[12];
16333 STRUCT basep_r BASEP[8]; // 0x0080
16334 uint32_t unused2[16];
16335 STRUCT wd_status_r WD_STATUS; // 0x0100
16336 STRUCT mac_status_r MAC_STATUS; // 0x0104
16337 STRUCT ao_status_r AO_STATUS; // 0x0108
16338 uint32_t unused3[1];
16339 STRUCT dma_status0_r DMA_STATUS0; // 0x0110
16340 STRUCT dma_status1_r DMA_STATUS1; // 0x0114
16341 uint32_t unused4[10];
16342 STRUCT clkforce_r CLKFORCE; // 0x0140
16343 STRUCT debug_address_r DEBUG_ADDRESS; // 0x0144
16344 STRUCT debug_misc_r DEBUG_MISC; // 0x0148
16346 STRUCT debug_block_r DEBUG_BLOCK; // 0x0150
16347 uint32_t unused5[11];
16348 STRUCT pmcr_r PMCR; // 0x0180
16349 STRUCT pmcntenset_r PMCNTENSET; // 0x0184
16350 STRUCT pmcntenclr_r PMCNTENCLR; // 0x0188
16351 STRUCT pmovsset_r PMOVSSET; // 0x018C
16352 STRUCT pmovsclr_r PMOVSCLR; // 0x0190
16353 STRUCT pmintset_r PMINTSET; // 0x0194
16354 STRUCT pmintclr_r PMINTCLR; // 0x0198
16355 uint32_t unused6[1];
16356 STRUCT pmccntr_r PMCCNTR; // 0x01A0
16357 STRUCT pmccntr_cfg_r PMCCNTR_CFG; // 0x01A8
16358 STRUCT pmcaxi_chan_r PMCAXI_CHAN; // 0x01AC
16359 uint32_t unused7[20];
16360 STRUCT kernel_x_r KERNEL_X; // 0x0200
16361 STRUCT kernel_y_r KERNEL_Y; // 0x0204
16362 STRUCT kernel_w_m1_r KERNEL_W_M1; // 0x0208
16363 STRUCT kernel_h_m1_r KERNEL_H_M1; // 0x020C
16364 STRUCT ofm_cblk_width_m1_r OFM_CBLK_WIDTH_M1; // 0x0210
16365 STRUCT ofm_cblk_height_m1_r OFM_CBLK_HEIGHT_M1; // 0x0214
16366 STRUCT ofm_cblk_depth_m1_r OFM_CBLK_DEPTH_M1; // 0x0218
16367 STRUCT ifm_cblk_depth_m1_r IFM_CBLK_DEPTH_M1; // 0x021C
16368 STRUCT ofm_x_r OFM_X; // 0x0220
16369 STRUCT ofm_y_r OFM_Y; // 0x0224
16370 STRUCT ofm_z_r OFM_Z; // 0x0228
16371 STRUCT ifm_z_r IFM_Z; // 0x022C
16372 STRUCT pad_top_r PAD_TOP; // 0x0230
16373 STRUCT pad_left_r PAD_LEFT; // 0x0234
16374 STRUCT ifm_cblk_width_r IFM_CBLK_WIDTH; // 0x0238
16375 STRUCT ifm_cblk_height_r IFM_CBLK_HEIGHT; // 0x023C
16376 STRUCT dma_ifm_src_r DMA_IFM_SRC; // 0x0240
16377 STRUCT dma_ifm_dst_r DMA_IFM_DST; // 0x0248
16378 STRUCT dma_ofm_src_r DMA_OFM_SRC; // 0x024C
16379 STRUCT dma_ofm_dst_r DMA_OFM_DST; // 0x0250
16380 STRUCT dma_weight_src_r DMA_WEIGHT_SRC; // 0x0258
16381 STRUCT dma_cmd_src_r DMA_CMD_SRC; // 0x0260
16382 STRUCT dma_cmd_size_r DMA_CMD_SIZE; // 0x0268
16383 STRUCT dma_m2m_src_r DMA_M2M_SRC; // 0x026C
16384 STRUCT dma_m2m_dst_r DMA_M2M_DST; // 0x0274
16385 STRUCT current_qread_r CURRENT_QREAD; // 0x027C
16386 STRUCT dma_scale_src_r DMA_SCALE_SRC; // 0x0280
16387 uint32_t unused8[11];
16388 STRUCT current_block_r CURRENT_BLOCK; // 0x02B4
16389 STRUCT current_op_r CURRENT_OP; // 0x02B8
16390 STRUCT current_cmd_r CURRENT_CMD; // 0x02BC
16391 uint32_t unused9[16];
16392 STRUCT pmevcntr_r PMEVCNTR[4]; // 0x0300
16393 uint32_t unused10[28];
16394 STRUCT pmevtyper_r PMEVTYPER[4]; // 0x0380
16395 uint32_t unused11[28];
16396 STRUCT shared_buffer_r SHARED_BUFFER[256]; // 0x0400
16397 STRUCT ifm_pad_top_r IFM_PAD_TOP; // 0x0800
16398 STRUCT ifm_pad_left_r IFM_PAD_LEFT; // 0x0804
16399 STRUCT ifm_pad_right_r IFM_PAD_RIGHT; // 0x0808
16400 STRUCT ifm_pad_bottom_r IFM_PAD_BOTTOM; // 0x080C
16401 STRUCT ifm_depth_m1_r IFM_DEPTH_M1; // 0x0810
16402 STRUCT ifm_precision_r IFM_PRECISION; // 0x0814
16403 uint32_t unused12[1];
16404 STRUCT ifm_upscale_r IFM_UPSCALE; // 0x081C
16405 uint32_t unused13[1];
16406 STRUCT ifm_zero_point_r IFM_ZERO_POINT; // 0x0824
16407 STRUCT ifm_width0_m1_r IFM_WIDTH0_M1; // 0x0828
16408 STRUCT ifm_height0_m1_r IFM_HEIGHT0_M1; // 0x082C
16409 STRUCT ifm_height1_m1_r IFM_HEIGHT1_M1; // 0x0830
16410 STRUCT ifm_ib_end_r IFM_IB_END; // 0x0834
16411 uint32_t unused14[1];
16412 STRUCT ifm_region_r IFM_REGION; // 0x083C
16413 uint32_t unused15[1];
16414 STRUCT ofm_width_m1_r OFM_WIDTH_M1; // 0x0844
16415 STRUCT ofm_height_m1_r OFM_HEIGHT_M1; // 0x0848
16416 STRUCT ofm_depth_m1_r OFM_DEPTH_M1; // 0x084C
16417 STRUCT ofm_precision_r OFM_PRECISION; // 0x0850
16418 STRUCT ofm_blk_width_m1_r OFM_BLK_WIDTH_M1; // 0x0854
16419 STRUCT ofm_blk_height_m1_r OFM_BLK_HEIGHT_M1; // 0x0858
16420 STRUCT ofm_blk_depth_m1_r OFM_BLK_DEPTH_M1; // 0x085C
16421 STRUCT ofm_zero_point_r OFM_ZERO_POINT; // 0x0860
16422 uint32_t unused16[1];
16423 STRUCT ofm_width0_m1_r OFM_WIDTH0_M1; // 0x0868
16424 STRUCT ofm_height0_m1_r OFM_HEIGHT0_M1; // 0x086C
16425 STRUCT ofm_height1_m1_r OFM_HEIGHT1_M1; // 0x0870
16426 uint32_t unused17[2];
16427 STRUCT ofm_region_r OFM_REGION; // 0x087C
16428 STRUCT kernel_width_m1_r KERNEL_WIDTH_M1; // 0x0880
16429 STRUCT kernel_height_m1_r KERNEL_HEIGHT_M1; // 0x0884
16430 STRUCT kernel_stride_r KERNEL_STRIDE; // 0x0888
16432 STRUCT acc_format_r ACC_FORMAT; // 0x0890
16433 STRUCT activation_r ACTIVATION; // 0x0894
16434 STRUCT activation_min_r ACTIVATION_MIN; // 0x0898
16435 STRUCT activation_max_r ACTIVATION_MAX; // 0x089C
16436 STRUCT weight_region_r WEIGHT_REGION; // 0x08A0
16437 STRUCT scale_region_r SCALE_REGION; // 0x08A4
16438 uint32_t unused18[3];
16439 STRUCT ab_start_r AB_START; // 0x08B4
16440 uint32_t unused19[1];
16441 STRUCT blockdep_r BLOCKDEP; // 0x08BC
16442 STRUCT dma0_src_region_r DMA0_SRC_REGION; // 0x08C0
16443 STRUCT dma0_dst_region_r DMA0_DST_REGION; // 0x08C4
16444 STRUCT dma0_size0_r DMA0_SIZE0; // 0x08C8
16445 STRUCT dma0_size1_r DMA0_SIZE1; // 0x08CC
16446 uint32_t unused20[12];
16447 STRUCT ifm2_broadcast_r IFM2_BROADCAST; // 0x0900
16448 STRUCT ifm2_scalar_r IFM2_SCALAR; // 0x0904
16449 uint32_t unused21[3];
16450 STRUCT ifm2_precision_r IFM2_PRECISION; // 0x0914
16451 uint32_t unused22[3];
16452 STRUCT ifm2_zero_point_r IFM2_ZERO_POINT; // 0x0924
16453 STRUCT ifm2_width0_m1_r IFM2_WIDTH0_M1; // 0x0928
16454 STRUCT ifm2_height0_m1_r IFM2_HEIGHT0_M1; // 0x092C
16455 STRUCT ifm2_height1_m1_r IFM2_HEIGHT1_M1; // 0x0930
16456 STRUCT ifm2_ib_start_r IFM2_IB_START; // 0x0934
16457 uint32_t unused23[1];
16458 STRUCT ifm2_region_r IFM2_REGION; // 0x093C
16459 uint32_t unused24[48];
16460 STRUCT ifm_base0_r IFM_BASE0; // 0x0A00
16461 STRUCT ifm_base1_r IFM_BASE1; // 0x0A08
16462 STRUCT ifm_base2_r IFM_BASE2; // 0x0A10
16463 STRUCT ifm_base3_r IFM_BASE3; // 0x0A18
16464 STRUCT ifm_stride_x_r IFM_STRIDE_X; // 0x0A20
16465 STRUCT ifm_stride_y_r IFM_STRIDE_Y; // 0x0A28
16466 STRUCT ifm_stride_c_r IFM_STRIDE_C; // 0x0A30
16467 uint32_t unused25[2];
16468 STRUCT ofm_base0_r OFM_BASE0; // 0x0A40
16469 STRUCT ofm_base1_r OFM_BASE1; // 0x0A48
16470 STRUCT ofm_base2_r OFM_BASE2; // 0x0A50
16471 STRUCT ofm_base3_r OFM_BASE3; // 0x0A58
16472 STRUCT ofm_stride_x_r OFM_STRIDE_X; // 0x0A60
16473 STRUCT ofm_stride_y_r OFM_STRIDE_Y; // 0x0A68
16474 STRUCT ofm_stride_c_r OFM_STRIDE_C; // 0x0A70
16475 uint32_t unused26[2];
16476 STRUCT weight_base_r WEIGHT_BASE; // 0x0A80
16477 STRUCT weight_length_r WEIGHT_LENGTH; // 0x0A88
16478 STRUCT scale_base_r SCALE_BASE; // 0x0A90
16479 STRUCT scale_length_r SCALE_LENGTH; // 0x0A98
16480 STRUCT ofm_scale_r OFM_SCALE; // 0x0AA0
16481 STRUCT ofm_scale_shift_r OFM_SCALE_SHIFT; // 0x0AA4
16482 STRUCT opa_scale_r OPA_SCALE; // 0x0AA8
16483 STRUCT opa_scale_shift_r OPA_SCALE_SHIFT; // 0x0AAC
16484 STRUCT opb_scale_r OPB_SCALE; // 0x0AB0
16485 uint32_t unused27[3];
16486 STRUCT dma0_src_r DMA0_SRC; // 0x0AC0
16487 STRUCT dma0_dst_r DMA0_DST; // 0x0AC8
16488 STRUCT dma0_len_r DMA0_LEN; // 0x0AD0
16491 uint32_t unused28[6];
16492 STRUCT ifm2_base0_r IFM2_BASE0; // 0x0B00
16493 STRUCT ifm2_base1_r IFM2_BASE1; // 0x0B08
16494 STRUCT ifm2_base2_r IFM2_BASE2; // 0x0B10
16495 STRUCT ifm2_base3_r IFM2_BASE3; // 0x0B18
16496 STRUCT ifm2_stride_x_r IFM2_STRIDE_X; // 0x0B20
16497 STRUCT ifm2_stride_y_r IFM2_STRIDE_Y; // 0x0B28
16498 STRUCT ifm2_stride_c_r IFM2_STRIDE_C; // 0x0B30
16499 uint32_t unused29[2];
16504 uint32_t unused30[280];
16505 STRUCT revision_r REVISION; // 0x0FC0
16506 uint32_t unused31[3];
16507 STRUCT pid4_r PID4; // 0x0FD0
16508 STRUCT pid5_r PID5; // 0x0FD4
16509 STRUCT pid6_r PID6; // 0x0FD8
16510 STRUCT pid7_r PID7; // 0x0FDC
16511 STRUCT pid0_r PID0; // 0x0FE0
16512 STRUCT pid1_r PID1; // 0x0FE4
16513 STRUCT pid2_r PID2; // 0x0FE8
16514 STRUCT pid3_r PID3; // 0x0FEC
16515 STRUCT cid0_r CID0; // 0x0FF0
16516 STRUCT cid1_r CID1; // 0x0FF4
16517 STRUCT cid2_r CID2; // 0x0FF8
16518 STRUCT cid3_r CID3; // 0x0FFC
16519
16520#ifdef __cplusplus
16521 enum class access_type_t : uint8_t
16522 {
16523 RW,
16524 RO,
16525 WO
16526 };
16527 NPU_REG()
16528 {
16529 reset();
16530 }
16531 void reset()
16532 {
16533 ID = 268853249;
16534 STATUS = 8;
16535 CMD = 12;
16536 RESET = 0;
16537 QBASE = 0;
16538 QREAD = 0;
16539 QCONFIG = 0;
16540 QSIZE = 0;
16541 PROT = 0;
16542 CONFIG = 268435456;
16543 LOCK = 0;
16544 REGIONCFG = 0;
16545 AXI_LIMIT0 = 0;
16546 AXI_LIMIT1 = 0;
16547 AXI_LIMIT2 = 0;
16548 AXI_LIMIT3 = 0;
16549 for (size_t i = 0; i < (sizeof(BASEP) / sizeof(BASEP[0])); ++i)
16550 BASEP[i] = 0;
16551 WD_STATUS = 0;
16552 MAC_STATUS = 0;
16553 AO_STATUS = 0;
16554 DMA_STATUS0 = 0;
16555 DMA_STATUS1 = 0;
16556 CLKFORCE = 0;
16557 DEBUG_ADDRESS = 0;
16558 DEBUG_MISC = 0;
16559 DEBUGCORE = 0;
16560 DEBUG_BLOCK = 0;
16561 PMCR = 8192;
16562 PMCNTENSET = 0;
16563 PMCNTENCLR = 0;
16564 PMOVSSET = 0;
16565 PMOVSCLR = 0;
16566 PMINTSET = 0;
16567 PMINTCLR = 0;
16568 PMCCNTR = 0;
16569 PMCCNTR_CFG = 0;
16570 PMCAXI_CHAN = 0;
16571 KERNEL_X = 0;
16572 KERNEL_Y = 0;
16573 KERNEL_W_M1 = 0;
16574 KERNEL_H_M1 = 0;
16575 OFM_CBLK_WIDTH_M1 = 0;
16576 OFM_CBLK_HEIGHT_M1 = 0;
16577 OFM_CBLK_DEPTH_M1 = 0;
16578 IFM_CBLK_DEPTH_M1 = 0;
16579 OFM_X = 0;
16580 OFM_Y = 0;
16581 OFM_Z = 0;
16582 IFM_Z = 0;
16583 PAD_TOP = 0;
16584 PAD_LEFT = 0;
16585 IFM_CBLK_WIDTH = 0;
16586 IFM_CBLK_HEIGHT = 0;
16587 DMA_IFM_SRC = 0;
16588 DMA_IFM_DST = 0;
16589 DMA_OFM_SRC = 0;
16590 DMA_OFM_DST = 0;
16591 DMA_WEIGHT_SRC = 0;
16592 DMA_CMD_SRC = 0;
16593 DMA_CMD_SIZE = 0;
16594 DMA_M2M_SRC = 0;
16595 DMA_M2M_DST = 0;
16596 CURRENT_QREAD = 0;
16597 DMA_SCALE_SRC = 0;
16598 CURRENT_BLOCK = 0;
16599 CURRENT_OP = 0;
16600 CURRENT_CMD = 0;
16601 for (size_t i = 0; i < (sizeof(PMEVCNTR) / sizeof(PMEVCNTR[0])); ++i)
16602 PMEVCNTR[i] = 0;
16603 for (size_t i = 0; i < (sizeof(PMEVTYPER) / sizeof(PMEVTYPER[0])); ++i)
16604 PMEVTYPER[i] = 0;
16605 for (size_t i = 0; i < (sizeof(SHARED_BUFFER) / sizeof(SHARED_BUFFER[0])); ++i)
16606 SHARED_BUFFER[i] = 0;
16607 IFM_PAD_TOP = 0;
16608 IFM_PAD_LEFT = 0;
16609 IFM_PAD_RIGHT = 0;
16610 IFM_PAD_BOTTOM = 0;
16611 IFM_DEPTH_M1 = 0;
16612 IFM_PRECISION = 0;
16613 IFM_UPSCALE = 0;
16614 IFM_ZERO_POINT = 0;
16615 IFM_WIDTH0_M1 = 0;
16616 IFM_HEIGHT0_M1 = 0;
16617 IFM_HEIGHT1_M1 = 0;
16618 IFM_IB_END = 0;
16619 IFM_REGION = 0;
16620 OFM_WIDTH_M1 = 0;
16621 OFM_HEIGHT_M1 = 0;
16622 OFM_DEPTH_M1 = 0;
16623 OFM_PRECISION = 0;
16624 OFM_BLK_WIDTH_M1 = 0;
16625 OFM_BLK_HEIGHT_M1 = 0;
16626 OFM_BLK_DEPTH_M1 = 0;
16627 OFM_ZERO_POINT = 0;
16628 OFM_WIDTH0_M1 = 0;
16629 OFM_HEIGHT0_M1 = 0;
16630 OFM_HEIGHT1_M1 = 0;
16631 OFM_REGION = 0;
16632 KERNEL_WIDTH_M1 = 0;
16633 KERNEL_HEIGHT_M1 = 0;
16634 KERNEL_STRIDE = 0;
16635 PARALLEL_MODE = 0;
16636 ACC_FORMAT = 0;
16637 ACTIVATION = 0;
16638 ACTIVATION_MIN = 0;
16639 ACTIVATION_MAX = 0;
16640 WEIGHT_REGION = 0;
16641 SCALE_REGION = 0;
16642 AB_START = 0;
16643 BLOCKDEP = 0;
16644 DMA0_SRC_REGION = 0;
16645 DMA0_DST_REGION = 0;
16646 DMA0_SIZE0 = 0;
16647 DMA0_SIZE1 = 0;
16648 IFM2_BROADCAST = 0;
16649 IFM2_SCALAR = 0;
16650 IFM2_PRECISION = 0;
16651 IFM2_ZERO_POINT = 0;
16652 IFM2_WIDTH0_M1 = 0;
16653 IFM2_HEIGHT0_M1 = 0;
16654 IFM2_HEIGHT1_M1 = 0;
16655 IFM2_IB_START = 0;
16656 IFM2_REGION = 0;
16657 IFM_BASE0 = 0;
16658 IFM_BASE1 = 0;
16659 IFM_BASE2 = 0;
16660 IFM_BASE3 = 0;
16661 IFM_STRIDE_X = 0;
16662 IFM_STRIDE_Y = 0;
16663 IFM_STRIDE_C = 0;
16664 OFM_BASE0 = 0;
16665 OFM_BASE1 = 0;
16666 OFM_BASE2 = 0;
16667 OFM_BASE3 = 0;
16668 OFM_STRIDE_X = 0;
16669 OFM_STRIDE_Y = 0;
16670 OFM_STRIDE_C = 0;
16671 WEIGHT_BASE = 0;
16672 WEIGHT_LENGTH = 0;
16673 SCALE_BASE = 0;
16674 SCALE_LENGTH = 0;
16675 OFM_SCALE = 0;
16676 OFM_SCALE_SHIFT = 0;
16677 OPA_SCALE = 0;
16678 OPA_SCALE_SHIFT = 0;
16679 OPB_SCALE = 0;
16680 DMA0_SRC = 0;
16681 DMA0_DST = 0;
16682 DMA0_LEN = 0;
16683 DMA0_SKIP0 = 0;
16684 DMA0_SKIP1 = 0;
16685 IFM2_BASE0 = 0;
16686 IFM2_BASE1 = 0;
16687 IFM2_BASE2 = 0;
16688 IFM2_BASE3 = 0;
16689 IFM2_STRIDE_X = 0;
16690 IFM2_STRIDE_Y = 0;
16691 IFM2_STRIDE_C = 0;
16692 WEIGHT1_BASE = 0;
16693 WEIGHT1_LENGTH = 0;
16694 SCALE1_BASE = 0;
16695 SCALE1_LENGTH = 0;
16696 REVISION = 0;
16697 PID4 = 4;
16698 PID5 = 0;
16699 PID6 = 0;
16700 PID7 = 0;
16701 PID0 = 129;
16702 PID1 = 181;
16703 PID2 = 11;
16704 PID3 = 0;
16705 CID0 = 13;
16706 CID1 = 240;
16707 CID2 = 5;
16708 CID3 = 177;
16709 }
16710 uint32_t &operator[](const int addr_offset)
16711 {
16712 return reinterpret_cast<uint32_t *>(this)[addr_offset / 4];
16713 }
16714 access_type_t get_access_type(uint32_t offset)
16715 {
16716 switch (offset)
16717 {
16718 case 0:
16719 return access_type_t::RO;
16720 case 4:
16721 return access_type_t::RO;
16722 case 8:
16723 return access_type_t::RW;
16724 case 12:
16725 return access_type_t::RW;
16726 case 16:
16727 return access_type_t::RW;
16728 case 24:
16729 return access_type_t::RO;
16730 case 28:
16731 return access_type_t::RW;
16732 case 32:
16733 return access_type_t::RW;
16734 case 36:
16735 return access_type_t::RO;
16736 case 40:
16737 return access_type_t::RO;
16738 case 44:
16739 return access_type_t::RW;
16740 case 60:
16741 return access_type_t::RW;
16742 case 64:
16743 return access_type_t::RW;
16744 case 68:
16745 return access_type_t::RW;
16746 case 72:
16747 return access_type_t::RW;
16748 case 76:
16749 return access_type_t::RW;
16750 case 128:
16751 return access_type_t::RW;
16752 case 136:
16753 return access_type_t::RW;
16754 case 144:
16755 return access_type_t::RW;
16756 case 152:
16757 return access_type_t::RW;
16758 case 160:
16759 return access_type_t::RW;
16760 case 168:
16761 return access_type_t::RW;
16762 case 176:
16763 return access_type_t::RW;
16764 case 184:
16765 return access_type_t::RW;
16766 case 256:
16767 return access_type_t::RO;
16768 case 260:
16769 return access_type_t::RO;
16770 case 264:
16771 return access_type_t::RO;
16772 case 272:
16773 return access_type_t::RO;
16774 case 276:
16775 return access_type_t::RO;
16776 case 320:
16777 return access_type_t::RW;
16778 case 324:
16779 return access_type_t::RW;
16780 case 328:
16781 return access_type_t::RW;
16782 case 332:
16783 return access_type_t::RW;
16784 case 336:
16785 return access_type_t::RW;
16786 case 384:
16787 return access_type_t::RW;
16788 case 388:
16789 return access_type_t::RW;
16790 case 392:
16791 return access_type_t::RW;
16792 case 396:
16793 return access_type_t::RW;
16794 case 400:
16795 return access_type_t::RW;
16796 case 404:
16797 return access_type_t::RW;
16798 case 408:
16799 return access_type_t::RW;
16800 case 416:
16801 return access_type_t::RW;
16802 case 424:
16803 return access_type_t::RW;
16804 case 428:
16805 return access_type_t::RW;
16806 case 512:
16807 return access_type_t::RO;
16808 case 516:
16809 return access_type_t::RO;
16810 case 520:
16811 return access_type_t::RO;
16812 case 524:
16813 return access_type_t::RO;
16814 case 528:
16815 return access_type_t::RO;
16816 case 532:
16817 return access_type_t::RO;
16818 case 536:
16819 return access_type_t::RO;
16820 case 540:
16821 return access_type_t::RO;
16822 case 544:
16823 return access_type_t::RO;
16824 case 548:
16825 return access_type_t::RO;
16826 case 552:
16827 return access_type_t::RO;
16828 case 556:
16829 return access_type_t::RO;
16830 case 560:
16831 return access_type_t::RO;
16832 case 564:
16833 return access_type_t::RO;
16834 case 568:
16835 return access_type_t::RO;
16836 case 572:
16837 return access_type_t::RO;
16838 case 576:
16839 return access_type_t::RO;
16840 case 584:
16841 return access_type_t::RO;
16842 case 588:
16843 return access_type_t::RO;
16844 case 592:
16845 return access_type_t::RO;
16846 case 600:
16847 return access_type_t::RO;
16848 case 608:
16849 return access_type_t::RO;
16850 case 616:
16851 return access_type_t::RO;
16852 case 620:
16853 return access_type_t::RO;
16854 case 628:
16855 return access_type_t::RO;
16856 case 636:
16857 return access_type_t::RO;
16858 case 640:
16859 return access_type_t::RO;
16860 case 692:
16861 return access_type_t::RO;
16862 case 696:
16863 return access_type_t::RO;
16864 case 700:
16865 return access_type_t::RO;
16866 case 768:
16867 return access_type_t::RW;
16868 case 772:
16869 return access_type_t::RW;
16870 case 776:
16871 return access_type_t::RW;
16872 case 780:
16873 return access_type_t::RW;
16874 case 896:
16875 return access_type_t::RW;
16876 case 900:
16877 return access_type_t::RW;
16878 case 904:
16879 return access_type_t::RW;
16880 case 908:
16881 return access_type_t::RW;
16882 case 1024:
16883 return access_type_t::RW;
16884 case 1028:
16885 return access_type_t::RW;
16886 case 1032:
16887 return access_type_t::RW;
16888 case 1036:
16889 return access_type_t::RW;
16890 case 1040:
16891 return access_type_t::RW;
16892 case 1044:
16893 return access_type_t::RW;
16894 case 1048:
16895 return access_type_t::RW;
16896 case 1052:
16897 return access_type_t::RW;
16898 case 1056:
16899 return access_type_t::RW;
16900 case 1060:
16901 return access_type_t::RW;
16902 case 1064:
16903 return access_type_t::RW;
16904 case 1068:
16905 return access_type_t::RW;
16906 case 1072:
16907 return access_type_t::RW;
16908 case 1076:
16909 return access_type_t::RW;
16910 case 1080:
16911 return access_type_t::RW;
16912 case 1084:
16913 return access_type_t::RW;
16914 case 1088:
16915 return access_type_t::RW;
16916 case 1092:
16917 return access_type_t::RW;
16918 case 1096:
16919 return access_type_t::RW;
16920 case 1100:
16921 return access_type_t::RW;
16922 case 1104:
16923 return access_type_t::RW;
16924 case 1108:
16925 return access_type_t::RW;
16926 case 1112:
16927 return access_type_t::RW;
16928 case 1116:
16929 return access_type_t::RW;
16930 case 1120:
16931 return access_type_t::RW;
16932 case 1124:
16933 return access_type_t::RW;
16934 case 1128:
16935 return access_type_t::RW;
16936 case 1132:
16937 return access_type_t::RW;
16938 case 1136:
16939 return access_type_t::RW;
16940 case 1140:
16941 return access_type_t::RW;
16942 case 1144:
16943 return access_type_t::RW;
16944 case 1148:
16945 return access_type_t::RW;
16946 case 1152:
16947 return access_type_t::RW;
16948 case 1156:
16949 return access_type_t::RW;
16950 case 1160:
16951 return access_type_t::RW;
16952 case 1164:
16953 return access_type_t::RW;
16954 case 1168:
16955 return access_type_t::RW;
16956 case 1172:
16957 return access_type_t::RW;
16958 case 1176:
16959 return access_type_t::RW;
16960 case 1180:
16961 return access_type_t::RW;
16962 case 1184:
16963 return access_type_t::RW;
16964 case 1188:
16965 return access_type_t::RW;
16966 case 1192:
16967 return access_type_t::RW;
16968 case 1196:
16969 return access_type_t::RW;
16970 case 1200:
16971 return access_type_t::RW;
16972 case 1204:
16973 return access_type_t::RW;
16974 case 1208:
16975 return access_type_t::RW;
16976 case 1212:
16977 return access_type_t::RW;
16978 case 1216:
16979 return access_type_t::RW;
16980 case 1220:
16981 return access_type_t::RW;
16982 case 1224:
16983 return access_type_t::RW;
16984 case 1228:
16985 return access_type_t::RW;
16986 case 1232:
16987 return access_type_t::RW;
16988 case 1236:
16989 return access_type_t::RW;
16990 case 1240:
16991 return access_type_t::RW;
16992 case 1244:
16993 return access_type_t::RW;
16994 case 1248:
16995 return access_type_t::RW;
16996 case 1252:
16997 return access_type_t::RW;
16998 case 1256:
16999 return access_type_t::RW;
17000 case 1260:
17001 return access_type_t::RW;
17002 case 1264:
17003 return access_type_t::RW;
17004 case 1268:
17005 return access_type_t::RW;
17006 case 1272:
17007 return access_type_t::RW;
17008 case 1276:
17009 return access_type_t::RW;
17010 case 1280:
17011 return access_type_t::RW;
17012 case 1284:
17013 return access_type_t::RW;
17014 case 1288:
17015 return access_type_t::RW;
17016 case 1292:
17017 return access_type_t::RW;
17018 case 1296:
17019 return access_type_t::RW;
17020 case 1300:
17021 return access_type_t::RW;
17022 case 1304:
17023 return access_type_t::RW;
17024 case 1308:
17025 return access_type_t::RW;
17026 case 1312:
17027 return access_type_t::RW;
17028 case 1316:
17029 return access_type_t::RW;
17030 case 1320:
17031 return access_type_t::RW;
17032 case 1324:
17033 return access_type_t::RW;
17034 case 1328:
17035 return access_type_t::RW;
17036 case 1332:
17037 return access_type_t::RW;
17038 case 1336:
17039 return access_type_t::RW;
17040 case 1340:
17041 return access_type_t::RW;
17042 case 1344:
17043 return access_type_t::RW;
17044 case 1348:
17045 return access_type_t::RW;
17046 case 1352:
17047 return access_type_t::RW;
17048 case 1356:
17049 return access_type_t::RW;
17050 case 1360:
17051 return access_type_t::RW;
17052 case 1364:
17053 return access_type_t::RW;
17054 case 1368:
17055 return access_type_t::RW;
17056 case 1372:
17057 return access_type_t::RW;
17058 case 1376:
17059 return access_type_t::RW;
17060 case 1380:
17061 return access_type_t::RW;
17062 case 1384:
17063 return access_type_t::RW;
17064 case 1388:
17065 return access_type_t::RW;
17066 case 1392:
17067 return access_type_t::RW;
17068 case 1396:
17069 return access_type_t::RW;
17070 case 1400:
17071 return access_type_t::RW;
17072 case 1404:
17073 return access_type_t::RW;
17074 case 1408:
17075 return access_type_t::RW;
17076 case 1412:
17077 return access_type_t::RW;
17078 case 1416:
17079 return access_type_t::RW;
17080 case 1420:
17081 return access_type_t::RW;
17082 case 1424:
17083 return access_type_t::RW;
17084 case 1428:
17085 return access_type_t::RW;
17086 case 1432:
17087 return access_type_t::RW;
17088 case 1436:
17089 return access_type_t::RW;
17090 case 1440:
17091 return access_type_t::RW;
17092 case 1444:
17093 return access_type_t::RW;
17094 case 1448:
17095 return access_type_t::RW;
17096 case 1452:
17097 return access_type_t::RW;
17098 case 1456:
17099 return access_type_t::RW;
17100 case 1460:
17101 return access_type_t::RW;
17102 case 1464:
17103 return access_type_t::RW;
17104 case 1468:
17105 return access_type_t::RW;
17106 case 1472:
17107 return access_type_t::RW;
17108 case 1476:
17109 return access_type_t::RW;
17110 case 1480:
17111 return access_type_t::RW;
17112 case 1484:
17113 return access_type_t::RW;
17114 case 1488:
17115 return access_type_t::RW;
17116 case 1492:
17117 return access_type_t::RW;
17118 case 1496:
17119 return access_type_t::RW;
17120 case 1500:
17121 return access_type_t::RW;
17122 case 1504:
17123 return access_type_t::RW;
17124 case 1508:
17125 return access_type_t::RW;
17126 case 1512:
17127 return access_type_t::RW;
17128 case 1516:
17129 return access_type_t::RW;
17130 case 1520:
17131 return access_type_t::RW;
17132 case 1524:
17133 return access_type_t::RW;
17134 case 1528:
17135 return access_type_t::RW;
17136 case 1532:
17137 return access_type_t::RW;
17138 case 1536:
17139 return access_type_t::RW;
17140 case 1540:
17141 return access_type_t::RW;
17142 case 1544:
17143 return access_type_t::RW;
17144 case 1548:
17145 return access_type_t::RW;
17146 case 1552:
17147 return access_type_t::RW;
17148 case 1556:
17149 return access_type_t::RW;
17150 case 1560:
17151 return access_type_t::RW;
17152 case 1564:
17153 return access_type_t::RW;
17154 case 1568:
17155 return access_type_t::RW;
17156 case 1572:
17157 return access_type_t::RW;
17158 case 1576:
17159 return access_type_t::RW;
17160 case 1580:
17161 return access_type_t::RW;
17162 case 1584:
17163 return access_type_t::RW;
17164 case 1588:
17165 return access_type_t::RW;
17166 case 1592:
17167 return access_type_t::RW;
17168 case 1596:
17169 return access_type_t::RW;
17170 case 1600:
17171 return access_type_t::RW;
17172 case 1604:
17173 return access_type_t::RW;
17174 case 1608:
17175 return access_type_t::RW;
17176 case 1612:
17177 return access_type_t::RW;
17178 case 1616:
17179 return access_type_t::RW;
17180 case 1620:
17181 return access_type_t::RW;
17182 case 1624:
17183 return access_type_t::RW;
17184 case 1628:
17185 return access_type_t::RW;
17186 case 1632:
17187 return access_type_t::RW;
17188 case 1636:
17189 return access_type_t::RW;
17190 case 1640:
17191 return access_type_t::RW;
17192 case 1644:
17193 return access_type_t::RW;
17194 case 1648:
17195 return access_type_t::RW;
17196 case 1652:
17197 return access_type_t::RW;
17198 case 1656:
17199 return access_type_t::RW;
17200 case 1660:
17201 return access_type_t::RW;
17202 case 1664:
17203 return access_type_t::RW;
17204 case 1668:
17205 return access_type_t::RW;
17206 case 1672:
17207 return access_type_t::RW;
17208 case 1676:
17209 return access_type_t::RW;
17210 case 1680:
17211 return access_type_t::RW;
17212 case 1684:
17213 return access_type_t::RW;
17214 case 1688:
17215 return access_type_t::RW;
17216 case 1692:
17217 return access_type_t::RW;
17218 case 1696:
17219 return access_type_t::RW;
17220 case 1700:
17221 return access_type_t::RW;
17222 case 1704:
17223 return access_type_t::RW;
17224 case 1708:
17225 return access_type_t::RW;
17226 case 1712:
17227 return access_type_t::RW;
17228 case 1716:
17229 return access_type_t::RW;
17230 case 1720:
17231 return access_type_t::RW;
17232 case 1724:
17233 return access_type_t::RW;
17234 case 1728:
17235 return access_type_t::RW;
17236 case 1732:
17237 return access_type_t::RW;
17238 case 1736:
17239 return access_type_t::RW;
17240 case 1740:
17241 return access_type_t::RW;
17242 case 1744:
17243 return access_type_t::RW;
17244 case 1748:
17245 return access_type_t::RW;
17246 case 1752:
17247 return access_type_t::RW;
17248 case 1756:
17249 return access_type_t::RW;
17250 case 1760:
17251 return access_type_t::RW;
17252 case 1764:
17253 return access_type_t::RW;
17254 case 1768:
17255 return access_type_t::RW;
17256 case 1772:
17257 return access_type_t::RW;
17258 case 1776:
17259 return access_type_t::RW;
17260 case 1780:
17261 return access_type_t::RW;
17262 case 1784:
17263 return access_type_t::RW;
17264 case 1788:
17265 return access_type_t::RW;
17266 case 1792:
17267 return access_type_t::RW;
17268 case 1796:
17269 return access_type_t::RW;
17270 case 1800:
17271 return access_type_t::RW;
17272 case 1804:
17273 return access_type_t::RW;
17274 case 1808:
17275 return access_type_t::RW;
17276 case 1812:
17277 return access_type_t::RW;
17278 case 1816:
17279 return access_type_t::RW;
17280 case 1820:
17281 return access_type_t::RW;
17282 case 1824:
17283 return access_type_t::RW;
17284 case 1828:
17285 return access_type_t::RW;
17286 case 1832:
17287 return access_type_t::RW;
17288 case 1836:
17289 return access_type_t::RW;
17290 case 1840:
17291 return access_type_t::RW;
17292 case 1844:
17293 return access_type_t::RW;
17294 case 1848:
17295 return access_type_t::RW;
17296 case 1852:
17297 return access_type_t::RW;
17298 case 1856:
17299 return access_type_t::RW;
17300 case 1860:
17301 return access_type_t::RW;
17302 case 1864:
17303 return access_type_t::RW;
17304 case 1868:
17305 return access_type_t::RW;
17306 case 1872:
17307 return access_type_t::RW;
17308 case 1876:
17309 return access_type_t::RW;
17310 case 1880:
17311 return access_type_t::RW;
17312 case 1884:
17313 return access_type_t::RW;
17314 case 1888:
17315 return access_type_t::RW;
17316 case 1892:
17317 return access_type_t::RW;
17318 case 1896:
17319 return access_type_t::RW;
17320 case 1900:
17321 return access_type_t::RW;
17322 case 1904:
17323 return access_type_t::RW;
17324 case 1908:
17325 return access_type_t::RW;
17326 case 1912:
17327 return access_type_t::RW;
17328 case 1916:
17329 return access_type_t::RW;
17330 case 1920:
17331 return access_type_t::RW;
17332 case 1924:
17333 return access_type_t::RW;
17334 case 1928:
17335 return access_type_t::RW;
17336 case 1932:
17337 return access_type_t::RW;
17338 case 1936:
17339 return access_type_t::RW;
17340 case 1940:
17341 return access_type_t::RW;
17342 case 1944:
17343 return access_type_t::RW;
17344 case 1948:
17345 return access_type_t::RW;
17346 case 1952:
17347 return access_type_t::RW;
17348 case 1956:
17349 return access_type_t::RW;
17350 case 1960:
17351 return access_type_t::RW;
17352 case 1964:
17353 return access_type_t::RW;
17354 case 1968:
17355 return access_type_t::RW;
17356 case 1972:
17357 return access_type_t::RW;
17358 case 1976:
17359 return access_type_t::RW;
17360 case 1980:
17361 return access_type_t::RW;
17362 case 1984:
17363 return access_type_t::RW;
17364 case 1988:
17365 return access_type_t::RW;
17366 case 1992:
17367 return access_type_t::RW;
17368 case 1996:
17369 return access_type_t::RW;
17370 case 2000:
17371 return access_type_t::RW;
17372 case 2004:
17373 return access_type_t::RW;
17374 case 2008:
17375 return access_type_t::RW;
17376 case 2012:
17377 return access_type_t::RW;
17378 case 2016:
17379 return access_type_t::RW;
17380 case 2020:
17381 return access_type_t::RW;
17382 case 2024:
17383 return access_type_t::RW;
17384 case 2028:
17385 return access_type_t::RW;
17386 case 2032:
17387 return access_type_t::RW;
17388 case 2036:
17389 return access_type_t::RW;
17390 case 2040:
17391 return access_type_t::RW;
17392 case 2044:
17393 return access_type_t::RW;
17394 case 2048:
17395 return access_type_t::RW;
17396 case 2052:
17397 return access_type_t::RW;
17398 case 2056:
17399 return access_type_t::RW;
17400 case 2060:
17401 return access_type_t::RW;
17402 case 2064:
17403 return access_type_t::RW;
17404 case 2068:
17405 return access_type_t::RW;
17406 case 2076:
17407 return access_type_t::RW;
17408 case 2084:
17409 return access_type_t::RW;
17410 case 2088:
17411 return access_type_t::RW;
17412 case 2092:
17413 return access_type_t::RW;
17414 case 2096:
17415 return access_type_t::RW;
17416 case 2100:
17417 return access_type_t::RW;
17418 case 2108:
17419 return access_type_t::RW;
17420 case 2116:
17421 return access_type_t::RW;
17422 case 2120:
17423 return access_type_t::RW;
17424 case 2124:
17425 return access_type_t::RW;
17426 case 2128:
17427 return access_type_t::RW;
17428 case 2132:
17429 return access_type_t::RW;
17430 case 2136:
17431 return access_type_t::RW;
17432 case 2140:
17433 return access_type_t::RW;
17434 case 2144:
17435 return access_type_t::RW;
17436 case 2152:
17437 return access_type_t::RW;
17438 case 2156:
17439 return access_type_t::RW;
17440 case 2160:
17441 return access_type_t::RW;
17442 case 2172:
17443 return access_type_t::RW;
17444 case 2176:
17445 return access_type_t::RW;
17446 case 2180:
17447 return access_type_t::RW;
17448 case 2184:
17449 return access_type_t::RW;
17450 case 2188:
17451 return access_type_t::RW;
17452 case 2192:
17453 return access_type_t::RW;
17454 case 2196:
17455 return access_type_t::RW;
17456 case 2200:
17457 return access_type_t::RW;
17458 case 2204:
17459 return access_type_t::RW;
17460 case 2208:
17461 return access_type_t::RW;
17462 case 2212:
17463 return access_type_t::RW;
17464 case 2228:
17465 return access_type_t::RW;
17466 case 2236:
17467 return access_type_t::RW;
17468 case 2240:
17469 return access_type_t::RW;
17470 case 2244:
17471 return access_type_t::RW;
17472 case 2248:
17473 return access_type_t::RW;
17474 case 2252:
17475 return access_type_t::RW;
17476 case 2304:
17477 return access_type_t::RW;
17478 case 2308:
17479 return access_type_t::RW;
17480 case 2324:
17481 return access_type_t::RW;
17482 case 2340:
17483 return access_type_t::RW;
17484 case 2344:
17485 return access_type_t::RW;
17486 case 2348:
17487 return access_type_t::RW;
17488 case 2352:
17489 return access_type_t::RW;
17490 case 2356:
17491 return access_type_t::RW;
17492 case 2364:
17493 return access_type_t::RW;
17494 case 2560:
17495 return access_type_t::RW;
17496 case 2568:
17497 return access_type_t::RW;
17498 case 2576:
17499 return access_type_t::RW;
17500 case 2584:
17501 return access_type_t::RW;
17502 case 2592:
17503 return access_type_t::RW;
17504 case 2600:
17505 return access_type_t::RW;
17506 case 2608:
17507 return access_type_t::RW;
17508 case 2624:
17509 return access_type_t::RW;
17510 case 2632:
17511 return access_type_t::RW;
17512 case 2640:
17513 return access_type_t::RW;
17514 case 2648:
17515 return access_type_t::RW;
17516 case 2656:
17517 return access_type_t::RW;
17518 case 2664:
17519 return access_type_t::RW;
17520 case 2672:
17521 return access_type_t::RW;
17522 case 2688:
17523 return access_type_t::RW;
17524 case 2696:
17525 return access_type_t::RW;
17526 case 2704:
17527 return access_type_t::RW;
17528 case 2712:
17529 return access_type_t::RW;
17530 case 2720:
17531 return access_type_t::RW;
17532 case 2724:
17533 return access_type_t::RW;
17534 case 2728:
17535 return access_type_t::RW;
17536 case 2732:
17537 return access_type_t::RW;
17538 case 2736:
17539 return access_type_t::RW;
17540 case 2752:
17541 return access_type_t::RW;
17542 case 2760:
17543 return access_type_t::RW;
17544 case 2768:
17545 return access_type_t::RW;
17546 case 2776:
17547 return access_type_t::RW;
17548 case 2784:
17549 return access_type_t::RW;
17550 case 2816:
17551 return access_type_t::RW;
17552 case 2824:
17553 return access_type_t::RW;
17554 case 2832:
17555 return access_type_t::RW;
17556 case 2840:
17557 return access_type_t::RW;
17558 case 2848:
17559 return access_type_t::RW;
17560 case 2856:
17561 return access_type_t::RW;
17562 case 2864:
17563 return access_type_t::RW;
17564 case 2880:
17565 return access_type_t::RW;
17566 case 2888:
17567 return access_type_t::RW;
17568 case 2896:
17569 return access_type_t::RW;
17570 case 2904:
17571 return access_type_t::RW;
17572 case 4032:
17573 return access_type_t::RO;
17574 case 4048:
17575 return access_type_t::RO;
17576 case 4052:
17577 return access_type_t::RO;
17578 case 4056:
17579 return access_type_t::RO;
17580 case 4060:
17581 return access_type_t::RO;
17582 case 4064:
17583 return access_type_t::RO;
17584 case 4068:
17585 return access_type_t::RO;
17586 case 4072:
17587 return access_type_t::RO;
17588 case 4076:
17589 return access_type_t::RO;
17590 case 4080:
17591 return access_type_t::RO;
17592 case 4084:
17593 return access_type_t::RO;
17594 case 4088:
17595 return access_type_t::RO;
17596 case 4092:
17597 return access_type_t::RO;
17598 default:
17599 return access_type_t::RO;
17600 }
17601 }
17602#endif
17603};
17604
17605#ifdef __cplusplus
17606struct isa
17607{
17608#ifdef NPU_DISASSEMBLE
17609 static int disassemble(const uint32_t *in,
17610 std::string &op,
17611 std::vector<std::pair<std::string, std::string>> &fields)
17612 {
17613 switch (*in & 0xffff)
17614 {
17615 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17616 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP):
17617 {
17618 const npu_op_stop_t &v = *reinterpret_cast<const npu_op_stop_t *>(in);
17619 op = "NPU_OP_STOP";
17620 v.disassemble(fields);
17621 break;
17622 }
17623 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17624 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ):
17625 {
17626 const npu_op_irq_t &v = *reinterpret_cast<const npu_op_irq_t *>(in);
17627 op = "NPU_OP_IRQ";
17628 v.disassemble(fields);
17629 break;
17630 }
17631 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17632 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV):
17633 {
17634 const npu_op_conv_t &v = *reinterpret_cast<const npu_op_conv_t *>(in);
17635 op = "NPU_OP_CONV";
17636 v.disassemble(fields);
17637 break;
17638 }
17639 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17640 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE):
17641 {
17642 const npu_op_depthwise_t &v = *reinterpret_cast<const npu_op_depthwise_t *>(in);
17643 op = "NPU_OP_DEPTHWISE";
17644 v.disassemble(fields);
17645 break;
17646 }
17647 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17648 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL):
17649 {
17650 const npu_op_pool_t &v = *reinterpret_cast<const npu_op_pool_t *>(in);
17651 op = "NPU_OP_POOL";
17652 v.disassemble(fields);
17653 break;
17654 }
17655 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17656 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE):
17657 {
17658 const npu_op_elementwise_t &v = *reinterpret_cast<const npu_op_elementwise_t *>(in);
17659 op = "NPU_OP_ELEMENTWISE";
17660 v.disassemble(fields);
17661 break;
17662 }
17663 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17664 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START):
17665 {
17666 const npu_op_dma_start_t &v = *reinterpret_cast<const npu_op_dma_start_t *>(in);
17667 op = "NPU_OP_DMA_START";
17668 v.disassemble(fields);
17669 break;
17670 }
17671 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17672 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT):
17673 {
17674 const npu_op_dma_wait_t &v = *reinterpret_cast<const npu_op_dma_wait_t *>(in);
17675 op = "NPU_OP_DMA_WAIT";
17676 v.disassemble(fields);
17677 break;
17678 }
17679 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17680 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT):
17681 {
17682 const npu_op_kernel_wait_t &v = *reinterpret_cast<const npu_op_kernel_wait_t *>(in);
17683 op = "NPU_OP_KERNEL_WAIT";
17684 v.disassemble(fields);
17685 break;
17686 }
17687 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17688 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK):
17689 {
17690 const npu_op_pmu_mask_t &v = *reinterpret_cast<const npu_op_pmu_mask_t *>(in);
17691 op = "NPU_OP_PMU_MASK";
17692 v.disassemble(fields);
17693 break;
17694 }
17695 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17696 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP):
17697 {
17698 const npu_set_ifm_pad_top_t &v = *reinterpret_cast<const npu_set_ifm_pad_top_t *>(in);
17699 op = "NPU_SET_IFM_PAD_TOP";
17700 v.disassemble(fields);
17701 break;
17702 }
17703 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17704 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT):
17705 {
17706 const npu_set_ifm_pad_left_t &v = *reinterpret_cast<const npu_set_ifm_pad_left_t *>(in);
17707 op = "NPU_SET_IFM_PAD_LEFT";
17708 v.disassemble(fields);
17709 break;
17710 }
17711 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17712 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT):
17713 {
17714 const npu_set_ifm_pad_right_t &v = *reinterpret_cast<const npu_set_ifm_pad_right_t *>(in);
17715 op = "NPU_SET_IFM_PAD_RIGHT";
17716 v.disassemble(fields);
17717 break;
17718 }
17719 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17720 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM):
17721 {
17722 const npu_set_ifm_pad_bottom_t &v = *reinterpret_cast<const npu_set_ifm_pad_bottom_t *>(in);
17723 op = "NPU_SET_IFM_PAD_BOTTOM";
17724 v.disassemble(fields);
17725 break;
17726 }
17727 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17728 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1):
17729 {
17730 const npu_set_ifm_depth_m1_t &v = *reinterpret_cast<const npu_set_ifm_depth_m1_t *>(in);
17731 op = "NPU_SET_IFM_DEPTH_M1";
17732 v.disassemble(fields);
17733 break;
17734 }
17735 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17736 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION):
17737 {
17738 const npu_set_ifm_precision_t &v = *reinterpret_cast<const npu_set_ifm_precision_t *>(in);
17739 op = "NPU_SET_IFM_PRECISION";
17740 v.disassemble(fields);
17741 break;
17742 }
17743 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17744 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE):
17745 {
17746 const npu_set_ifm_upscale_t &v = *reinterpret_cast<const npu_set_ifm_upscale_t *>(in);
17747 op = "NPU_SET_IFM_UPSCALE";
17748 v.disassemble(fields);
17749 break;
17750 }
17751 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17752 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT):
17753 {
17754 const npu_set_ifm_zero_point_t &v = *reinterpret_cast<const npu_set_ifm_zero_point_t *>(in);
17755 op = "NPU_SET_IFM_ZERO_POINT";
17756 v.disassemble(fields);
17757 break;
17758 }
17759 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17760 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1):
17761 {
17762 const npu_set_ifm_width0_m1_t &v = *reinterpret_cast<const npu_set_ifm_width0_m1_t *>(in);
17763 op = "NPU_SET_IFM_WIDTH0_M1";
17764 v.disassemble(fields);
17765 break;
17766 }
17767 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17768 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1):
17769 {
17770 const npu_set_ifm_height0_m1_t &v = *reinterpret_cast<const npu_set_ifm_height0_m1_t *>(in);
17771 op = "NPU_SET_IFM_HEIGHT0_M1";
17772 v.disassemble(fields);
17773 break;
17774 }
17775 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17776 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1):
17777 {
17778 const npu_set_ifm_height1_m1_t &v = *reinterpret_cast<const npu_set_ifm_height1_m1_t *>(in);
17779 op = "NPU_SET_IFM_HEIGHT1_M1";
17780 v.disassemble(fields);
17781 break;
17782 }
17783 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17784 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END):
17785 {
17786 const npu_set_ifm_ib_end_t &v = *reinterpret_cast<const npu_set_ifm_ib_end_t *>(in);
17787 op = "NPU_SET_IFM_IB_END";
17788 v.disassemble(fields);
17789 break;
17790 }
17791 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17792 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION):
17793 {
17794 const npu_set_ifm_region_t &v = *reinterpret_cast<const npu_set_ifm_region_t *>(in);
17795 op = "NPU_SET_IFM_REGION";
17796 v.disassemble(fields);
17797 break;
17798 }
17799 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17800 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1):
17801 {
17802 const npu_set_ofm_width_m1_t &v = *reinterpret_cast<const npu_set_ofm_width_m1_t *>(in);
17803 op = "NPU_SET_OFM_WIDTH_M1";
17804 v.disassemble(fields);
17805 break;
17806 }
17807 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17808 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1):
17809 {
17810 const npu_set_ofm_height_m1_t &v = *reinterpret_cast<const npu_set_ofm_height_m1_t *>(in);
17811 op = "NPU_SET_OFM_HEIGHT_M1";
17812 v.disassemble(fields);
17813 break;
17814 }
17815 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17816 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1):
17817 {
17818 const npu_set_ofm_depth_m1_t &v = *reinterpret_cast<const npu_set_ofm_depth_m1_t *>(in);
17819 op = "NPU_SET_OFM_DEPTH_M1";
17820 v.disassemble(fields);
17821 break;
17822 }
17823 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17824 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION):
17825 {
17826 const npu_set_ofm_precision_t &v = *reinterpret_cast<const npu_set_ofm_precision_t *>(in);
17827 op = "NPU_SET_OFM_PRECISION";
17828 v.disassemble(fields);
17829 break;
17830 }
17831 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17832 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1):
17833 {
17834 const npu_set_ofm_blk_width_m1_t &v = *reinterpret_cast<const npu_set_ofm_blk_width_m1_t *>(in);
17835 op = "NPU_SET_OFM_BLK_WIDTH_M1";
17836 v.disassemble(fields);
17837 break;
17838 }
17839 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17840 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1):
17841 {
17842 const npu_set_ofm_blk_height_m1_t &v = *reinterpret_cast<const npu_set_ofm_blk_height_m1_t *>(in);
17843 op = "NPU_SET_OFM_BLK_HEIGHT_M1";
17844 v.disassemble(fields);
17845 break;
17846 }
17847 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17848 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1):
17849 {
17850 const npu_set_ofm_blk_depth_m1_t &v = *reinterpret_cast<const npu_set_ofm_blk_depth_m1_t *>(in);
17851 op = "NPU_SET_OFM_BLK_DEPTH_M1";
17852 v.disassemble(fields);
17853 break;
17854 }
17855 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17856 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT):
17857 {
17858 const npu_set_ofm_zero_point_t &v = *reinterpret_cast<const npu_set_ofm_zero_point_t *>(in);
17859 op = "NPU_SET_OFM_ZERO_POINT";
17860 v.disassemble(fields);
17861 break;
17862 }
17863 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17864 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1):
17865 {
17866 const npu_set_ofm_width0_m1_t &v = *reinterpret_cast<const npu_set_ofm_width0_m1_t *>(in);
17867 op = "NPU_SET_OFM_WIDTH0_M1";
17868 v.disassemble(fields);
17869 break;
17870 }
17871 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17872 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1):
17873 {
17874 const npu_set_ofm_height0_m1_t &v = *reinterpret_cast<const npu_set_ofm_height0_m1_t *>(in);
17875 op = "NPU_SET_OFM_HEIGHT0_M1";
17876 v.disassemble(fields);
17877 break;
17878 }
17879 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17880 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1):
17881 {
17882 const npu_set_ofm_height1_m1_t &v = *reinterpret_cast<const npu_set_ofm_height1_m1_t *>(in);
17883 op = "NPU_SET_OFM_HEIGHT1_M1";
17884 v.disassemble(fields);
17885 break;
17886 }
17887 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17888 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION):
17889 {
17890 const npu_set_ofm_region_t &v = *reinterpret_cast<const npu_set_ofm_region_t *>(in);
17891 op = "NPU_SET_OFM_REGION";
17892 v.disassemble(fields);
17893 break;
17894 }
17895 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17896 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1):
17897 {
17898 const npu_set_kernel_width_m1_t &v = *reinterpret_cast<const npu_set_kernel_width_m1_t *>(in);
17899 op = "NPU_SET_KERNEL_WIDTH_M1";
17900 v.disassemble(fields);
17901 break;
17902 }
17903 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17904 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1):
17905 {
17906 const npu_set_kernel_height_m1_t &v = *reinterpret_cast<const npu_set_kernel_height_m1_t *>(in);
17907 op = "NPU_SET_KERNEL_HEIGHT_M1";
17908 v.disassemble(fields);
17909 break;
17910 }
17911 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17912 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE):
17913 {
17914 const npu_set_kernel_stride_t &v = *reinterpret_cast<const npu_set_kernel_stride_t *>(in);
17915 op = "NPU_SET_KERNEL_STRIDE";
17916 v.disassemble(fields);
17917 break;
17918 }
17919 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17920 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE):
17921 {
17922 const npu_set_parallel_mode_t &v = *reinterpret_cast<const npu_set_parallel_mode_t *>(in);
17923 op = "NPU_SET_PARALLEL_MODE";
17924 v.disassemble(fields);
17925 break;
17926 }
17927 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17928 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT):
17929 {
17930 const npu_set_acc_format_t &v = *reinterpret_cast<const npu_set_acc_format_t *>(in);
17931 op = "NPU_SET_ACC_FORMAT";
17932 v.disassemble(fields);
17933 break;
17934 }
17935 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17936 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION):
17937 {
17938 const npu_set_activation_t &v = *reinterpret_cast<const npu_set_activation_t *>(in);
17939 op = "NPU_SET_ACTIVATION";
17940 v.disassemble(fields);
17941 break;
17942 }
17943 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17944 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN):
17945 {
17946 const npu_set_activation_min_t &v = *reinterpret_cast<const npu_set_activation_min_t *>(in);
17947 op = "NPU_SET_ACTIVATION_MIN";
17948 v.disassemble(fields);
17949 break;
17950 }
17951 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17952 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX):
17953 {
17954 const npu_set_activation_max_t &v = *reinterpret_cast<const npu_set_activation_max_t *>(in);
17955 op = "NPU_SET_ACTIVATION_MAX";
17956 v.disassemble(fields);
17957 break;
17958 }
17959 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17960 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION):
17961 {
17962 const npu_set_weight_region_t &v = *reinterpret_cast<const npu_set_weight_region_t *>(in);
17963 op = "NPU_SET_WEIGHT_REGION";
17964 v.disassemble(fields);
17965 break;
17966 }
17967 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17968 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION):
17969 {
17970 const npu_set_scale_region_t &v = *reinterpret_cast<const npu_set_scale_region_t *>(in);
17971 op = "NPU_SET_SCALE_REGION";
17972 v.disassemble(fields);
17973 break;
17974 }
17975 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17976 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START):
17977 {
17978 const npu_set_ab_start_t &v = *reinterpret_cast<const npu_set_ab_start_t *>(in);
17979 op = "NPU_SET_AB_START";
17980 v.disassemble(fields);
17981 break;
17982 }
17983 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17984 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP):
17985 {
17986 const npu_set_blockdep_t &v = *reinterpret_cast<const npu_set_blockdep_t *>(in);
17987 op = "NPU_SET_BLOCKDEP";
17988 v.disassemble(fields);
17989 break;
17990 }
17991 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17992 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION):
17993 {
17994 const npu_set_dma0_src_region_t &v = *reinterpret_cast<const npu_set_dma0_src_region_t *>(in);
17995 op = "NPU_SET_DMA0_SRC_REGION";
17996 v.disassemble(fields);
17997 break;
17998 }
17999 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18000 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION):
18001 {
18002 const npu_set_dma0_dst_region_t &v = *reinterpret_cast<const npu_set_dma0_dst_region_t *>(in);
18003 op = "NPU_SET_DMA0_DST_REGION";
18004 v.disassemble(fields);
18005 break;
18006 }
18007 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18008 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0):
18009 {
18010 const npu_set_dma0_size0_t &v = *reinterpret_cast<const npu_set_dma0_size0_t *>(in);
18011 op = "NPU_SET_DMA0_SIZE0";
18012 v.disassemble(fields);
18013 break;
18014 }
18015 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18016 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1):
18017 {
18018 const npu_set_dma0_size1_t &v = *reinterpret_cast<const npu_set_dma0_size1_t *>(in);
18019 op = "NPU_SET_DMA0_SIZE1";
18020 v.disassemble(fields);
18021 break;
18022 }
18023 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18024 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST):
18025 {
18026 const npu_set_ifm2_broadcast_t &v = *reinterpret_cast<const npu_set_ifm2_broadcast_t *>(in);
18027 op = "NPU_SET_IFM2_BROADCAST";
18028 v.disassemble(fields);
18029 break;
18030 }
18031 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18032 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR):
18033 {
18034 const npu_set_ifm2_scalar_t &v = *reinterpret_cast<const npu_set_ifm2_scalar_t *>(in);
18035 op = "NPU_SET_IFM2_SCALAR";
18036 v.disassemble(fields);
18037 break;
18038 }
18039 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18040 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION):
18041 {
18042 const npu_set_ifm2_precision_t &v = *reinterpret_cast<const npu_set_ifm2_precision_t *>(in);
18043 op = "NPU_SET_IFM2_PRECISION";
18044 v.disassemble(fields);
18045 break;
18046 }
18047 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18048 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT):
18049 {
18050 const npu_set_ifm2_zero_point_t &v = *reinterpret_cast<const npu_set_ifm2_zero_point_t *>(in);
18051 op = "NPU_SET_IFM2_ZERO_POINT";
18052 v.disassemble(fields);
18053 break;
18054 }
18055 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18056 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1):
18057 {
18058 const npu_set_ifm2_width0_m1_t &v = *reinterpret_cast<const npu_set_ifm2_width0_m1_t *>(in);
18059 op = "NPU_SET_IFM2_WIDTH0_M1";
18060 v.disassemble(fields);
18061 break;
18062 }
18063 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18064 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1):
18065 {
18066 const npu_set_ifm2_height0_m1_t &v = *reinterpret_cast<const npu_set_ifm2_height0_m1_t *>(in);
18067 op = "NPU_SET_IFM2_HEIGHT0_M1";
18068 v.disassemble(fields);
18069 break;
18070 }
18071 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18072 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1):
18073 {
18074 const npu_set_ifm2_height1_m1_t &v = *reinterpret_cast<const npu_set_ifm2_height1_m1_t *>(in);
18075 op = "NPU_SET_IFM2_HEIGHT1_M1";
18076 v.disassemble(fields);
18077 break;
18078 }
18079 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18080 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START):
18081 {
18082 const npu_set_ifm2_ib_start_t &v = *reinterpret_cast<const npu_set_ifm2_ib_start_t *>(in);
18083 op = "NPU_SET_IFM2_IB_START";
18084 v.disassemble(fields);
18085 break;
18086 }
18087 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18088 static_cast<uint32_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION):
18089 {
18090 const npu_set_ifm2_region_t &v = *reinterpret_cast<const npu_set_ifm2_region_t *>(in);
18091 op = "NPU_SET_IFM2_REGION";
18092 v.disassemble(fields);
18093 break;
18094 }
18095 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18096 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0):
18097 {
18098 const npu_set_ifm_base0_t &v = *reinterpret_cast<const npu_set_ifm_base0_t *>(in);
18099 op = "NPU_SET_IFM_BASE0";
18100 v.disassemble(fields);
18101 break;
18102 }
18103 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18104 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1):
18105 {
18106 const npu_set_ifm_base1_t &v = *reinterpret_cast<const npu_set_ifm_base1_t *>(in);
18107 op = "NPU_SET_IFM_BASE1";
18108 v.disassemble(fields);
18109 break;
18110 }
18111 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18112 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2):
18113 {
18114 const npu_set_ifm_base2_t &v = *reinterpret_cast<const npu_set_ifm_base2_t *>(in);
18115 op = "NPU_SET_IFM_BASE2";
18116 v.disassemble(fields);
18117 break;
18118 }
18119 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18120 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3):
18121 {
18122 const npu_set_ifm_base3_t &v = *reinterpret_cast<const npu_set_ifm_base3_t *>(in);
18123 op = "NPU_SET_IFM_BASE3";
18124 v.disassemble(fields);
18125 break;
18126 }
18127 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18128 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X):
18129 {
18130 const npu_set_ifm_stride_x_t &v = *reinterpret_cast<const npu_set_ifm_stride_x_t *>(in);
18131 op = "NPU_SET_IFM_STRIDE_X";
18132 v.disassemble(fields);
18133 break;
18134 }
18135 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18136 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y):
18137 {
18138 const npu_set_ifm_stride_y_t &v = *reinterpret_cast<const npu_set_ifm_stride_y_t *>(in);
18139 op = "NPU_SET_IFM_STRIDE_Y";
18140 v.disassemble(fields);
18141 break;
18142 }
18143 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18144 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C):
18145 {
18146 const npu_set_ifm_stride_c_t &v = *reinterpret_cast<const npu_set_ifm_stride_c_t *>(in);
18147 op = "NPU_SET_IFM_STRIDE_C";
18148 v.disassemble(fields);
18149 break;
18150 }
18151 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18152 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0):
18153 {
18154 const npu_set_ofm_base0_t &v = *reinterpret_cast<const npu_set_ofm_base0_t *>(in);
18155 op = "NPU_SET_OFM_BASE0";
18156 v.disassemble(fields);
18157 break;
18158 }
18159 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18160 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1):
18161 {
18162 const npu_set_ofm_base1_t &v = *reinterpret_cast<const npu_set_ofm_base1_t *>(in);
18163 op = "NPU_SET_OFM_BASE1";
18164 v.disassemble(fields);
18165 break;
18166 }
18167 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18168 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2):
18169 {
18170 const npu_set_ofm_base2_t &v = *reinterpret_cast<const npu_set_ofm_base2_t *>(in);
18171 op = "NPU_SET_OFM_BASE2";
18172 v.disassemble(fields);
18173 break;
18174 }
18175 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18176 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3):
18177 {
18178 const npu_set_ofm_base3_t &v = *reinterpret_cast<const npu_set_ofm_base3_t *>(in);
18179 op = "NPU_SET_OFM_BASE3";
18180 v.disassemble(fields);
18181 break;
18182 }
18183 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18184 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X):
18185 {
18186 const npu_set_ofm_stride_x_t &v = *reinterpret_cast<const npu_set_ofm_stride_x_t *>(in);
18187 op = "NPU_SET_OFM_STRIDE_X";
18188 v.disassemble(fields);
18189 break;
18190 }
18191 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18192 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y):
18193 {
18194 const npu_set_ofm_stride_y_t &v = *reinterpret_cast<const npu_set_ofm_stride_y_t *>(in);
18195 op = "NPU_SET_OFM_STRIDE_Y";
18196 v.disassemble(fields);
18197 break;
18198 }
18199 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18200 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C):
18201 {
18202 const npu_set_ofm_stride_c_t &v = *reinterpret_cast<const npu_set_ofm_stride_c_t *>(in);
18203 op = "NPU_SET_OFM_STRIDE_C";
18204 v.disassemble(fields);
18205 break;
18206 }
18207 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18208 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE):
18209 {
18210 const npu_set_weight_base_t &v = *reinterpret_cast<const npu_set_weight_base_t *>(in);
18211 op = "NPU_SET_WEIGHT_BASE";
18212 v.disassemble(fields);
18213 break;
18214 }
18215 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18216 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH):
18217 {
18218 const npu_set_weight_length_t &v = *reinterpret_cast<const npu_set_weight_length_t *>(in);
18219 op = "NPU_SET_WEIGHT_LENGTH";
18220 v.disassemble(fields);
18221 break;
18222 }
18223 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18224 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE):
18225 {
18226 const npu_set_scale_base_t &v = *reinterpret_cast<const npu_set_scale_base_t *>(in);
18227 op = "NPU_SET_SCALE_BASE";
18228 v.disassemble(fields);
18229 break;
18230 }
18231 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18232 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH):
18233 {
18234 const npu_set_scale_length_t &v = *reinterpret_cast<const npu_set_scale_length_t *>(in);
18235 op = "NPU_SET_SCALE_LENGTH";
18236 v.disassemble(fields);
18237 break;
18238 }
18239 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18240 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE):
18241 {
18242 const npu_set_ofm_scale_t &v = *reinterpret_cast<const npu_set_ofm_scale_t *>(in);
18243 op = "NPU_SET_OFM_SCALE";
18244 v.disassemble(fields);
18245 break;
18246 }
18247 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18248 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE):
18249 {
18250 const npu_set_opa_scale_t &v = *reinterpret_cast<const npu_set_opa_scale_t *>(in);
18251 op = "NPU_SET_OPA_SCALE";
18252 v.disassemble(fields);
18253 break;
18254 }
18255 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18256 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE):
18257 {
18258 const npu_set_opb_scale_t &v = *reinterpret_cast<const npu_set_opb_scale_t *>(in);
18259 op = "NPU_SET_OPB_SCALE";
18260 v.disassemble(fields);
18261 break;
18262 }
18263 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18264 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC):
18265 {
18266 const npu_set_dma0_src_t &v = *reinterpret_cast<const npu_set_dma0_src_t *>(in);
18267 op = "NPU_SET_DMA0_SRC";
18268 v.disassemble(fields);
18269 break;
18270 }
18271 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18272 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST):
18273 {
18274 const npu_set_dma0_dst_t &v = *reinterpret_cast<const npu_set_dma0_dst_t *>(in);
18275 op = "NPU_SET_DMA0_DST";
18276 v.disassemble(fields);
18277 break;
18278 }
18279 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18280 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN):
18281 {
18282 const npu_set_dma0_len_t &v = *reinterpret_cast<const npu_set_dma0_len_t *>(in);
18283 op = "NPU_SET_DMA0_LEN";
18284 v.disassemble(fields);
18285 break;
18286 }
18287 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18288 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0):
18289 {
18290 const npu_set_dma0_skip0_t &v = *reinterpret_cast<const npu_set_dma0_skip0_t *>(in);
18291 op = "NPU_SET_DMA0_SKIP0";
18292 v.disassemble(fields);
18293 break;
18294 }
18295 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18296 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1):
18297 {
18298 const npu_set_dma0_skip1_t &v = *reinterpret_cast<const npu_set_dma0_skip1_t *>(in);
18299 op = "NPU_SET_DMA0_SKIP1";
18300 v.disassemble(fields);
18301 break;
18302 }
18303 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18304 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0):
18305 {
18306 const npu_set_ifm2_base0_t &v = *reinterpret_cast<const npu_set_ifm2_base0_t *>(in);
18307 op = "NPU_SET_IFM2_BASE0";
18308 v.disassemble(fields);
18309 break;
18310 }
18311 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18312 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1):
18313 {
18314 const npu_set_ifm2_base1_t &v = *reinterpret_cast<const npu_set_ifm2_base1_t *>(in);
18315 op = "NPU_SET_IFM2_BASE1";
18316 v.disassemble(fields);
18317 break;
18318 }
18319 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18320 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2):
18321 {
18322 const npu_set_ifm2_base2_t &v = *reinterpret_cast<const npu_set_ifm2_base2_t *>(in);
18323 op = "NPU_SET_IFM2_BASE2";
18324 v.disassemble(fields);
18325 break;
18326 }
18327 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18328 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3):
18329 {
18330 const npu_set_ifm2_base3_t &v = *reinterpret_cast<const npu_set_ifm2_base3_t *>(in);
18331 op = "NPU_SET_IFM2_BASE3";
18332 v.disassemble(fields);
18333 break;
18334 }
18335 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18336 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X):
18337 {
18338 const npu_set_ifm2_stride_x_t &v = *reinterpret_cast<const npu_set_ifm2_stride_x_t *>(in);
18339 op = "NPU_SET_IFM2_STRIDE_X";
18340 v.disassemble(fields);
18341 break;
18342 }
18343 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18344 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y):
18345 {
18346 const npu_set_ifm2_stride_y_t &v = *reinterpret_cast<const npu_set_ifm2_stride_y_t *>(in);
18347 op = "NPU_SET_IFM2_STRIDE_Y";
18348 v.disassemble(fields);
18349 break;
18350 }
18351 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18352 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C):
18353 {
18354 const npu_set_ifm2_stride_c_t &v = *reinterpret_cast<const npu_set_ifm2_stride_c_t *>(in);
18355 op = "NPU_SET_IFM2_STRIDE_C";
18356 v.disassemble(fields);
18357 break;
18358 }
18359 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18360 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE):
18361 {
18362 const npu_set_weight1_base_t &v = *reinterpret_cast<const npu_set_weight1_base_t *>(in);
18363 op = "NPU_SET_WEIGHT1_BASE";
18364 v.disassemble(fields);
18365 break;
18366 }
18367 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18368 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH):
18369 {
18370 const npu_set_weight1_length_t &v = *reinterpret_cast<const npu_set_weight1_length_t *>(in);
18371 op = "NPU_SET_WEIGHT1_LENGTH";
18372 v.disassemble(fields);
18373 break;
18374 }
18375 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18376 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE):
18377 {
18378 const npu_set_scale1_base_t &v = *reinterpret_cast<const npu_set_scale1_base_t *>(in);
18379 op = "NPU_SET_SCALE1_BASE";
18380 v.disassemble(fields);
18381 break;
18382 }
18383 case (static_cast<uint32_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18384 static_cast<uint32_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH):
18385 {
18386 const npu_set_scale1_length_t &v = *reinterpret_cast<const npu_set_scale1_length_t *>(in);
18387 op = "NPU_SET_SCALE1_LENGTH";
18388 v.disassemble(fields);
18389 break;
18390 }
18391 }
18392 return (*in & (3 << 14)) != 0 ? 2 : 1;
18393 }
18394#endif
18395#endif
18396 // Signal the end of command stream
18397 struct npu_op_stop_t
18398 {
18399#ifdef __cplusplus
18400 private:
18401#endif
18402 uint32_t opcode : 10; // opcode
18403 uint32_t reserved0 : 4;
18404 uint32_t control : 2; // control
18405 uint32_t mask : 16; // Encoding for 16-bit mask value
18406#ifdef __cplusplus
18407 public:
18408 npu_op_stop_t(uint32_t _mask) :
18409 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP)), reserved0(0),
18410 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(_mask & ((1U << 16) - 1))
18411 {
18412 }
18414 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP)), reserved0(0),
18415 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(0)
18416 {
18417 }
18418 CONSTEXPR bool valid() const
18419 {
18420 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP) &&
18421 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18422 }
18423 CONSTEXPR void init()
18424 {
18425 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP);
18426 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18427 }
18428 operator uint32_t()
18429 {
18430 uint32_t word;
18431 std::memcpy(&word, this, sizeof(word));
18432 return word;
18433 }
18434 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18435 {
18436 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18437 }
18438 CONSTEXPR npu_op_stop_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18439 {
18440 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18441 return *this;
18442 }
18443 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18444 {
18445 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18446 }
18447 CONSTEXPR npu_op_stop_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18448 {
18449 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18450 return *this;
18451 }
18452 CONSTEXPR uint32_t get_mask() const
18453 {
18454 return static_cast<uint32_t>(mask);
18455 }
18456 CONSTEXPR npu_op_stop_t &set_mask(uint32_t value)
18457 {
18458 mask = static_cast<uint16_t>(value) & ((1U << 16) - 1);
18459 return *this;
18460 }
18461#ifdef NPU_DISASSEMBLE
18462 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
18463 {
18464 fields.push_back(std::make_pair<std::string, std::string>("mask", std::to_string(mask)));
18465 }
18466#endif
18467#endif
18468 };
18469 // Raises an IRQ to the host
18470 struct npu_op_irq_t
18471 {
18472#ifdef __cplusplus
18473 private:
18474#endif
18475 uint32_t opcode : 10; // opcode
18476 uint32_t reserved0 : 4;
18477 uint32_t control : 2; // control
18478 uint32_t mask : 16; // Encoding for 16-bit mask value
18479#ifdef __cplusplus
18480 public:
18481 npu_op_irq_t(uint32_t _mask) :
18482 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ)), reserved0(0),
18483 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(_mask & ((1U << 16) - 1))
18484 {
18485 }
18487 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ)), reserved0(0),
18488 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mask(0)
18489 {
18490 }
18491 CONSTEXPR bool valid() const
18492 {
18493 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ) &&
18494 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18495 }
18496 CONSTEXPR void init()
18497 {
18498 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ);
18499 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18500 }
18501 operator uint32_t()
18502 {
18503 uint32_t word;
18504 std::memcpy(&word, this, sizeof(word));
18505 return word;
18506 }
18507 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18508 {
18509 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18510 }
18511 CONSTEXPR npu_op_irq_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18512 {
18513 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18514 return *this;
18515 }
18516 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18517 {
18518 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18519 }
18520 CONSTEXPR npu_op_irq_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18521 {
18522 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18523 return *this;
18524 }
18525 CONSTEXPR uint32_t get_mask() const
18526 {
18527 return static_cast<uint32_t>(mask);
18528 }
18529 CONSTEXPR npu_op_irq_t &set_mask(uint32_t value)
18530 {
18531 mask = static_cast<uint16_t>(value) & ((1U << 16) - 1);
18532 return *this;
18533 }
18534#ifdef NPU_DISASSEMBLE
18535 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
18536 {
18537 fields.push_back(std::make_pair<std::string, std::string>("mask", std::to_string(mask)));
18538 }
18539#endif
18540#endif
18541 };
18542 // 2D convolution
18543 struct npu_op_conv_t
18544 {
18545#ifdef __cplusplus
18546 private:
18547#endif
18548 uint32_t opcode : 10; // opcode
18549 uint32_t reserved0 : 4;
18550 uint32_t control : 2; // control
18551 uint32_t reserved1 : 16;
18552#ifdef __cplusplus
18553 public:
18555 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV)), reserved0(0),
18556 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0)
18557 {
18558 }
18559 CONSTEXPR bool valid() const
18560 {
18561 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV) &&
18562 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18563 }
18564 CONSTEXPR void init()
18565 {
18566 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV);
18567 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18568 }
18569 operator uint32_t()
18570 {
18571 uint32_t word;
18572 std::memcpy(&word, this, sizeof(word));
18573 return word;
18574 }
18575 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18576 {
18577 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18578 }
18579 CONSTEXPR npu_op_conv_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18580 {
18581 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18582 return *this;
18583 }
18584 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18585 {
18586 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18587 }
18588 CONSTEXPR npu_op_conv_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18589 {
18590 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18591 return *this;
18592 }
18593#ifdef NPU_DISASSEMBLE
18594 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const {}
18595#endif
18596#endif
18597 };
18598 // Depth-wise 2D convolution
18599 struct npu_op_depthwise_t
18600 {
18601#ifdef __cplusplus
18602 private:
18603#endif
18604 uint32_t opcode : 10; // opcode
18605 uint32_t reserved0 : 4;
18606 uint32_t control : 2; // control
18607 uint32_t reserved1 : 16;
18608#ifdef __cplusplus
18609 public:
18611 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE)), reserved0(0),
18612 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0)
18613 {
18614 }
18615 CONSTEXPR bool valid() const
18616 {
18617 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE) &&
18618 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18619 }
18620 CONSTEXPR void init()
18621 {
18622 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE);
18623 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18624 }
18625 operator uint32_t()
18626 {
18627 uint32_t word;
18628 std::memcpy(&word, this, sizeof(word));
18629 return word;
18630 }
18631 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18632 {
18633 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18634 }
18635 CONSTEXPR npu_op_depthwise_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18636 {
18637 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18638 return *this;
18639 }
18640 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18641 {
18642 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18643 }
18644 CONSTEXPR npu_op_depthwise_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18645 {
18646 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18647 return *this;
18648 }
18649#ifdef NPU_DISASSEMBLE
18650 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const {}
18651#endif
18652#endif
18653 };
18654 // Pooling
18655 struct npu_op_pool_t
18656 {
18657#ifdef __cplusplus
18658 private:
18659#endif
18660 uint32_t opcode : 10; // opcode
18661 uint32_t reserved0 : 4;
18662 uint32_t control : 2; // control
18663 uint32_t pooling_mode : 3; // Pooling mode
18664 uint32_t reserved1 : 13;
18665#ifdef __cplusplus
18666 public:
18667 npu_op_pool_t(NPU_NAMESPACE::pooling_mode _pooling_mode) :
18668 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL)), reserved0(0),
18669 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
18670 pooling_mode(static_cast<uint8_t>(_pooling_mode) & ((1U << 3) - 1)), reserved1(0)
18671 {
18672 }
18674 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL)), reserved0(0),
18675 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pooling_mode(0), reserved1(0)
18676 {
18677 }
18678 CONSTEXPR bool valid() const
18679 {
18680 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL) &&
18681 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18682 }
18683 CONSTEXPR void init()
18684 {
18685 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL);
18686 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18687 }
18688 operator uint32_t()
18689 {
18690 uint32_t word;
18691 std::memcpy(&word, this, sizeof(word));
18692 return word;
18693 }
18694 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18695 {
18696 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18697 }
18698 CONSTEXPR npu_op_pool_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18699 {
18700 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18701 return *this;
18702 }
18703 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18704 {
18705 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18706 }
18707 CONSTEXPR npu_op_pool_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18708 {
18709 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18710 return *this;
18711 }
18712 CONSTEXPR NPU_NAMESPACE::pooling_mode get_pooling_mode() const
18713 {
18714 return static_cast<NPU_NAMESPACE::pooling_mode>(pooling_mode);
18715 }
18716 CONSTEXPR npu_op_pool_t &set_pooling_mode(NPU_NAMESPACE::pooling_mode value)
18717 {
18718 pooling_mode = static_cast<uint8_t>(value) & ((1U << 3) - 1);
18719 return *this;
18720 }
18721#ifdef NPU_DISASSEMBLE
18722 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
18723 {
18724 fields.push_back(std::make_pair<std::string, std::string>(
18725 "pooling_mode",
18726 (pooling_mode < (sizeof(pooling_mode_str) / sizeof(pooling_mode_str[0])) ?
18727 pooling_mode_str[pooling_mode] :
18728 "****")));
18729 }
18730#endif
18731#endif
18732 };
18733 // Elementwise operation
18735 {
18736#ifdef __cplusplus
18737 private:
18738#endif
18739 uint32_t opcode : 10; // opcode
18740 uint32_t reserved0 : 4;
18741 uint32_t control : 2; // control
18742 uint32_t elementwise_mode : 6; // Elementwise mode
18743 uint32_t reserved1 : 10;
18744#ifdef __cplusplus
18745 public:
18746 npu_op_elementwise_t(NPU_NAMESPACE::elementwise_mode _elementwise_mode) :
18747 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE)), reserved0(0),
18748 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
18749 elementwise_mode(static_cast<uint8_t>(_elementwise_mode) & ((1U << 6) - 1)), reserved1(0)
18750 {
18751 }
18753 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE)), reserved0(0),
18754 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), elementwise_mode(0), reserved1(0)
18755 {
18756 }
18757 CONSTEXPR bool valid() const
18758 {
18759 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE) &&
18760 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18761 }
18762 CONSTEXPR void init()
18763 {
18764 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE);
18765 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18766 }
18767 operator uint32_t()
18768 {
18769 uint32_t word;
18770 std::memcpy(&word, this, sizeof(word));
18771 return word;
18772 }
18773 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18774 {
18775 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18776 }
18777 CONSTEXPR npu_op_elementwise_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18778 {
18779 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18780 return *this;
18781 }
18782 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18783 {
18784 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18785 }
18786 CONSTEXPR npu_op_elementwise_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18787 {
18788 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18789 return *this;
18790 }
18791 CONSTEXPR NPU_NAMESPACE::elementwise_mode get_elementwise_mode() const
18792 {
18793 return static_cast<NPU_NAMESPACE::elementwise_mode>(elementwise_mode);
18794 }
18795 CONSTEXPR npu_op_elementwise_t &set_elementwise_mode(NPU_NAMESPACE::elementwise_mode value)
18796 {
18797 elementwise_mode = static_cast<uint8_t>(value) & ((1U << 6) - 1);
18798 return *this;
18799 }
18800#ifdef NPU_DISASSEMBLE
18801 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
18802 {
18803 fields.push_back(std::make_pair<std::string, std::string>(
18804 "elementwise_mode",
18805 (elementwise_mode < (sizeof(elementwise_mode_str) / sizeof(elementwise_mode_str[0])) ?
18806 elementwise_mode_str[elementwise_mode] :
18807 "****")));
18808 }
18809#endif
18810#endif
18811 };
18812 // Queue new DMA for the given channel
18813 struct npu_op_dma_start_t
18814 {
18815#ifdef __cplusplus
18816 private:
18817#endif
18818 uint32_t opcode : 10; // opcode
18819 uint32_t reserved0 : 4;
18820 uint32_t control : 2; // control
18821 uint32_t reserved1 : 16;
18822#ifdef __cplusplus
18823 public:
18825 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START)), reserved0(0),
18826 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), reserved1(0)
18827 {
18828 }
18829 CONSTEXPR bool valid() const
18830 {
18831 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START) &&
18832 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18833 }
18834 CONSTEXPR void init()
18835 {
18836 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START);
18837 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18838 }
18839 operator uint32_t()
18840 {
18841 uint32_t word;
18842 std::memcpy(&word, this, sizeof(word));
18843 return word;
18844 }
18845 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18846 {
18847 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18848 }
18849 CONSTEXPR npu_op_dma_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18850 {
18851 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18852 return *this;
18853 }
18854 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18855 {
18856 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18857 }
18858 CONSTEXPR npu_op_dma_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18859 {
18860 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18861 return *this;
18862 }
18863#ifdef NPU_DISASSEMBLE
18864 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const {}
18865#endif
18866#endif
18867 };
18868 // Wait for the DMA channel to have k or fewer active descriptors outstanding
18869 struct npu_op_dma_wait_t
18870 {
18871#ifdef __cplusplus
18872 private:
18873#endif
18874 uint32_t opcode : 10; // opcode
18875 uint32_t reserved0 : 4;
18876 uint32_t control : 2; // control
18877 uint32_t k : 4; // Number of outstanding descriptors
18878 uint32_t reserved1 : 12;
18879#ifdef __cplusplus
18880 public:
18881 npu_op_dma_wait_t(uint32_t _k) :
18882 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT)), reserved0(0),
18883 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), k(_k & ((1U << 4) - 1)), reserved1(0)
18884 {
18885 }
18887 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT)), reserved0(0),
18888 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), k(0), reserved1(0)
18889 {
18890 }
18891 CONSTEXPR bool valid() const
18892 {
18893 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT) &&
18894 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18895 }
18896 CONSTEXPR void init()
18897 {
18898 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT);
18899 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18900 }
18901 operator uint32_t()
18902 {
18903 uint32_t word;
18904 std::memcpy(&word, this, sizeof(word));
18905 return word;
18906 }
18907 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18908 {
18909 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18910 }
18911 CONSTEXPR npu_op_dma_wait_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18912 {
18913 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18914 return *this;
18915 }
18916 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18917 {
18918 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18919 }
18920 CONSTEXPR npu_op_dma_wait_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18921 {
18922 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18923 return *this;
18924 }
18925 CONSTEXPR uint32_t get_k() const
18926 {
18927 return static_cast<uint32_t>(k);
18928 }
18929 CONSTEXPR npu_op_dma_wait_t &set_k(uint32_t value)
18930 {
18931 k = static_cast<uint8_t>(value) & ((1U << 4) - 1);
18932 return *this;
18933 }
18934#ifdef NPU_DISASSEMBLE
18935 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
18936 {
18937 fields.push_back(std::make_pair<std::string, std::string>("k", std::to_string(k)));
18938 }
18939#endif
18940#endif
18941 };
18942 // Wait for n or fewer kernel operations to be remaining
18944 {
18945#ifdef __cplusplus
18946 private:
18947#endif
18948 uint32_t opcode : 10; // opcode
18949 uint32_t reserved0 : 4;
18950 uint32_t control : 2; // control
18951 uint32_t n : 2; // Number of kernel operations in range 0-3
18952 uint32_t reserved1 : 14;
18953#ifdef __cplusplus
18954 public:
18955 npu_op_kernel_wait_t(uint32_t _n) :
18956 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT)), reserved0(0),
18957 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), n(_n & ((1U << 2) - 1)), reserved1(0)
18958 {
18959 }
18961 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT)), reserved0(0),
18962 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), n(0), reserved1(0)
18963 {
18964 }
18965 CONSTEXPR bool valid() const
18966 {
18967 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT) &&
18968 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18969 }
18970 CONSTEXPR void init()
18971 {
18972 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT);
18973 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18974 }
18975 operator uint32_t()
18976 {
18977 uint32_t word;
18978 std::memcpy(&word, this, sizeof(word));
18979 return word;
18980 }
18981 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
18982 {
18983 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
18984 }
18985 CONSTEXPR npu_op_kernel_wait_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
18986 {
18987 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
18988 return *this;
18989 }
18990 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
18991 {
18992 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
18993 }
18994 CONSTEXPR npu_op_kernel_wait_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
18995 {
18996 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
18997 return *this;
18998 }
18999 CONSTEXPR uint32_t get_n() const
19000 {
19001 return static_cast<uint32_t>(n);
19002 }
19003 CONSTEXPR npu_op_kernel_wait_t &set_n(uint32_t value)
19004 {
19005 n = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19006 return *this;
19007 }
19008#ifdef NPU_DISASSEMBLE
19009 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19010 {
19011 fields.push_back(std::make_pair<std::string, std::string>("n", std::to_string(n)));
19012 }
19013#endif
19014#endif
19015 };
19016 // Enable or disable PMU counting (debug feature only)
19017 struct npu_op_pmu_mask_t
19018 {
19019#ifdef __cplusplus
19020 private:
19021#endif
19022 uint32_t opcode : 10; // opcode
19023 uint32_t reserved0 : 4;
19024 uint32_t control : 2; // control
19025 uint32_t enable : 1; // Enable or disable PMU mask
19026 uint32_t reserved1 : 15;
19027#ifdef __cplusplus
19028 public:
19029 npu_op_pmu_mask_t(uint32_t _enable) :
19030 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK)), reserved0(0),
19031 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), enable(_enable & ((1U << 1) - 1)),
19032 reserved1(0)
19033 {
19034 }
19036 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK)), reserved0(0),
19037 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), enable(0), reserved1(0)
19038 {
19039 }
19040 CONSTEXPR bool valid() const
19041 {
19042 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK) &&
19043 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19044 }
19045 CONSTEXPR void init()
19046 {
19047 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK);
19048 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19049 }
19050 operator uint32_t()
19051 {
19052 uint32_t word;
19053 std::memcpy(&word, this, sizeof(word));
19054 return word;
19055 }
19056 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19057 {
19058 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19059 }
19060 CONSTEXPR npu_op_pmu_mask_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19061 {
19062 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19063 return *this;
19064 }
19065 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19066 {
19067 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19068 }
19069 CONSTEXPR npu_op_pmu_mask_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19070 {
19071 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19072 return *this;
19073 }
19074 CONSTEXPR uint32_t get_enable() const
19075 {
19076 return static_cast<uint32_t>(enable);
19077 }
19078 CONSTEXPR npu_op_pmu_mask_t &set_enable(uint32_t value)
19079 {
19080 enable = static_cast<uint8_t>(value) & ((1U << 1) - 1);
19081 return *this;
19082 }
19083#ifdef NPU_DISASSEMBLE
19084 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19085 {
19086 fields.push_back(std::make_pair<std::string, std::string>("enable", std::to_string(enable)));
19087 }
19088#endif
19089#endif
19090 };
19091 // IFM top pad
19093 {
19094#ifdef __cplusplus
19095 private:
19096#endif
19097 uint32_t opcode : 10; // opcode
19098 uint32_t reserved0 : 4;
19099 uint32_t control : 2; // control
19100 uint32_t pad : 7; // IFM top pad
19101 uint32_t reserved1 : 9;
19102#ifdef __cplusplus
19103 public:
19104 npu_set_ifm_pad_top_t(uint32_t _pad) :
19105 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP)), reserved0(0),
19106 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 7) - 1)), reserved1(0)
19107 {
19108 }
19110 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP)), reserved0(0),
19111 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19112 {
19113 }
19114 CONSTEXPR bool valid() const
19115 {
19116 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP) &&
19117 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19118 }
19119 CONSTEXPR void init()
19120 {
19121 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP);
19122 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19123 }
19124 operator uint32_t()
19125 {
19126 uint32_t word;
19127 std::memcpy(&word, this, sizeof(word));
19128 return word;
19129 }
19130 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19131 {
19132 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19133 }
19134 CONSTEXPR npu_set_ifm_pad_top_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19135 {
19136 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19137 return *this;
19138 }
19139 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19140 {
19141 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19142 }
19143 CONSTEXPR npu_set_ifm_pad_top_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19144 {
19145 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19146 return *this;
19147 }
19148 CONSTEXPR uint32_t get_pad() const
19149 {
19150 return static_cast<uint32_t>(pad);
19151 }
19152 CONSTEXPR npu_set_ifm_pad_top_t &set_pad(uint32_t value)
19153 {
19154 pad = static_cast<uint8_t>(value) & ((1U << 7) - 1);
19155 return *this;
19156 }
19157#ifdef NPU_DISASSEMBLE
19158 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19159 {
19160 fields.push_back(std::make_pair<std::string, std::string>("pad", std::to_string(pad)));
19161 }
19162#endif
19163#endif
19164 };
19165 // IFM left pad
19167 {
19168#ifdef __cplusplus
19169 private:
19170#endif
19171 uint32_t opcode : 10; // opcode
19172 uint32_t reserved0 : 4;
19173 uint32_t control : 2; // control
19174 uint32_t pad : 7; // IFM left pad
19175 uint32_t reserved1 : 9;
19176#ifdef __cplusplus
19177 public:
19178 npu_set_ifm_pad_left_t(uint32_t _pad) :
19179 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT)), reserved0(0),
19180 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 7) - 1)), reserved1(0)
19181 {
19182 }
19184 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT)), reserved0(0),
19185 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19186 {
19187 }
19188 CONSTEXPR bool valid() const
19189 {
19190 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT) &&
19191 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19192 }
19193 CONSTEXPR void init()
19194 {
19195 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT);
19196 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19197 }
19198 operator uint32_t()
19199 {
19200 uint32_t word;
19201 std::memcpy(&word, this, sizeof(word));
19202 return word;
19203 }
19204 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19205 {
19206 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19207 }
19208 CONSTEXPR npu_set_ifm_pad_left_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19209 {
19210 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19211 return *this;
19212 }
19213 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19214 {
19215 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19216 }
19217 CONSTEXPR npu_set_ifm_pad_left_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19218 {
19219 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19220 return *this;
19221 }
19222 CONSTEXPR uint32_t get_pad() const
19223 {
19224 return static_cast<uint32_t>(pad);
19225 }
19226 CONSTEXPR npu_set_ifm_pad_left_t &set_pad(uint32_t value)
19227 {
19228 pad = static_cast<uint8_t>(value) & ((1U << 7) - 1);
19229 return *this;
19230 }
19231#ifdef NPU_DISASSEMBLE
19232 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19233 {
19234 fields.push_back(std::make_pair<std::string, std::string>("pad", std::to_string(pad)));
19235 }
19236#endif
19237#endif
19238 };
19239 // IFM right pad
19241 {
19242#ifdef __cplusplus
19243 private:
19244#endif
19245 uint32_t opcode : 10; // opcode
19246 uint32_t reserved0 : 4;
19247 uint32_t control : 2; // control
19248 uint32_t pad : 8; // IFM right pad. Max value is 128
19249 uint32_t reserved1 : 8;
19250#ifdef __cplusplus
19251 public:
19252 npu_set_ifm_pad_right_t(uint32_t _pad) :
19253 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT)), reserved0(0),
19254 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 8) - 1)), reserved1(0)
19255 {
19256 }
19258 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT)), reserved0(0),
19259 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19260 {
19261 }
19262 CONSTEXPR bool valid() const
19263 {
19264 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT) &&
19265 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19266 }
19267 CONSTEXPR void init()
19268 {
19269 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT);
19270 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19271 }
19272 operator uint32_t()
19273 {
19274 uint32_t word;
19275 std::memcpy(&word, this, sizeof(word));
19276 return word;
19277 }
19278 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19279 {
19280 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19281 }
19282 CONSTEXPR npu_set_ifm_pad_right_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19283 {
19284 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19285 return *this;
19286 }
19287 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19288 {
19289 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19290 }
19291 CONSTEXPR npu_set_ifm_pad_right_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19292 {
19293 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19294 return *this;
19295 }
19296 CONSTEXPR uint32_t get_pad() const
19297 {
19298 return static_cast<uint32_t>(pad);
19299 }
19300 CONSTEXPR npu_set_ifm_pad_right_t &set_pad(uint32_t value)
19301 {
19302 pad = static_cast<uint8_t>(value) & ((1U << 8) - 1);
19303 return *this;
19304 }
19305#ifdef NPU_DISASSEMBLE
19306 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19307 {
19308 fields.push_back(std::make_pair<std::string, std::string>("pad", std::to_string(pad)));
19309 }
19310#endif
19311#endif
19312 };
19313 // IFM bottom pad
19315 {
19316#ifdef __cplusplus
19317 private:
19318#endif
19319 uint32_t opcode : 10; // opcode
19320 uint32_t reserved0 : 4;
19321 uint32_t control : 2; // control
19322 uint32_t pad : 8; // IFM bottom pad. Max value is 128
19323 uint32_t reserved1 : 8;
19324#ifdef __cplusplus
19325 public:
19326 npu_set_ifm_pad_bottom_t(uint32_t _pad) :
19327 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM)), reserved0(0),
19328 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 8) - 1)), reserved1(0)
19329 {
19330 }
19332 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM)), reserved0(0),
19333 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19334 {
19335 }
19336 CONSTEXPR bool valid() const
19337 {
19338 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM) &&
19339 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19340 }
19341 CONSTEXPR void init()
19342 {
19343 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM);
19344 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19345 }
19346 operator uint32_t()
19347 {
19348 uint32_t word;
19349 std::memcpy(&word, this, sizeof(word));
19350 return word;
19351 }
19352 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19353 {
19354 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19355 }
19356 CONSTEXPR npu_set_ifm_pad_bottom_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19357 {
19358 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19359 return *this;
19360 }
19361 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19362 {
19363 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19364 }
19365 CONSTEXPR npu_set_ifm_pad_bottom_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19366 {
19367 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19368 return *this;
19369 }
19370 CONSTEXPR uint32_t get_pad() const
19371 {
19372 return static_cast<uint32_t>(pad);
19373 }
19374 CONSTEXPR npu_set_ifm_pad_bottom_t &set_pad(uint32_t value)
19375 {
19376 pad = static_cast<uint8_t>(value) & ((1U << 8) - 1);
19377 return *this;
19378 }
19379#ifdef NPU_DISASSEMBLE
19380 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19381 {
19382 fields.push_back(std::make_pair<std::string, std::string>("pad", std::to_string(pad)));
19383 }
19384#endif
19385#endif
19386 };
19387 // Number of input channels for convolution
19389 {
19390#ifdef __cplusplus
19391 private:
19392#endif
19393 uint32_t opcode : 10; // opcode
19394 uint32_t reserved0 : 4;
19395 uint32_t control : 2; // control
19396 uint32_t depth_m1 : 16; // Number of input channels for convolution
19397#ifdef __cplusplus
19398 public:
19399 npu_set_ifm_depth_m1_t(uint32_t _depth_m1) :
19400 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1)), reserved0(0),
19401 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 16) - 1))
19402 {
19403 }
19405 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1)), reserved0(0),
19406 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0)
19407 {
19408 }
19409 CONSTEXPR bool valid() const
19410 {
19411 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1) &&
19412 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19413 }
19414 CONSTEXPR void init()
19415 {
19416 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1);
19417 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19418 }
19419 operator uint32_t()
19420 {
19421 uint32_t word;
19422 std::memcpy(&word, this, sizeof(word));
19423 return word;
19424 }
19425 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19426 {
19427 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19428 }
19429 CONSTEXPR npu_set_ifm_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19430 {
19431 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19432 return *this;
19433 }
19434 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19435 {
19436 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19437 }
19438 CONSTEXPR npu_set_ifm_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19439 {
19440 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19441 return *this;
19442 }
19443 CONSTEXPR uint32_t get_depth_m1() const
19444 {
19445 return static_cast<uint32_t>(depth_m1);
19446 }
19447 CONSTEXPR npu_set_ifm_depth_m1_t &set_depth_m1(uint32_t value)
19448 {
19449 depth_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
19450 return *this;
19451 }
19452#ifdef NPU_DISASSEMBLE
19453 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19454 {
19455 fields.push_back(std::make_pair<std::string, std::string>("depth_m1", std::to_string(depth_m1)));
19456 }
19457#endif
19458#endif
19459 };
19460 // IFM Precision
19462 {
19463#ifdef __cplusplus
19464 private:
19465#endif
19466 uint32_t opcode : 10; // opcode
19467 uint32_t reserved0 : 4;
19468 uint32_t control : 2; // control
19469 uint32_t activation_type : 1; // IFM type
19470 uint32_t reserved1 : 1;
19471 uint32_t activation_precision : 2; // IFM precision
19472 uint32_t reserved2 : 2;
19473 uint32_t activation_format : 2; // IFM format
19474 uint32_t scale_mode : 2; // IFM scale mode
19475 uint32_t reserved3 : 4;
19476 uint32_t round_mode : 2; // IFM round mode
19477#ifdef __cplusplus
19478 public:
19479 npu_set_ifm_precision_t(NPU_NAMESPACE::activation_type _activation_type,
19480 NPU_NAMESPACE::activation_precision _activation_precision,
19481 NPU_NAMESPACE::activation_format _activation_format,
19482 NPU_NAMESPACE::ifm_scale_mode _scale_mode,
19483 NPU_NAMESPACE::round_mode _round_mode) :
19484 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION)),
19485 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
19486 activation_type(static_cast<uint8_t>(_activation_type) & ((1U << 1) - 1)), reserved1(0),
19487 activation_precision(static_cast<uint8_t>(_activation_precision) & ((1U << 2) - 1)), reserved2(0),
19488 activation_format(static_cast<uint8_t>(_activation_format) & ((1U << 2) - 1)),
19489 scale_mode(static_cast<uint8_t>(_scale_mode) & ((1U << 2) - 1)), reserved3(0),
19490 round_mode(static_cast<uint8_t>(_round_mode) & ((1U << 2) - 1))
19491 {
19492 }
19494 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION)), reserved0(0),
19495 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0), reserved1(0),
19496 activation_precision(0), reserved2(0), activation_format(0), scale_mode(0), reserved3(0), round_mode(0)
19497 {
19498 }
19499 CONSTEXPR bool valid() const
19500 {
19501 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION) &&
19502 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19503 }
19504 CONSTEXPR void init()
19505 {
19506 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION);
19507 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19508 }
19509 operator uint32_t()
19510 {
19511 uint32_t word;
19512 std::memcpy(&word, this, sizeof(word));
19513 return word;
19514 }
19515 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19516 {
19517 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19518 }
19519 CONSTEXPR npu_set_ifm_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19520 {
19521 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19522 return *this;
19523 }
19524 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19525 {
19526 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19527 }
19528 CONSTEXPR npu_set_ifm_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19529 {
19530 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19531 return *this;
19532 }
19533 CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const
19534 {
19535 return static_cast<NPU_NAMESPACE::activation_type>(activation_type);
19536 }
19537 CONSTEXPR npu_set_ifm_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value)
19538 {
19539 activation_type = static_cast<uint8_t>(value) & ((1U << 1) - 1);
19540 return *this;
19541 }
19542 CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const
19543 {
19544 return static_cast<NPU_NAMESPACE::activation_precision>(activation_precision);
19545 }
19546 CONSTEXPR npu_set_ifm_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value)
19547 {
19548 activation_precision = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19549 return *this;
19550 }
19551 CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const
19552 {
19553 return static_cast<NPU_NAMESPACE::activation_format>(activation_format);
19554 }
19555 CONSTEXPR npu_set_ifm_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value)
19556 {
19557 activation_format = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19558 return *this;
19559 }
19560 CONSTEXPR NPU_NAMESPACE::ifm_scale_mode get_scale_mode() const
19561 {
19562 return static_cast<NPU_NAMESPACE::ifm_scale_mode>(scale_mode);
19563 }
19564 CONSTEXPR npu_set_ifm_precision_t &set_scale_mode(NPU_NAMESPACE::ifm_scale_mode value)
19565 {
19566 scale_mode = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19567 return *this;
19568 }
19569 CONSTEXPR NPU_NAMESPACE::round_mode get_round_mode() const
19570 {
19571 return static_cast<NPU_NAMESPACE::round_mode>(round_mode);
19572 }
19573 CONSTEXPR npu_set_ifm_precision_t &set_round_mode(NPU_NAMESPACE::round_mode value)
19574 {
19575 round_mode = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19576 return *this;
19577 }
19578#ifdef NPU_DISASSEMBLE
19579 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19580 {
19581 fields.push_back(std::make_pair<std::string, std::string>(
19582 "activation_type",
19583 (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ?
19584 activation_type_str[activation_type] :
19585 "****")));
19586 fields.push_back(std::make_pair<std::string, std::string>(
19587 "activation_precision",
19588 (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ?
19589 activation_precision_str[activation_precision] :
19590 "****")));
19591 fields.push_back(std::make_pair<std::string, std::string>(
19592 "activation_format",
19593 (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ?
19594 activation_format_str[activation_format] :
19595 "****")));
19596 fields.push_back(std::make_pair<std::string, std::string>(
19597 "scale_mode",
19598 (scale_mode < (sizeof(ifm_scale_mode_str) / sizeof(ifm_scale_mode_str[0])) ?
19599 ifm_scale_mode_str[scale_mode] :
19600 "****")));
19601 fields.push_back(std::make_pair<std::string, std::string>(
19602 "round_mode",
19603 (round_mode < (sizeof(round_mode_str) / sizeof(round_mode_str[0])) ? round_mode_str[round_mode] :
19604 "****")));
19605 }
19606#endif
19607#endif
19608 };
19609 // IFM upscale mode
19611 {
19612#ifdef __cplusplus
19613 private:
19614#endif
19615 uint32_t opcode : 10; // opcode
19616 uint32_t reserved0 : 4;
19617 uint32_t control : 2; // control
19618 uint32_t mode : 2; // IFM upscale mode
19619 uint32_t reserved1 : 14;
19620#ifdef __cplusplus
19621 public:
19622 npu_set_ifm_upscale_t(NPU_NAMESPACE::ifm_upscale_mode _mode) :
19623 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE)), reserved0(0),
19624 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
19625 mode(static_cast<uint8_t>(_mode) & ((1U << 2) - 1)), reserved1(0)
19626 {
19627 }
19629 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE)), reserved0(0),
19630 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), mode(0), reserved1(0)
19631 {
19632 }
19633 CONSTEXPR bool valid() const
19634 {
19635 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE) &&
19636 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19637 }
19638 CONSTEXPR void init()
19639 {
19640 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE);
19641 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19642 }
19643 operator uint32_t()
19644 {
19645 uint32_t word;
19646 std::memcpy(&word, this, sizeof(word));
19647 return word;
19648 }
19649 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19650 {
19651 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19652 }
19653 CONSTEXPR npu_set_ifm_upscale_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19654 {
19655 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19656 return *this;
19657 }
19658 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19659 {
19660 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19661 }
19662 CONSTEXPR npu_set_ifm_upscale_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19663 {
19664 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19665 return *this;
19666 }
19667 CONSTEXPR NPU_NAMESPACE::ifm_upscale_mode get_mode() const
19668 {
19669 return static_cast<NPU_NAMESPACE::ifm_upscale_mode>(mode);
19670 }
19671 CONSTEXPR npu_set_ifm_upscale_t &set_mode(NPU_NAMESPACE::ifm_upscale_mode value)
19672 {
19673 mode = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19674 return *this;
19675 }
19676#ifdef NPU_DISASSEMBLE
19677 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19678 {
19679 fields.push_back(std::make_pair<std::string, std::string>(
19680 "mode",
19681 (mode < (sizeof(ifm_upscale_mode_str) / sizeof(ifm_upscale_mode_str[0])) ? ifm_upscale_mode_str[mode] :
19682 "****")));
19683 }
19684#endif
19685#endif
19686 };
19687 // IFM zero point
19689 {
19690#ifdef __cplusplus
19691 private:
19692#endif
19693 uint32_t opcode : 10; // opcode
19694 uint32_t reserved0 : 4;
19695 uint32_t control : 2; // control
19696 uint32_t zero_point : 16; // Zero point offset
19697#ifdef __cplusplus
19698 public:
19699 npu_set_ifm_zero_point_t(uint32_t _zero_point) :
19700 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT)), reserved0(0),
19701 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
19702 zero_point(_zero_point & ((1U << 16) - 1))
19703 {
19704 }
19706 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT)), reserved0(0),
19707 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0)
19708 {
19709 }
19710 CONSTEXPR bool valid() const
19711 {
19712 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT) &&
19713 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19714 }
19715 CONSTEXPR void init()
19716 {
19717 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT);
19718 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19719 }
19720 operator uint32_t()
19721 {
19722 uint32_t word;
19723 std::memcpy(&word, this, sizeof(word));
19724 return word;
19725 }
19726 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19727 {
19728 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19729 }
19730 CONSTEXPR npu_set_ifm_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19731 {
19732 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19733 return *this;
19734 }
19735 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19736 {
19737 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19738 }
19739 CONSTEXPR npu_set_ifm_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19740 {
19741 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19742 return *this;
19743 }
19744 CONSTEXPR uint32_t get_zero_point() const
19745 {
19746 return static_cast<uint32_t>(zero_point);
19747 }
19748 CONSTEXPR npu_set_ifm_zero_point_t &set_zero_point(uint32_t value)
19749 {
19750 zero_point = static_cast<uint16_t>(value) & ((1U << 16) - 1);
19751 return *this;
19752 }
19753#ifdef NPU_DISASSEMBLE
19754 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19755 {
19756 fields.push_back(std::make_pair<std::string, std::string>("zero_point", std::to_string(zero_point)));
19757 }
19758#endif
19759#endif
19760 };
19761 // IFM Tile 0 and tile 2 width
19763 {
19764#ifdef __cplusplus
19765 private:
19766#endif
19767 uint32_t opcode : 10; // opcode
19768 uint32_t reserved0 : 4;
19769 uint32_t control : 2; // control
19770 uint32_t width_m1 : 16; // IFM Tile 0 and tile 2 width
19771#ifdef __cplusplus
19772 public:
19773 npu_set_ifm_width0_m1_t(uint32_t _width_m1) :
19774 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1)), reserved0(0),
19775 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
19776 {
19777 }
19779 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1)), reserved0(0),
19780 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0)
19781 {
19782 }
19783 CONSTEXPR bool valid() const
19784 {
19785 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1) &&
19786 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19787 }
19788 CONSTEXPR void init()
19789 {
19790 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1);
19791 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19792 }
19793 operator uint32_t()
19794 {
19795 uint32_t word;
19796 std::memcpy(&word, this, sizeof(word));
19797 return word;
19798 }
19799 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19800 {
19801 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19802 }
19803 CONSTEXPR npu_set_ifm_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19804 {
19805 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19806 return *this;
19807 }
19808 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19809 {
19810 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19811 }
19812 CONSTEXPR npu_set_ifm_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19813 {
19814 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19815 return *this;
19816 }
19817 CONSTEXPR uint32_t get_width_m1() const
19818 {
19819 return static_cast<uint32_t>(width_m1);
19820 }
19821 CONSTEXPR npu_set_ifm_width0_m1_t &set_width_m1(uint32_t value)
19822 {
19823 width_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
19824 return *this;
19825 }
19826#ifdef NPU_DISASSEMBLE
19827 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19828 {
19829 fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
19830 }
19831#endif
19832#endif
19833 };
19834 // IFM Tile 0 height
19836 {
19837#ifdef __cplusplus
19838 private:
19839#endif
19840 uint32_t opcode : 10; // opcode
19841 uint32_t reserved0 : 4;
19842 uint32_t control : 2; // control
19843 uint32_t height_m1 : 16; // IFM Tile 0 height
19844#ifdef __cplusplus
19845 public:
19846 npu_set_ifm_height0_m1_t(uint32_t _height_m1) :
19847 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1)), reserved0(0),
19848 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
19849 {
19850 }
19852 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1)), reserved0(0),
19853 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
19854 {
19855 }
19856 CONSTEXPR bool valid() const
19857 {
19858 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1) &&
19859 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19860 }
19861 CONSTEXPR void init()
19862 {
19863 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1);
19864 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19865 }
19866 operator uint32_t()
19867 {
19868 uint32_t word;
19869 std::memcpy(&word, this, sizeof(word));
19870 return word;
19871 }
19872 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19873 {
19874 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19875 }
19876 CONSTEXPR npu_set_ifm_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19877 {
19878 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19879 return *this;
19880 }
19881 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19882 {
19883 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19884 }
19885 CONSTEXPR npu_set_ifm_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19886 {
19887 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19888 return *this;
19889 }
19890 CONSTEXPR uint32_t get_height_m1() const
19891 {
19892 return static_cast<uint32_t>(height_m1);
19893 }
19894 CONSTEXPR npu_set_ifm_height0_m1_t &set_height_m1(uint32_t value)
19895 {
19896 height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
19897 return *this;
19898 }
19899#ifdef NPU_DISASSEMBLE
19900 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19901 {
19902 fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
19903 }
19904#endif
19905#endif
19906 };
19907 // IFM Tile 1 height
19909 {
19910#ifdef __cplusplus
19911 private:
19912#endif
19913 uint32_t opcode : 10; // opcode
19914 uint32_t reserved0 : 4;
19915 uint32_t control : 2; // control
19916 uint32_t height_m1 : 16; // IFM Tile 1 height
19917#ifdef __cplusplus
19918 public:
19919 npu_set_ifm_height1_m1_t(uint32_t _height_m1) :
19920 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1)), reserved0(0),
19921 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
19922 {
19923 }
19925 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1)), reserved0(0),
19926 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
19927 {
19928 }
19929 CONSTEXPR bool valid() const
19930 {
19931 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1) &&
19932 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19933 }
19934 CONSTEXPR void init()
19935 {
19936 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1);
19937 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19938 }
19939 operator uint32_t()
19940 {
19941 uint32_t word;
19942 std::memcpy(&word, this, sizeof(word));
19943 return word;
19944 }
19945 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
19946 {
19947 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
19948 }
19949 CONSTEXPR npu_set_ifm_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
19950 {
19951 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
19952 return *this;
19953 }
19954 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
19955 {
19956 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
19957 }
19958 CONSTEXPR npu_set_ifm_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
19959 {
19960 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
19961 return *this;
19962 }
19963 CONSTEXPR uint32_t get_height_m1() const
19964 {
19965 return static_cast<uint32_t>(height_m1);
19966 }
19967 CONSTEXPR npu_set_ifm_height1_m1_t &set_height_m1(uint32_t value)
19968 {
19969 height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
19970 return *this;
19971 }
19972#ifdef NPU_DISASSEMBLE
19973 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
19974 {
19975 fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
19976 }
19977#endif
19978#endif
19979 };
19980 // End of IB0,IB1 buffers
19982 {
19983#ifdef __cplusplus
19984 private:
19985#endif
19986 uint32_t opcode : 10; // opcode
19987 uint32_t reserved0 : 4;
19988 uint32_t control : 2; // control
19989 uint32_t ib_end : 6; // End of IB0,IB1 buffers in the SHRAM in KB units. Multiple of 2
19990 uint32_t reserved1 : 10;
19991#ifdef __cplusplus
19992 public:
19993 npu_set_ifm_ib_end_t(uint32_t _ib_end) :
19994 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END)), reserved0(0),
19995 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_end(_ib_end & ((1U << 6) - 1)),
19996 reserved1(0)
19997 {
19998 }
20000 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END)), reserved0(0),
20001 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_end(0), reserved1(0)
20002 {
20003 }
20004 CONSTEXPR bool valid() const
20005 {
20006 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END) &&
20007 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20008 }
20009 CONSTEXPR void init()
20010 {
20011 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END);
20012 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20013 }
20014 operator uint32_t()
20015 {
20016 uint32_t word;
20017 std::memcpy(&word, this, sizeof(word));
20018 return word;
20019 }
20020 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20021 {
20022 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20023 }
20024 CONSTEXPR npu_set_ifm_ib_end_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20025 {
20026 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20027 return *this;
20028 }
20029 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20030 {
20031 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20032 }
20033 CONSTEXPR npu_set_ifm_ib_end_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20034 {
20035 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20036 return *this;
20037 }
20038 CONSTEXPR uint32_t get_ib_end() const
20039 {
20040 return static_cast<uint32_t>(ib_end);
20041 }
20042 CONSTEXPR npu_set_ifm_ib_end_t &set_ib_end(uint32_t value)
20043 {
20044 ib_end = static_cast<uint8_t>(value) & ((1U << 6) - 1);
20045 return *this;
20046 }
20047#ifdef NPU_DISASSEMBLE
20048 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20049 {
20050 fields.push_back(std::make_pair<std::string, std::string>("ib_end", std::to_string(ib_end)));
20051 }
20052#endif
20053#endif
20054 };
20055 // Index n for IFM access
20057 {
20058#ifdef __cplusplus
20059 private:
20060#endif
20061 uint32_t opcode : 10; // opcode
20062 uint32_t reserved0 : 4;
20063 uint32_t control : 2; // control
20064 uint32_t region : 3; // Region number n
20065 uint32_t reserved1 : 13;
20066#ifdef __cplusplus
20067 public:
20068 npu_set_ifm_region_t(uint32_t _region) :
20069 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION)), reserved0(0),
20070 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
20071 reserved1(0)
20072 {
20073 }
20075 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION)), reserved0(0),
20076 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
20077 {
20078 }
20079 CONSTEXPR bool valid() const
20080 {
20081 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION) &&
20082 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20083 }
20084 CONSTEXPR void init()
20085 {
20086 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION);
20087 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20088 }
20089 operator uint32_t()
20090 {
20091 uint32_t word;
20092 std::memcpy(&word, this, sizeof(word));
20093 return word;
20094 }
20095 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20096 {
20097 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20098 }
20099 CONSTEXPR npu_set_ifm_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20100 {
20101 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20102 return *this;
20103 }
20104 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20105 {
20106 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20107 }
20108 CONSTEXPR npu_set_ifm_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20109 {
20110 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20111 return *this;
20112 }
20113 CONSTEXPR uint32_t get_region() const
20114 {
20115 return static_cast<uint32_t>(region);
20116 }
20117 CONSTEXPR npu_set_ifm_region_t &set_region(uint32_t value)
20118 {
20119 region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
20120 return *this;
20121 }
20122#ifdef NPU_DISASSEMBLE
20123 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20124 {
20125 fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
20126 }
20127#endif
20128#endif
20129 };
20130 // Output feature map width
20132 {
20133#ifdef __cplusplus
20134 private:
20135#endif
20136 uint32_t opcode : 10; // opcode
20137 uint32_t reserved0 : 4;
20138 uint32_t control : 2; // control
20139 uint32_t width_m1 : 16; // Output feature map width
20140#ifdef __cplusplus
20141 public:
20142 npu_set_ofm_width_m1_t(uint32_t _width_m1) :
20143 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1)), reserved0(0),
20144 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
20145 {
20146 }
20148 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1)), reserved0(0),
20149 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0)
20150 {
20151 }
20152 CONSTEXPR bool valid() const
20153 {
20154 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1) &&
20155 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20156 }
20157 CONSTEXPR void init()
20158 {
20159 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1);
20160 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20161 }
20162 operator uint32_t()
20163 {
20164 uint32_t word;
20165 std::memcpy(&word, this, sizeof(word));
20166 return word;
20167 }
20168 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20169 {
20170 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20171 }
20172 CONSTEXPR npu_set_ofm_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20173 {
20174 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20175 return *this;
20176 }
20177 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20178 {
20179 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20180 }
20181 CONSTEXPR npu_set_ofm_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20182 {
20183 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20184 return *this;
20185 }
20186 CONSTEXPR uint32_t get_width_m1() const
20187 {
20188 return static_cast<uint32_t>(width_m1);
20189 }
20190 CONSTEXPR npu_set_ofm_width_m1_t &set_width_m1(uint32_t value)
20191 {
20192 width_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20193 return *this;
20194 }
20195#ifdef NPU_DISASSEMBLE
20196 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20197 {
20198 fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
20199 }
20200#endif
20201#endif
20202 };
20203 // Output feature map height
20205 {
20206#ifdef __cplusplus
20207 private:
20208#endif
20209 uint32_t opcode : 10; // opcode
20210 uint32_t reserved0 : 4;
20211 uint32_t control : 2; // control
20212 uint32_t height_m1 : 16; // Output feature map height
20213#ifdef __cplusplus
20214 public:
20215 npu_set_ofm_height_m1_t(uint32_t _height_m1) :
20216 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1)), reserved0(0),
20217 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
20218 {
20219 }
20221 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1)), reserved0(0),
20222 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
20223 {
20224 }
20225 CONSTEXPR bool valid() const
20226 {
20227 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1) &&
20228 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20229 }
20230 CONSTEXPR void init()
20231 {
20232 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1);
20233 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20234 }
20235 operator uint32_t()
20236 {
20237 uint32_t word;
20238 std::memcpy(&word, this, sizeof(word));
20239 return word;
20240 }
20241 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20242 {
20243 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20244 }
20245 CONSTEXPR npu_set_ofm_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20246 {
20247 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20248 return *this;
20249 }
20250 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20251 {
20252 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20253 }
20254 CONSTEXPR npu_set_ofm_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20255 {
20256 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20257 return *this;
20258 }
20259 CONSTEXPR uint32_t get_height_m1() const
20260 {
20261 return static_cast<uint32_t>(height_m1);
20262 }
20263 CONSTEXPR npu_set_ofm_height_m1_t &set_height_m1(uint32_t value)
20264 {
20265 height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20266 return *this;
20267 }
20268#ifdef NPU_DISASSEMBLE
20269 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20270 {
20271 fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
20272 }
20273#endif
20274#endif
20275 };
20276 // Output feature map depth
20278 {
20279#ifdef __cplusplus
20280 private:
20281#endif
20282 uint32_t opcode : 10; // opcode
20283 uint32_t reserved0 : 4;
20284 uint32_t control : 2; // control
20285 uint32_t depth_m1 : 16; // Output feature map depth
20286#ifdef __cplusplus
20287 public:
20288 npu_set_ofm_depth_m1_t(uint32_t _depth_m1) :
20289 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1)), reserved0(0),
20290 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 16) - 1))
20291 {
20292 }
20294 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1)), reserved0(0),
20295 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0)
20296 {
20297 }
20298 CONSTEXPR bool valid() const
20299 {
20300 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1) &&
20301 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20302 }
20303 CONSTEXPR void init()
20304 {
20305 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1);
20306 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20307 }
20308 operator uint32_t()
20309 {
20310 uint32_t word;
20311 std::memcpy(&word, this, sizeof(word));
20312 return word;
20313 }
20314 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20315 {
20316 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20317 }
20318 CONSTEXPR npu_set_ofm_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20319 {
20320 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20321 return *this;
20322 }
20323 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20324 {
20325 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20326 }
20327 CONSTEXPR npu_set_ofm_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20328 {
20329 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20330 return *this;
20331 }
20332 CONSTEXPR uint32_t get_depth_m1() const
20333 {
20334 return static_cast<uint32_t>(depth_m1);
20335 }
20336 CONSTEXPR npu_set_ofm_depth_m1_t &set_depth_m1(uint32_t value)
20337 {
20338 depth_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20339 return *this;
20340 }
20341#ifdef NPU_DISASSEMBLE
20342 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20343 {
20344 fields.push_back(std::make_pair<std::string, std::string>("depth_m1", std::to_string(depth_m1)));
20345 }
20346#endif
20347#endif
20348 };
20349 // OFM Precision
20351 {
20352#ifdef __cplusplus
20353 private:
20354#endif
20355 uint32_t opcode : 10; // opcode
20356 uint32_t reserved0 : 4;
20357 uint32_t control : 2; // control
20358 uint32_t activation_type : 1; // OFM type
20359 uint32_t activation_precision : 2; // OFM precision
20360 uint32_t reserved1 : 3;
20361 uint32_t activation_format : 2; // OFM format
20362 uint32_t scale_mode : 1; // OFM scale mode
20363 uint32_t reserved2 : 5;
20364 uint32_t round_mode : 2; // OFM round mode
20365#ifdef __cplusplus
20366 public:
20367 npu_set_ofm_precision_t(NPU_NAMESPACE::activation_type _activation_type,
20368 NPU_NAMESPACE::activation_precision _activation_precision,
20369 NPU_NAMESPACE::activation_format _activation_format,
20370 NPU_NAMESPACE::ofm_scale_mode _scale_mode,
20371 NPU_NAMESPACE::round_mode _round_mode) :
20372 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION)),
20373 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
20374 activation_type(static_cast<uint8_t>(_activation_type) & ((1U << 1) - 1)),
20375 activation_precision(static_cast<uint8_t>(_activation_precision) & ((1U << 2) - 1)), reserved1(0),
20376 activation_format(static_cast<uint8_t>(_activation_format) & ((1U << 2) - 1)),
20377 scale_mode(static_cast<uint8_t>(_scale_mode) & ((1U << 1) - 1)), reserved2(0),
20378 round_mode(static_cast<uint8_t>(_round_mode) & ((1U << 2) - 1))
20379 {
20380 }
20382 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION)), reserved0(0),
20383 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0),
20384 activation_precision(0), reserved1(0), activation_format(0), scale_mode(0), reserved2(0), round_mode(0)
20385 {
20386 }
20387 CONSTEXPR bool valid() const
20388 {
20389 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION) &&
20390 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20391 }
20392 CONSTEXPR void init()
20393 {
20394 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION);
20395 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20396 }
20397 operator uint32_t()
20398 {
20399 uint32_t word;
20400 std::memcpy(&word, this, sizeof(word));
20401 return word;
20402 }
20403 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20404 {
20405 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20406 }
20407 CONSTEXPR npu_set_ofm_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20408 {
20409 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20410 return *this;
20411 }
20412 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20413 {
20414 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20415 }
20416 CONSTEXPR npu_set_ofm_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20417 {
20418 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20419 return *this;
20420 }
20421 CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const
20422 {
20423 return static_cast<NPU_NAMESPACE::activation_type>(activation_type);
20424 }
20425 CONSTEXPR npu_set_ofm_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value)
20426 {
20427 activation_type = static_cast<uint8_t>(value) & ((1U << 1) - 1);
20428 return *this;
20429 }
20430 CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const
20431 {
20432 return static_cast<NPU_NAMESPACE::activation_precision>(activation_precision);
20433 }
20434 CONSTEXPR npu_set_ofm_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value)
20435 {
20436 activation_precision = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20437 return *this;
20438 }
20439 CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const
20440 {
20441 return static_cast<NPU_NAMESPACE::activation_format>(activation_format);
20442 }
20443 CONSTEXPR npu_set_ofm_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value)
20444 {
20445 activation_format = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20446 return *this;
20447 }
20448 CONSTEXPR NPU_NAMESPACE::ofm_scale_mode get_scale_mode() const
20449 {
20450 return static_cast<NPU_NAMESPACE::ofm_scale_mode>(scale_mode);
20451 }
20452 CONSTEXPR npu_set_ofm_precision_t &set_scale_mode(NPU_NAMESPACE::ofm_scale_mode value)
20453 {
20454 scale_mode = static_cast<uint8_t>(value) & ((1U << 1) - 1);
20455 return *this;
20456 }
20457 CONSTEXPR NPU_NAMESPACE::round_mode get_round_mode() const
20458 {
20459 return static_cast<NPU_NAMESPACE::round_mode>(round_mode);
20460 }
20461 CONSTEXPR npu_set_ofm_precision_t &set_round_mode(NPU_NAMESPACE::round_mode value)
20462 {
20463 round_mode = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20464 return *this;
20465 }
20466#ifdef NPU_DISASSEMBLE
20467 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20468 {
20469 fields.push_back(std::make_pair<std::string, std::string>(
20470 "activation_type",
20471 (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ?
20472 activation_type_str[activation_type] :
20473 "****")));
20474 fields.push_back(std::make_pair<std::string, std::string>(
20475 "activation_precision",
20476 (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ?
20477 activation_precision_str[activation_precision] :
20478 "****")));
20479 fields.push_back(std::make_pair<std::string, std::string>(
20480 "activation_format",
20481 (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ?
20482 activation_format_str[activation_format] :
20483 "****")));
20484 fields.push_back(std::make_pair<std::string, std::string>(
20485 "scale_mode",
20486 (scale_mode < (sizeof(ofm_scale_mode_str) / sizeof(ofm_scale_mode_str[0])) ?
20487 ofm_scale_mode_str[scale_mode] :
20488 "****")));
20489 fields.push_back(std::make_pair<std::string, std::string>(
20490 "round_mode",
20491 (round_mode < (sizeof(round_mode_str) / sizeof(round_mode_str[0])) ? round_mode_str[round_mode] :
20492 "****")));
20493 }
20494#endif
20495#endif
20496 };
20497 // OFM block width
20499 {
20500#ifdef __cplusplus
20501 private:
20502#endif
20503 uint32_t opcode : 10; // opcode
20504 uint32_t reserved0 : 4;
20505 uint32_t control : 2; // control
20506 uint32_t width_m1 : 6; // OFM block width
20507 uint32_t reserved1 : 10;
20508#ifdef __cplusplus
20509 public:
20510 npu_set_ofm_blk_width_m1_t(uint32_t _width_m1) :
20511 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1)), reserved0(0),
20512 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 6) - 1)),
20513 reserved1(0)
20514 {
20515 }
20517 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1)), reserved0(0),
20518 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0), reserved1(0)
20519 {
20520 }
20521 CONSTEXPR bool valid() const
20522 {
20523 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1) &&
20524 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20525 }
20526 CONSTEXPR void init()
20527 {
20528 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1);
20529 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20530 }
20531 operator uint32_t()
20532 {
20533 uint32_t word;
20534 std::memcpy(&word, this, sizeof(word));
20535 return word;
20536 }
20537 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20538 {
20539 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20540 }
20541 CONSTEXPR npu_set_ofm_blk_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20542 {
20543 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20544 return *this;
20545 }
20546 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20547 {
20548 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20549 }
20550 CONSTEXPR npu_set_ofm_blk_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20551 {
20552 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20553 return *this;
20554 }
20555 CONSTEXPR uint32_t get_width_m1() const
20556 {
20557 return static_cast<uint32_t>(width_m1);
20558 }
20559 CONSTEXPR npu_set_ofm_blk_width_m1_t &set_width_m1(uint32_t value)
20560 {
20561 width_m1 = static_cast<uint8_t>(value) & ((1U << 6) - 1);
20562 return *this;
20563 }
20564#ifdef NPU_DISASSEMBLE
20565 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20566 {
20567 fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
20568 }
20569#endif
20570#endif
20571 };
20572 // OFM block height
20574 {
20575#ifdef __cplusplus
20576 private:
20577#endif
20578 uint32_t opcode : 10; // opcode
20579 uint32_t reserved0 : 4;
20580 uint32_t control : 2; // control
20581 uint32_t height_m1 : 5; // OFM block height
20582 uint32_t reserved1 : 11;
20583#ifdef __cplusplus
20584 public:
20585 npu_set_ofm_blk_height_m1_t(uint32_t _height_m1) :
20586 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1)), reserved0(0),
20587 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 5) - 1)),
20588 reserved1(0)
20589 {
20590 }
20592 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1)), reserved0(0),
20593 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0), reserved1(0)
20594 {
20595 }
20596 CONSTEXPR bool valid() const
20597 {
20598 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1) &&
20599 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20600 }
20601 CONSTEXPR void init()
20602 {
20603 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1);
20604 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20605 }
20606 operator uint32_t()
20607 {
20608 uint32_t word;
20609 std::memcpy(&word, this, sizeof(word));
20610 return word;
20611 }
20612 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20613 {
20614 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20615 }
20616 CONSTEXPR npu_set_ofm_blk_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20617 {
20618 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20619 return *this;
20620 }
20621 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20622 {
20623 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20624 }
20625 CONSTEXPR npu_set_ofm_blk_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20626 {
20627 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20628 return *this;
20629 }
20630 CONSTEXPR uint32_t get_height_m1() const
20631 {
20632 return static_cast<uint32_t>(height_m1);
20633 }
20634 CONSTEXPR npu_set_ofm_blk_height_m1_t &set_height_m1(uint32_t value)
20635 {
20636 height_m1 = static_cast<uint8_t>(value) & ((1U << 5) - 1);
20637 return *this;
20638 }
20639#ifdef NPU_DISASSEMBLE
20640 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20641 {
20642 fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
20643 }
20644#endif
20645#endif
20646 };
20647 // OFM block depth
20649 {
20650#ifdef __cplusplus
20651 private:
20652#endif
20653 uint32_t opcode : 10; // opcode
20654 uint32_t reserved0 : 4;
20655 uint32_t control : 2; // control
20656 uint32_t depth_m1 : 7; // OFM block depth
20657 uint32_t reserved1 : 9;
20658#ifdef __cplusplus
20659 public:
20660 npu_set_ofm_blk_depth_m1_t(uint32_t _depth_m1) :
20661 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1)), reserved0(0),
20662 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 7) - 1)),
20663 reserved1(0)
20664 {
20665 }
20667 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1)), reserved0(0),
20668 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), depth_m1(0), reserved1(0)
20669 {
20670 }
20671 CONSTEXPR bool valid() const
20672 {
20673 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1) &&
20674 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20675 }
20676 CONSTEXPR void init()
20677 {
20678 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1);
20679 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20680 }
20681 operator uint32_t()
20682 {
20683 uint32_t word;
20684 std::memcpy(&word, this, sizeof(word));
20685 return word;
20686 }
20687 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20688 {
20689 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20690 }
20691 CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20692 {
20693 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20694 return *this;
20695 }
20696 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20697 {
20698 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20699 }
20700 CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20701 {
20702 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20703 return *this;
20704 }
20705 CONSTEXPR uint32_t get_depth_m1() const
20706 {
20707 return static_cast<uint32_t>(depth_m1);
20708 }
20709 CONSTEXPR npu_set_ofm_blk_depth_m1_t &set_depth_m1(uint32_t value)
20710 {
20711 depth_m1 = static_cast<uint8_t>(value) & ((1U << 7) - 1);
20712 return *this;
20713 }
20714#ifdef NPU_DISASSEMBLE
20715 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20716 {
20717 fields.push_back(std::make_pair<std::string, std::string>("depth_m1", std::to_string(depth_m1)));
20718 }
20719#endif
20720#endif
20721 };
20722 // OFM zero point
20724 {
20725#ifdef __cplusplus
20726 private:
20727#endif
20728 uint32_t opcode : 10; // opcode
20729 uint32_t reserved0 : 4;
20730 uint32_t control : 2; // control
20731 uint32_t zero_point : 16; // Zero point offset
20732#ifdef __cplusplus
20733 public:
20734 npu_set_ofm_zero_point_t(uint32_t _zero_point) :
20735 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT)), reserved0(0),
20736 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
20737 zero_point(_zero_point & ((1U << 16) - 1))
20738 {
20739 }
20741 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT)), reserved0(0),
20742 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0)
20743 {
20744 }
20745 CONSTEXPR bool valid() const
20746 {
20747 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT) &&
20748 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20749 }
20750 CONSTEXPR void init()
20751 {
20752 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT);
20753 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20754 }
20755 operator uint32_t()
20756 {
20757 uint32_t word;
20758 std::memcpy(&word, this, sizeof(word));
20759 return word;
20760 }
20761 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20762 {
20763 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20764 }
20765 CONSTEXPR npu_set_ofm_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20766 {
20767 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20768 return *this;
20769 }
20770 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20771 {
20772 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20773 }
20774 CONSTEXPR npu_set_ofm_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20775 {
20776 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20777 return *this;
20778 }
20779 CONSTEXPR uint32_t get_zero_point() const
20780 {
20781 return static_cast<uint32_t>(zero_point);
20782 }
20783 CONSTEXPR npu_set_ofm_zero_point_t &set_zero_point(uint32_t value)
20784 {
20785 zero_point = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20786 return *this;
20787 }
20788#ifdef NPU_DISASSEMBLE
20789 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20790 {
20791 fields.push_back(std::make_pair<std::string, std::string>("zero_point", std::to_string(zero_point)));
20792 }
20793#endif
20794#endif
20795 };
20796 // OFM Tile 0 and tile 2 width
20798 {
20799#ifdef __cplusplus
20800 private:
20801#endif
20802 uint32_t opcode : 10; // opcode
20803 uint32_t reserved0 : 4;
20804 uint32_t control : 2; // control
20805 uint32_t width_m1 : 16; // OFM Tile 0 and tile 2 width
20806#ifdef __cplusplus
20807 public:
20808 npu_set_ofm_width0_m1_t(uint32_t _width_m1) :
20809 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1)), reserved0(0),
20810 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
20811 {
20812 }
20814 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1)), reserved0(0),
20815 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0)
20816 {
20817 }
20818 CONSTEXPR bool valid() const
20819 {
20820 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1) &&
20821 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20822 }
20823 CONSTEXPR void init()
20824 {
20825 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1);
20826 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20827 }
20828 operator uint32_t()
20829 {
20830 uint32_t word;
20831 std::memcpy(&word, this, sizeof(word));
20832 return word;
20833 }
20834 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20835 {
20836 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20837 }
20838 CONSTEXPR npu_set_ofm_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20839 {
20840 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20841 return *this;
20842 }
20843 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20844 {
20845 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20846 }
20847 CONSTEXPR npu_set_ofm_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20848 {
20849 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20850 return *this;
20851 }
20852 CONSTEXPR uint32_t get_width_m1() const
20853 {
20854 return static_cast<uint32_t>(width_m1);
20855 }
20856 CONSTEXPR npu_set_ofm_width0_m1_t &set_width_m1(uint32_t value)
20857 {
20858 width_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20859 return *this;
20860 }
20861#ifdef NPU_DISASSEMBLE
20862 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20863 {
20864 fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
20865 }
20866#endif
20867#endif
20868 };
20869 // OFM Tile 0 height
20871 {
20872#ifdef __cplusplus
20873 private:
20874#endif
20875 uint32_t opcode : 10; // opcode
20876 uint32_t reserved0 : 4;
20877 uint32_t control : 2; // control
20878 uint32_t height_m1 : 16; // OFM Tile 0 height
20879#ifdef __cplusplus
20880 public:
20881 npu_set_ofm_height0_m1_t(uint32_t _height_m1) :
20882 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1)), reserved0(0),
20883 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
20884 {
20885 }
20887 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1)), reserved0(0),
20888 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
20889 {
20890 }
20891 CONSTEXPR bool valid() const
20892 {
20893 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1) &&
20894 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20895 }
20896 CONSTEXPR void init()
20897 {
20898 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1);
20899 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20900 }
20901 operator uint32_t()
20902 {
20903 uint32_t word;
20904 std::memcpy(&word, this, sizeof(word));
20905 return word;
20906 }
20907 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20908 {
20909 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20910 }
20911 CONSTEXPR npu_set_ofm_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20912 {
20913 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20914 return *this;
20915 }
20916 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20917 {
20918 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20919 }
20920 CONSTEXPR npu_set_ofm_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20921 {
20922 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20923 return *this;
20924 }
20925 CONSTEXPR uint32_t get_height_m1() const
20926 {
20927 return static_cast<uint32_t>(height_m1);
20928 }
20929 CONSTEXPR npu_set_ofm_height0_m1_t &set_height_m1(uint32_t value)
20930 {
20931 height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
20932 return *this;
20933 }
20934#ifdef NPU_DISASSEMBLE
20935 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
20936 {
20937 fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
20938 }
20939#endif
20940#endif
20941 };
20942 // OFM Tile 1 height
20944 {
20945#ifdef __cplusplus
20946 private:
20947#endif
20948 uint32_t opcode : 10; // opcode
20949 uint32_t reserved0 : 4;
20950 uint32_t control : 2; // control
20951 uint32_t height_m1 : 16; // OFM Tile 1 height
20952#ifdef __cplusplus
20953 public:
20954 npu_set_ofm_height1_m1_t(uint32_t _height_m1) :
20955 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1)), reserved0(0),
20956 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
20957 {
20958 }
20960 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1)), reserved0(0),
20961 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
20962 {
20963 }
20964 CONSTEXPR bool valid() const
20965 {
20966 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1) &&
20967 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20968 }
20969 CONSTEXPR void init()
20970 {
20971 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1);
20972 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20973 }
20974 operator uint32_t()
20975 {
20976 uint32_t word;
20977 std::memcpy(&word, this, sizeof(word));
20978 return word;
20979 }
20980 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
20981 {
20982 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
20983 }
20984 CONSTEXPR npu_set_ofm_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
20985 {
20986 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
20987 return *this;
20988 }
20989 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
20990 {
20991 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
20992 }
20993 CONSTEXPR npu_set_ofm_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
20994 {
20995 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
20996 return *this;
20997 }
20998 CONSTEXPR uint32_t get_height_m1() const
20999 {
21000 return static_cast<uint32_t>(height_m1);
21001 }
21002 CONSTEXPR npu_set_ofm_height1_m1_t &set_height_m1(uint32_t value)
21003 {
21004 height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
21005 return *this;
21006 }
21007#ifdef NPU_DISASSEMBLE
21008 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21009 {
21010 fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
21011 }
21012#endif
21013#endif
21014 };
21015 // Index n for OFM access
21017 {
21018#ifdef __cplusplus
21019 private:
21020#endif
21021 uint32_t opcode : 10; // opcode
21022 uint32_t reserved0 : 4;
21023 uint32_t control : 2; // control
21024 uint32_t region : 3; // Index n for OFM access
21025 uint32_t reserved1 : 13;
21026#ifdef __cplusplus
21027 public:
21028 npu_set_ofm_region_t(uint32_t _region) :
21029 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION)), reserved0(0),
21030 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
21031 reserved1(0)
21032 {
21033 }
21035 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION)), reserved0(0),
21036 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
21037 {
21038 }
21039 CONSTEXPR bool valid() const
21040 {
21041 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION) &&
21042 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21043 }
21044 CONSTEXPR void init()
21045 {
21046 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION);
21047 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21048 }
21049 operator uint32_t()
21050 {
21051 uint32_t word;
21052 std::memcpy(&word, this, sizeof(word));
21053 return word;
21054 }
21055 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21056 {
21057 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21058 }
21059 CONSTEXPR npu_set_ofm_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21060 {
21061 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21062 return *this;
21063 }
21064 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21065 {
21066 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21067 }
21068 CONSTEXPR npu_set_ofm_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21069 {
21070 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21071 return *this;
21072 }
21073 CONSTEXPR uint32_t get_region() const
21074 {
21075 return static_cast<uint32_t>(region);
21076 }
21077 CONSTEXPR npu_set_ofm_region_t &set_region(uint32_t value)
21078 {
21079 region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
21080 return *this;
21081 }
21082#ifdef NPU_DISASSEMBLE
21083 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21084 {
21085 fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
21086 }
21087#endif
21088#endif
21089 };
21090 // Kernel width
21092 {
21093#ifdef __cplusplus
21094 private:
21095#endif
21096 uint32_t opcode : 10; // opcode
21097 uint32_t reserved0 : 4;
21098 uint32_t control : 2; // control
21099 uint32_t width_m1 : 16; // Kernel width
21100#ifdef __cplusplus
21101 public:
21102 npu_set_kernel_width_m1_t(uint32_t _width_m1) :
21103 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1)), reserved0(0),
21104 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
21105 {
21106 }
21108 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1)), reserved0(0),
21109 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0)
21110 {
21111 }
21112 CONSTEXPR bool valid() const
21113 {
21114 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1) &&
21115 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21116 }
21117 CONSTEXPR void init()
21118 {
21119 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1);
21120 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21121 }
21122 operator uint32_t()
21123 {
21124 uint32_t word;
21125 std::memcpy(&word, this, sizeof(word));
21126 return word;
21127 }
21128 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21129 {
21130 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21131 }
21132 CONSTEXPR npu_set_kernel_width_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21133 {
21134 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21135 return *this;
21136 }
21137 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21138 {
21139 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21140 }
21141 CONSTEXPR npu_set_kernel_width_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21142 {
21143 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21144 return *this;
21145 }
21146 CONSTEXPR uint32_t get_width_m1() const
21147 {
21148 return static_cast<uint32_t>(width_m1);
21149 }
21150 CONSTEXPR npu_set_kernel_width_m1_t &set_width_m1(uint32_t value)
21151 {
21152 width_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
21153 return *this;
21154 }
21155#ifdef NPU_DISASSEMBLE
21156 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21157 {
21158 fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
21159 }
21160#endif
21161#endif
21162 };
21163 // Kernel height
21165 {
21166#ifdef __cplusplus
21167 private:
21168#endif
21169 uint32_t opcode : 10; // opcode
21170 uint32_t reserved0 : 4;
21171 uint32_t control : 2; // control
21172 uint32_t height_m1 : 16; // Kernel height
21173#ifdef __cplusplus
21174 public:
21175 npu_set_kernel_height_m1_t(uint32_t _height_m1) :
21176 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1)), reserved0(0),
21177 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
21178 {
21179 }
21181 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1)), reserved0(0),
21182 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
21183 {
21184 }
21185 CONSTEXPR bool valid() const
21186 {
21187 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1) &&
21188 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21189 }
21190 CONSTEXPR void init()
21191 {
21192 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1);
21193 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21194 }
21195 operator uint32_t()
21196 {
21197 uint32_t word;
21198 std::memcpy(&word, this, sizeof(word));
21199 return word;
21200 }
21201 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21202 {
21203 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21204 }
21205 CONSTEXPR npu_set_kernel_height_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21206 {
21207 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21208 return *this;
21209 }
21210 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21211 {
21212 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21213 }
21214 CONSTEXPR npu_set_kernel_height_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21215 {
21216 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21217 return *this;
21218 }
21219 CONSTEXPR uint32_t get_height_m1() const
21220 {
21221 return static_cast<uint32_t>(height_m1);
21222 }
21223 CONSTEXPR npu_set_kernel_height_m1_t &set_height_m1(uint32_t value)
21224 {
21225 height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
21226 return *this;
21227 }
21228#ifdef NPU_DISASSEMBLE
21229 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21230 {
21231 fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
21232 }
21233#endif
21234#endif
21235 };
21236 // Kernel stride
21238 {
21239#ifdef __cplusplus
21240 private:
21241#endif
21242 uint32_t opcode : 10; // opcode
21243 uint32_t reserved0 : 4;
21244 uint32_t control : 2; // control
21245 uint32_t stride_x_lsb : 1; // Stride x LSB. (kernel_x_stride - 1)[0]
21246 uint32_t stride_y_lsb : 1; // Stride y LSB. (kernel_y_stride - 1)[0]
21247 uint32_t weight_order : 1; // Weight ordering mode
21248 uint32_t dilation_x : 1; // Kernel x dilation
21249 uint32_t dilation_y : 1; // Kernel y dilation
21250 uint32_t decomposition : 1; // Kernel decomposition
21251 uint32_t stride_x_msb : 1; // Stride x MSB. (kernel_x_stride - 1) >> 1
21252 uint32_t reserved1 : 2;
21253 uint32_t stride_y_msb : 1; // Stride y MSB. (kernel_y_stride - 1) >> 1
21254 uint32_t reserved2 : 6;
21255#ifdef __cplusplus
21256 public:
21257 npu_set_kernel_stride_t(uint32_t _stride_x_lsb,
21258 uint32_t _stride_y_lsb,
21259 NPU_NAMESPACE::weight_order _weight_order,
21260 NPU_NAMESPACE::kernel_dilation _dilation_x,
21261 NPU_NAMESPACE::kernel_dilation _dilation_y,
21262 NPU_NAMESPACE::kernel_decomposition _decomposition,
21263 uint32_t _stride_x_msb,
21264 uint32_t _stride_y_msb) :
21265 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE)),
21266 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21267 stride_x_lsb(_stride_x_lsb & ((1U << 1) - 1)), stride_y_lsb(_stride_y_lsb & ((1U << 1) - 1)),
21268 weight_order(static_cast<uint8_t>(_weight_order) & ((1U << 1) - 1)),
21269 dilation_x(static_cast<uint8_t>(_dilation_x) & ((1U << 1) - 1)),
21270 dilation_y(static_cast<uint8_t>(_dilation_y) & ((1U << 1) - 1)),
21271 decomposition(static_cast<uint8_t>(_decomposition) & ((1U << 1) - 1)),
21272 stride_x_msb(_stride_x_msb & ((1U << 1) - 1)), reserved1(0), stride_y_msb(_stride_y_msb & ((1U << 1) - 1)),
21273 reserved2(0)
21274 {
21275 }
21277 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE)), reserved0(0),
21278 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), stride_x_lsb(0), stride_y_lsb(0),
21279 weight_order(0), dilation_x(0), dilation_y(0), decomposition(0), stride_x_msb(0), reserved1(0),
21280 stride_y_msb(0), reserved2(0)
21281 {
21282 }
21283 CONSTEXPR bool valid() const
21284 {
21285 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE) &&
21286 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21287 }
21288 CONSTEXPR void init()
21289 {
21290 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE);
21291 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21292 }
21293 operator uint32_t()
21294 {
21295 uint32_t word;
21296 std::memcpy(&word, this, sizeof(word));
21297 return word;
21298 }
21299 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21300 {
21301 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21302 }
21303 CONSTEXPR npu_set_kernel_stride_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21304 {
21305 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21306 return *this;
21307 }
21308 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21309 {
21310 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21311 }
21312 CONSTEXPR npu_set_kernel_stride_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21313 {
21314 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21315 return *this;
21316 }
21317 CONSTEXPR uint32_t get_stride_x_lsb() const
21318 {
21319 return static_cast<uint32_t>(stride_x_lsb);
21320 }
21321 CONSTEXPR npu_set_kernel_stride_t &set_stride_x_lsb(uint32_t value)
21322 {
21323 stride_x_lsb = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21324 return *this;
21325 }
21326 CONSTEXPR uint32_t get_stride_y_lsb() const
21327 {
21328 return static_cast<uint32_t>(stride_y_lsb);
21329 }
21330 CONSTEXPR npu_set_kernel_stride_t &set_stride_y_lsb(uint32_t value)
21331 {
21332 stride_y_lsb = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21333 return *this;
21334 }
21335 CONSTEXPR NPU_NAMESPACE::weight_order get_weight_order() const
21336 {
21337 return static_cast<NPU_NAMESPACE::weight_order>(weight_order);
21338 }
21339 CONSTEXPR npu_set_kernel_stride_t &set_weight_order(NPU_NAMESPACE::weight_order value)
21340 {
21341 weight_order = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21342 return *this;
21343 }
21344 CONSTEXPR NPU_NAMESPACE::kernel_dilation get_dilation_x() const
21345 {
21346 return static_cast<NPU_NAMESPACE::kernel_dilation>(dilation_x);
21347 }
21348 CONSTEXPR npu_set_kernel_stride_t &set_dilation_x(NPU_NAMESPACE::kernel_dilation value)
21349 {
21350 dilation_x = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21351 return *this;
21352 }
21353 CONSTEXPR NPU_NAMESPACE::kernel_dilation get_dilation_y() const
21354 {
21355 return static_cast<NPU_NAMESPACE::kernel_dilation>(dilation_y);
21356 }
21357 CONSTEXPR npu_set_kernel_stride_t &set_dilation_y(NPU_NAMESPACE::kernel_dilation value)
21358 {
21359 dilation_y = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21360 return *this;
21361 }
21362 CONSTEXPR NPU_NAMESPACE::kernel_decomposition get_decomposition() const
21363 {
21364 return static_cast<NPU_NAMESPACE::kernel_decomposition>(decomposition);
21365 }
21366 CONSTEXPR npu_set_kernel_stride_t &set_decomposition(NPU_NAMESPACE::kernel_decomposition value)
21367 {
21368 decomposition = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21369 return *this;
21370 }
21371 CONSTEXPR uint32_t get_stride_x_msb() const
21372 {
21373 return static_cast<uint32_t>(stride_x_msb);
21374 }
21375 CONSTEXPR npu_set_kernel_stride_t &set_stride_x_msb(uint32_t value)
21376 {
21377 stride_x_msb = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21378 return *this;
21379 }
21380 CONSTEXPR uint32_t get_stride_y_msb() const
21381 {
21382 return static_cast<uint32_t>(stride_y_msb);
21383 }
21384 CONSTEXPR npu_set_kernel_stride_t &set_stride_y_msb(uint32_t value)
21385 {
21386 stride_y_msb = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21387 return *this;
21388 }
21389#ifdef NPU_DISASSEMBLE
21390 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21391 {
21392 fields.push_back(std::make_pair<std::string, std::string>("stride_x_lsb", std::to_string(stride_x_lsb)));
21393 fields.push_back(std::make_pair<std::string, std::string>("stride_y_lsb", std::to_string(stride_y_lsb)));
21394 fields.push_back(std::make_pair<std::string, std::string>(
21395 "weight_order",
21396 (weight_order < (sizeof(weight_order_str) / sizeof(weight_order_str[0])) ?
21397 weight_order_str[weight_order] :
21398 "****")));
21399 fields.push_back(std::make_pair<std::string, std::string>(
21400 "dilation_x",
21401 (dilation_x < (sizeof(kernel_dilation_str) / sizeof(kernel_dilation_str[0])) ?
21402 kernel_dilation_str[dilation_x] :
21403 "****")));
21404 fields.push_back(std::make_pair<std::string, std::string>(
21405 "dilation_y",
21406 (dilation_y < (sizeof(kernel_dilation_str) / sizeof(kernel_dilation_str[0])) ?
21407 kernel_dilation_str[dilation_y] :
21408 "****")));
21409 fields.push_back(std::make_pair<std::string, std::string>(
21410 "decomposition",
21411 (decomposition < (sizeof(kernel_decomposition_str) / sizeof(kernel_decomposition_str[0])) ?
21412 kernel_decomposition_str[decomposition] :
21413 "****")));
21414 fields.push_back(std::make_pair<std::string, std::string>("stride_x_msb", std::to_string(stride_x_msb)));
21415 fields.push_back(std::make_pair<std::string, std::string>("stride_y_msb", std::to_string(stride_y_msb)));
21416 }
21417#endif
21418#endif
21419 };
21420 // Multi-core parallel mode
21422 {
21423#ifdef __cplusplus
21424 private:
21425#endif
21426 uint32_t opcode : 10; // opcode
21427 uint32_t reserved0 : 4;
21428 uint32_t control : 2; // control
21429 uint32_t parallel_mode : 1; // Multi-core parallel mode
21430 uint32_t reserved1 : 15;
21431#ifdef __cplusplus
21432 public:
21433 npu_set_parallel_mode_t(NPU_NAMESPACE::parallel_mode _parallel_mode) :
21434 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE)), reserved0(0),
21435 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21436 parallel_mode(static_cast<uint8_t>(_parallel_mode) & ((1U << 1) - 1)), reserved1(0)
21437 {
21438 }
21440 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE)), reserved0(0),
21441 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), parallel_mode(0), reserved1(0)
21442 {
21443 }
21444 CONSTEXPR bool valid() const
21445 {
21446 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE) &&
21447 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21448 }
21449 CONSTEXPR void init()
21450 {
21451 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE);
21452 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21453 }
21454 operator uint32_t()
21455 {
21456 uint32_t word;
21457 std::memcpy(&word, this, sizeof(word));
21458 return word;
21459 }
21460 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21461 {
21462 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21463 }
21464 CONSTEXPR npu_set_parallel_mode_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21465 {
21466 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21467 return *this;
21468 }
21469 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21470 {
21471 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21472 }
21473 CONSTEXPR npu_set_parallel_mode_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21474 {
21475 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21476 return *this;
21477 }
21478 CONSTEXPR NPU_NAMESPACE::parallel_mode get_parallel_mode() const
21479 {
21480 return static_cast<NPU_NAMESPACE::parallel_mode>(parallel_mode);
21481 }
21482 CONSTEXPR npu_set_parallel_mode_t &set_parallel_mode(NPU_NAMESPACE::parallel_mode value)
21483 {
21484 parallel_mode = static_cast<uint8_t>(value) & ((1U << 1) - 1);
21485 return *this;
21486 }
21487#ifdef NPU_DISASSEMBLE
21488 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21489 {
21490 fields.push_back(std::make_pair<std::string, std::string>(
21491 "parallel_mode",
21492 (parallel_mode < (sizeof(parallel_mode_str) / sizeof(parallel_mode_str[0])) ?
21493 parallel_mode_str[parallel_mode] :
21494 "****")));
21495 }
21496#endif
21497#endif
21498 };
21499 // Accumulator format
21501 {
21502#ifdef __cplusplus
21503 private:
21504#endif
21505 uint32_t opcode : 10; // opcode
21506 uint32_t reserved0 : 4;
21507 uint32_t control : 2; // control
21508 uint32_t acc_format : 2; // Accumulator format
21509 uint32_t reserved1 : 14;
21510#ifdef __cplusplus
21511 public:
21512 npu_set_acc_format_t(NPU_NAMESPACE::acc_format _acc_format) :
21513 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT)), reserved0(0),
21514 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21515 acc_format(static_cast<uint8_t>(_acc_format) & ((1U << 2) - 1)), reserved1(0)
21516 {
21517 }
21519 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT)), reserved0(0),
21520 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), acc_format(0), reserved1(0)
21521 {
21522 }
21523 CONSTEXPR bool valid() const
21524 {
21525 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT) &&
21526 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21527 }
21528 CONSTEXPR void init()
21529 {
21530 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT);
21531 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21532 }
21533 operator uint32_t()
21534 {
21535 uint32_t word;
21536 std::memcpy(&word, this, sizeof(word));
21537 return word;
21538 }
21539 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21540 {
21541 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21542 }
21543 CONSTEXPR npu_set_acc_format_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21544 {
21545 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21546 return *this;
21547 }
21548 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21549 {
21550 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21551 }
21552 CONSTEXPR npu_set_acc_format_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21553 {
21554 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21555 return *this;
21556 }
21557 CONSTEXPR NPU_NAMESPACE::acc_format get_acc_format() const
21558 {
21559 return static_cast<NPU_NAMESPACE::acc_format>(acc_format);
21560 }
21561 CONSTEXPR npu_set_acc_format_t &set_acc_format(NPU_NAMESPACE::acc_format value)
21562 {
21563 acc_format = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21564 return *this;
21565 }
21566#ifdef NPU_DISASSEMBLE
21567 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21568 {
21569 fields.push_back(std::make_pair<std::string, std::string>(
21570 "acc_format",
21571 (acc_format < (sizeof(acc_format_str) / sizeof(acc_format_str[0])) ? acc_format_str[acc_format] :
21572 "****")));
21573 }
21574#endif
21575#endif
21576 };
21577 // Activation function and clip range
21579 {
21580#ifdef __cplusplus
21581 private:
21582#endif
21583 uint32_t opcode : 10; // opcode
21584 uint32_t reserved0 : 4;
21585 uint32_t control : 2; // control
21586 uint32_t activation_function : 5; // Activation function (before table lookup)
21587 uint32_t reserved1 : 7;
21588 uint32_t activation_clip_range : 3; // Activation clip range. This must be set to 0 if table lookup is not used
21589 uint32_t reserved2 : 1;
21590#ifdef __cplusplus
21591 public:
21592 npu_set_activation_t(NPU_NAMESPACE::activation_function _activation_function,
21593 NPU_NAMESPACE::activation_clip_range _activation_clip_range) :
21594 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION)),
21595 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21596 activation_function(static_cast<uint8_t>(_activation_function) & ((1U << 5) - 1)), reserved1(0),
21597 activation_clip_range(static_cast<uint8_t>(_activation_clip_range) & ((1U << 3) - 1)), reserved2(0)
21598 {
21599 }
21601 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION)), reserved0(0),
21602 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_function(0), reserved1(0),
21603 activation_clip_range(0), reserved2(0)
21604 {
21605 }
21606 CONSTEXPR bool valid() const
21607 {
21608 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION) &&
21609 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21610 }
21611 CONSTEXPR void init()
21612 {
21613 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION);
21614 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21615 }
21616 operator uint32_t()
21617 {
21618 uint32_t word;
21619 std::memcpy(&word, this, sizeof(word));
21620 return word;
21621 }
21622 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21623 {
21624 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21625 }
21626 CONSTEXPR npu_set_activation_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21627 {
21628 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21629 return *this;
21630 }
21631 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21632 {
21633 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21634 }
21635 CONSTEXPR npu_set_activation_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21636 {
21637 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21638 return *this;
21639 }
21640 CONSTEXPR NPU_NAMESPACE::activation_function get_activation_function() const
21641 {
21642 return static_cast<NPU_NAMESPACE::activation_function>(activation_function);
21643 }
21644 CONSTEXPR npu_set_activation_t &set_activation_function(NPU_NAMESPACE::activation_function value)
21645 {
21646 activation_function = static_cast<uint8_t>(value) & ((1U << 5) - 1);
21647 return *this;
21648 }
21649 CONSTEXPR NPU_NAMESPACE::activation_clip_range get_activation_clip_range() const
21650 {
21651 return static_cast<NPU_NAMESPACE::activation_clip_range>(activation_clip_range);
21652 }
21653 CONSTEXPR npu_set_activation_t &set_activation_clip_range(NPU_NAMESPACE::activation_clip_range value)
21654 {
21655 activation_clip_range = static_cast<uint8_t>(value) & ((1U << 3) - 1);
21656 return *this;
21657 }
21658#ifdef NPU_DISASSEMBLE
21659 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21660 {
21661 fields.push_back(std::make_pair<std::string, std::string>(
21662 "activation_function",
21663 (activation_function < (sizeof(activation_function_str) / sizeof(activation_function_str[0])) ?
21664 activation_function_str[activation_function] :
21665 "****")));
21666 fields.push_back(std::make_pair<std::string, std::string>(
21667 "activation_clip_range",
21668 (activation_clip_range < (sizeof(activation_clip_range_str) / sizeof(activation_clip_range_str[0])) ?
21669 activation_clip_range_str[activation_clip_range] :
21670 "****")));
21671 }
21672#endif
21673#endif
21674 };
21675 // Lower bound clip
21677 {
21678#ifdef __cplusplus
21679 private:
21680#endif
21681 uint32_t opcode : 10; // opcode
21682 uint32_t reserved0 : 4;
21683 uint32_t control : 2; // control
21684 uint32_t clip_boundary : 16; // Clip boundary for OFM activations
21685#ifdef __cplusplus
21686 public:
21687 npu_set_activation_min_t(uint32_t _clip_boundary) :
21688 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN)), reserved0(0),
21689 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21690 clip_boundary(_clip_boundary & ((1U << 16) - 1))
21691 {
21692 }
21694 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN)), reserved0(0),
21695 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), clip_boundary(0)
21696 {
21697 }
21698 CONSTEXPR bool valid() const
21699 {
21700 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN) &&
21701 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21702 }
21703 CONSTEXPR void init()
21704 {
21705 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN);
21706 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21707 }
21708 operator uint32_t()
21709 {
21710 uint32_t word;
21711 std::memcpy(&word, this, sizeof(word));
21712 return word;
21713 }
21714 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21715 {
21716 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21717 }
21718 CONSTEXPR npu_set_activation_min_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21719 {
21720 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21721 return *this;
21722 }
21723 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21724 {
21725 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21726 }
21727 CONSTEXPR npu_set_activation_min_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21728 {
21729 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21730 return *this;
21731 }
21732 CONSTEXPR uint32_t get_clip_boundary() const
21733 {
21734 return static_cast<uint32_t>(clip_boundary);
21735 }
21736 CONSTEXPR npu_set_activation_min_t &set_clip_boundary(uint32_t value)
21737 {
21738 clip_boundary = static_cast<uint16_t>(value) & ((1U << 16) - 1);
21739 return *this;
21740 }
21741#ifdef NPU_DISASSEMBLE
21742 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21743 {
21744 fields.push_back(std::make_pair<std::string, std::string>("clip_boundary", std::to_string(clip_boundary)));
21745 }
21746#endif
21747#endif
21748 };
21749 // Upper bound clip
21751 {
21752#ifdef __cplusplus
21753 private:
21754#endif
21755 uint32_t opcode : 10; // opcode
21756 uint32_t reserved0 : 4;
21757 uint32_t control : 2; // control
21758 uint32_t clip_boundary : 16; // Clip boundary for OFM activations
21759#ifdef __cplusplus
21760 public:
21761 npu_set_activation_max_t(uint32_t _clip_boundary) :
21762 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX)), reserved0(0),
21763 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
21764 clip_boundary(_clip_boundary & ((1U << 16) - 1))
21765 {
21766 }
21768 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX)), reserved0(0),
21769 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), clip_boundary(0)
21770 {
21771 }
21772 CONSTEXPR bool valid() const
21773 {
21774 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX) &&
21775 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21776 }
21777 CONSTEXPR void init()
21778 {
21779 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX);
21780 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21781 }
21782 operator uint32_t()
21783 {
21784 uint32_t word;
21785 std::memcpy(&word, this, sizeof(word));
21786 return word;
21787 }
21788 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21789 {
21790 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21791 }
21792 CONSTEXPR npu_set_activation_max_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21793 {
21794 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21795 return *this;
21796 }
21797 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21798 {
21799 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21800 }
21801 CONSTEXPR npu_set_activation_max_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21802 {
21803 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21804 return *this;
21805 }
21806 CONSTEXPR uint32_t get_clip_boundary() const
21807 {
21808 return static_cast<uint32_t>(clip_boundary);
21809 }
21810 CONSTEXPR npu_set_activation_max_t &set_clip_boundary(uint32_t value)
21811 {
21812 clip_boundary = static_cast<uint16_t>(value) & ((1U << 16) - 1);
21813 return *this;
21814 }
21815#ifdef NPU_DISASSEMBLE
21816 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21817 {
21818 fields.push_back(std::make_pair<std::string, std::string>("clip_boundary", std::to_string(clip_boundary)));
21819 }
21820#endif
21821#endif
21822 };
21823 // Index n for weight stream access
21825 {
21826#ifdef __cplusplus
21827 private:
21828#endif
21829 uint32_t opcode : 10; // opcode
21830 uint32_t reserved0 : 4;
21831 uint32_t control : 2; // control
21832 uint32_t region : 3; // Index n for weight stream access
21833 uint32_t reserved1 : 13;
21834#ifdef __cplusplus
21835 public:
21836 npu_set_weight_region_t(uint32_t _region) :
21837 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION)), reserved0(0),
21838 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
21839 reserved1(0)
21840 {
21841 }
21843 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION)), reserved0(0),
21844 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
21845 {
21846 }
21847 CONSTEXPR bool valid() const
21848 {
21849 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION) &&
21850 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21851 }
21852 CONSTEXPR void init()
21853 {
21854 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION);
21855 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21856 }
21857 operator uint32_t()
21858 {
21859 uint32_t word;
21860 std::memcpy(&word, this, sizeof(word));
21861 return word;
21862 }
21863 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21864 {
21865 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21866 }
21867 CONSTEXPR npu_set_weight_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21868 {
21869 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21870 return *this;
21871 }
21872 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21873 {
21874 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21875 }
21876 CONSTEXPR npu_set_weight_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21877 {
21878 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21879 return *this;
21880 }
21881 CONSTEXPR uint32_t get_region() const
21882 {
21883 return static_cast<uint32_t>(region);
21884 }
21885 CONSTEXPR npu_set_weight_region_t &set_region(uint32_t value)
21886 {
21887 region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
21888 return *this;
21889 }
21890#ifdef NPU_DISASSEMBLE
21891 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21892 {
21893 fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
21894 }
21895#endif
21896#endif
21897 };
21898 // Index n for scale stream access
21900 {
21901#ifdef __cplusplus
21902 private:
21903#endif
21904 uint32_t opcode : 10; // opcode
21905 uint32_t reserved0 : 4;
21906 uint32_t control : 2; // control
21907 uint32_t region : 3; // Index n for scale stream access
21908 uint32_t reserved1 : 13;
21909#ifdef __cplusplus
21910 public:
21911 npu_set_scale_region_t(uint32_t _region) :
21912 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION)), reserved0(0),
21913 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
21914 reserved1(0)
21915 {
21916 }
21918 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION)), reserved0(0),
21919 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
21920 {
21921 }
21922 CONSTEXPR bool valid() const
21923 {
21924 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION) &&
21925 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21926 }
21927 CONSTEXPR void init()
21928 {
21929 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION);
21930 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21931 }
21932 operator uint32_t()
21933 {
21934 uint32_t word;
21935 std::memcpy(&word, this, sizeof(word));
21936 return word;
21937 }
21938 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
21939 {
21940 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
21941 }
21942 CONSTEXPR npu_set_scale_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
21943 {
21944 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
21945 return *this;
21946 }
21947 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
21948 {
21949 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
21950 }
21951 CONSTEXPR npu_set_scale_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
21952 {
21953 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
21954 return *this;
21955 }
21956 CONSTEXPR uint32_t get_region() const
21957 {
21958 return static_cast<uint32_t>(region);
21959 }
21960 CONSTEXPR npu_set_scale_region_t &set_region(uint32_t value)
21961 {
21962 region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
21963 return *this;
21964 }
21965#ifdef NPU_DISASSEMBLE
21966 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
21967 {
21968 fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
21969 }
21970#endif
21971#endif
21972 };
21973 // Start of ACC0,ACC1 buffers
21974 struct npu_set_ab_start_t
21975 {
21976#ifdef __cplusplus
21977 private:
21978#endif
21979 uint32_t opcode : 10; // opcode
21980 uint32_t reserved0 : 4;
21981 uint32_t control : 2; // control
21982 uint32_t ab_start : 6; // Start of ACC0,ACC1 buffers in the SHRAM in KB units. Multiple of 2
21983 uint32_t reserved1 : 10;
21984#ifdef __cplusplus
21985 public:
21986 npu_set_ab_start_t(uint32_t _ab_start) :
21987 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START)), reserved0(0),
21988 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ab_start(_ab_start & ((1U << 6) - 1)),
21989 reserved1(0)
21990 {
21991 }
21993 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START)), reserved0(0),
21994 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ab_start(0), reserved1(0)
21995 {
21996 }
21997 CONSTEXPR bool valid() const
21998 {
21999 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START) &&
22000 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22001 }
22002 CONSTEXPR void init()
22003 {
22004 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START);
22005 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22006 }
22007 operator uint32_t()
22008 {
22009 uint32_t word;
22010 std::memcpy(&word, this, sizeof(word));
22011 return word;
22012 }
22013 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22014 {
22015 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22016 }
22017 CONSTEXPR npu_set_ab_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22018 {
22019 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22020 return *this;
22021 }
22022 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22023 {
22024 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22025 }
22026 CONSTEXPR npu_set_ab_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22027 {
22028 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22029 return *this;
22030 }
22031 CONSTEXPR uint32_t get_ab_start() const
22032 {
22033 return static_cast<uint32_t>(ab_start);
22034 }
22035 CONSTEXPR npu_set_ab_start_t &set_ab_start(uint32_t value)
22036 {
22037 ab_start = static_cast<uint8_t>(value) & ((1U << 6) - 1);
22038 return *this;
22039 }
22040#ifdef NPU_DISASSEMBLE
22041 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22042 {
22043 fields.push_back(std::make_pair<std::string, std::string>("ab_start", std::to_string(ab_start)));
22044 }
22045#endif
22046#endif
22047 };
22048 // Block number of blocks dependency
22049 struct npu_set_blockdep_t
22050 {
22051#ifdef __cplusplus
22052 private:
22053#endif
22054 uint32_t opcode : 10; // opcode
22055 uint32_t reserved0 : 4;
22056 uint32_t control : 2; // control
22057 uint32_t blockdep : 2; // Block number of blocks dependency between kernel operations
22058 uint32_t reserved1 : 14;
22059#ifdef __cplusplus
22060 public:
22061 npu_set_blockdep_t(uint32_t _blockdep) :
22062 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP)), reserved0(0),
22063 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), blockdep(_blockdep & ((1U << 2) - 1)),
22064 reserved1(0)
22065 {
22066 }
22068 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP)), reserved0(0),
22069 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), blockdep(0), reserved1(0)
22070 {
22071 }
22072 CONSTEXPR bool valid() const
22073 {
22074 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP) &&
22075 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22076 }
22077 CONSTEXPR void init()
22078 {
22079 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP);
22080 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22081 }
22082 operator uint32_t()
22083 {
22084 uint32_t word;
22085 std::memcpy(&word, this, sizeof(word));
22086 return word;
22087 }
22088 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22089 {
22090 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22091 }
22092 CONSTEXPR npu_set_blockdep_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22093 {
22094 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22095 return *this;
22096 }
22097 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22098 {
22099 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22100 }
22101 CONSTEXPR npu_set_blockdep_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22102 {
22103 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22104 return *this;
22105 }
22106 CONSTEXPR uint32_t get_blockdep() const
22107 {
22108 return static_cast<uint32_t>(blockdep);
22109 }
22110 CONSTEXPR npu_set_blockdep_t &set_blockdep(uint32_t value)
22111 {
22112 blockdep = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22113 return *this;
22114 }
22115#ifdef NPU_DISASSEMBLE
22116 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22117 {
22118 fields.push_back(std::make_pair<std::string, std::string>("blockdep", std::to_string(blockdep)));
22119 }
22120#endif
22121#endif
22122 };
22123 // DMA0 source region
22125 {
22126#ifdef __cplusplus
22127 private:
22128#endif
22129 uint32_t opcode : 10; // opcode
22130 uint32_t reserved0 : 4;
22131 uint32_t control : 2; // control
22132 uint32_t region : 3; // Region number
22133 uint32_t reserved1 : 5;
22134 uint32_t region_mode : 1; // Region mode
22135 uint32_t stride_mode : 2; // Stride mode
22136 uint32_t reserved2 : 5;
22137#ifdef __cplusplus
22138 public:
22139 npu_set_dma0_src_region_t(uint32_t _region,
22140 NPU_NAMESPACE::dma_region_mode _region_mode,
22141 NPU_NAMESPACE::dma_stride_mode _stride_mode) :
22142 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION)),
22143 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
22144 region(_region & ((1U << 3) - 1)), reserved1(0),
22145 region_mode(static_cast<uint8_t>(_region_mode) & ((1U << 1) - 1)),
22146 stride_mode(static_cast<uint8_t>(_stride_mode) & ((1U << 2) - 1)), reserved2(0)
22147 {
22148 }
22150 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION)), reserved0(0),
22151 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), region_mode(0),
22152 stride_mode(0), reserved2(0)
22153 {
22154 }
22155 CONSTEXPR bool valid() const
22156 {
22157 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION) &&
22158 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22159 }
22160 CONSTEXPR void init()
22161 {
22162 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION);
22163 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22164 }
22165 operator uint32_t()
22166 {
22167 uint32_t word;
22168 std::memcpy(&word, this, sizeof(word));
22169 return word;
22170 }
22171 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22172 {
22173 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22174 }
22175 CONSTEXPR npu_set_dma0_src_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22176 {
22177 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22178 return *this;
22179 }
22180 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22181 {
22182 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22183 }
22184 CONSTEXPR npu_set_dma0_src_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22185 {
22186 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22187 return *this;
22188 }
22189 CONSTEXPR uint32_t get_region() const
22190 {
22191 return static_cast<uint32_t>(region);
22192 }
22193 CONSTEXPR npu_set_dma0_src_region_t &set_region(uint32_t value)
22194 {
22195 region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
22196 return *this;
22197 }
22198 CONSTEXPR NPU_NAMESPACE::dma_region_mode get_region_mode() const
22199 {
22200 return static_cast<NPU_NAMESPACE::dma_region_mode>(region_mode);
22201 }
22202 CONSTEXPR npu_set_dma0_src_region_t &set_region_mode(NPU_NAMESPACE::dma_region_mode value)
22203 {
22204 region_mode = static_cast<uint8_t>(value) & ((1U << 1) - 1);
22205 return *this;
22206 }
22207 CONSTEXPR NPU_NAMESPACE::dma_stride_mode get_stride_mode() const
22208 {
22209 return static_cast<NPU_NAMESPACE::dma_stride_mode>(stride_mode);
22210 }
22211 CONSTEXPR npu_set_dma0_src_region_t &set_stride_mode(NPU_NAMESPACE::dma_stride_mode value)
22212 {
22213 stride_mode = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22214 return *this;
22215 }
22216#ifdef NPU_DISASSEMBLE
22217 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22218 {
22219 fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
22220 fields.push_back(std::make_pair<std::string, std::string>(
22221 "region_mode",
22222 (region_mode < (sizeof(dma_region_mode_str) / sizeof(dma_region_mode_str[0])) ?
22223 dma_region_mode_str[region_mode] :
22224 "****")));
22225 fields.push_back(std::make_pair<std::string, std::string>(
22226 "stride_mode",
22227 (stride_mode < (sizeof(dma_stride_mode_str) / sizeof(dma_stride_mode_str[0])) ?
22228 dma_stride_mode_str[stride_mode] :
22229 "****")));
22230 }
22231#endif
22232#endif
22233 };
22234 // DMA0 destination region
22236 {
22237#ifdef __cplusplus
22238 private:
22239#endif
22240 uint32_t opcode : 10; // opcode
22241 uint32_t reserved0 : 4;
22242 uint32_t control : 2; // control
22243 uint32_t region : 3; // Region number if region_mode is region_mode_external. Else core mask to write to (bit k
22244 // set for core k=0,1)
22245 uint32_t reserved1 : 5;
22246 uint32_t region_mode : 1; // Region mode
22247 uint32_t stride_mode : 2; // Stride mode
22248 uint32_t reserved2 : 5;
22249#ifdef __cplusplus
22250 public:
22251 npu_set_dma0_dst_region_t(uint32_t _region,
22252 NPU_NAMESPACE::dma_region_mode _region_mode,
22253 NPU_NAMESPACE::dma_stride_mode _stride_mode) :
22254 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION)),
22255 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
22256 region(_region & ((1U << 3) - 1)), reserved1(0),
22257 region_mode(static_cast<uint8_t>(_region_mode) & ((1U << 1) - 1)),
22258 stride_mode(static_cast<uint8_t>(_stride_mode) & ((1U << 2) - 1)), reserved2(0)
22259 {
22260 }
22262 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION)), reserved0(0),
22263 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), region_mode(0),
22264 stride_mode(0), reserved2(0)
22265 {
22266 }
22267 CONSTEXPR bool valid() const
22268 {
22269 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION) &&
22270 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22271 }
22272 CONSTEXPR void init()
22273 {
22274 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION);
22275 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22276 }
22277 operator uint32_t()
22278 {
22279 uint32_t word;
22280 std::memcpy(&word, this, sizeof(word));
22281 return word;
22282 }
22283 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22284 {
22285 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22286 }
22287 CONSTEXPR npu_set_dma0_dst_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22288 {
22289 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22290 return *this;
22291 }
22292 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22293 {
22294 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22295 }
22296 CONSTEXPR npu_set_dma0_dst_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22297 {
22298 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22299 return *this;
22300 }
22301 CONSTEXPR uint32_t get_region() const
22302 {
22303 return static_cast<uint32_t>(region);
22304 }
22305 CONSTEXPR npu_set_dma0_dst_region_t &set_region(uint32_t value)
22306 {
22307 region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
22308 return *this;
22309 }
22310 CONSTEXPR NPU_NAMESPACE::dma_region_mode get_region_mode() const
22311 {
22312 return static_cast<NPU_NAMESPACE::dma_region_mode>(region_mode);
22313 }
22314 CONSTEXPR npu_set_dma0_dst_region_t &set_region_mode(NPU_NAMESPACE::dma_region_mode value)
22315 {
22316 region_mode = static_cast<uint8_t>(value) & ((1U << 1) - 1);
22317 return *this;
22318 }
22319 CONSTEXPR NPU_NAMESPACE::dma_stride_mode get_stride_mode() const
22320 {
22321 return static_cast<NPU_NAMESPACE::dma_stride_mode>(stride_mode);
22322 }
22323 CONSTEXPR npu_set_dma0_dst_region_t &set_stride_mode(NPU_NAMESPACE::dma_stride_mode value)
22324 {
22325 stride_mode = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22326 return *this;
22327 }
22328#ifdef NPU_DISASSEMBLE
22329 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22330 {
22331 fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
22332 fields.push_back(std::make_pair<std::string, std::string>(
22333 "region_mode",
22334 (region_mode < (sizeof(dma_region_mode_str) / sizeof(dma_region_mode_str[0])) ?
22335 dma_region_mode_str[region_mode] :
22336 "****")));
22337 fields.push_back(std::make_pair<std::string, std::string>(
22338 "stride_mode",
22339 (stride_mode < (sizeof(dma_stride_mode_str) / sizeof(dma_stride_mode_str[0])) ?
22340 dma_stride_mode_str[stride_mode] :
22341 "****")));
22342 }
22343#endif
22344#endif
22345 };
22346 // Size of second dimension for 2D/3D transfers
22348 {
22349#ifdef __cplusplus
22350 private:
22351#endif
22352 uint32_t opcode : 10; // opcode
22353 uint32_t reserved0 : 4;
22354 uint32_t control : 2; // control
22355 uint32_t size : 16; // Size of second dimension for 2D/3D transfers
22356#ifdef __cplusplus
22357 public:
22358 npu_set_dma0_size0_t(uint32_t _size) :
22359 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0)), reserved0(0),
22360 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(_size & ((1U << 16) - 1))
22361 {
22362 }
22364 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0)), reserved0(0),
22365 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(0)
22366 {
22367 }
22368 CONSTEXPR bool valid() const
22369 {
22370 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0) &&
22371 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22372 }
22373 CONSTEXPR void init()
22374 {
22375 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0);
22376 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22377 }
22378 operator uint32_t()
22379 {
22380 uint32_t word;
22381 std::memcpy(&word, this, sizeof(word));
22382 return word;
22383 }
22384 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22385 {
22386 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22387 }
22388 CONSTEXPR npu_set_dma0_size0_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22389 {
22390 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22391 return *this;
22392 }
22393 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22394 {
22395 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22396 }
22397 CONSTEXPR npu_set_dma0_size0_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22398 {
22399 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22400 return *this;
22401 }
22402 CONSTEXPR uint32_t get_size() const
22403 {
22404 return static_cast<uint32_t>(size);
22405 }
22406 CONSTEXPR npu_set_dma0_size0_t &set_size(uint32_t value)
22407 {
22408 size = static_cast<uint16_t>(value) & ((1U << 16) - 1);
22409 return *this;
22410 }
22411#ifdef NPU_DISASSEMBLE
22412 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22413 {
22414 fields.push_back(std::make_pair<std::string, std::string>("size", std::to_string(size)));
22415 }
22416#endif
22417#endif
22418 };
22419 // Size of third dimension for 3D transfers
22421 {
22422#ifdef __cplusplus
22423 private:
22424#endif
22425 uint32_t opcode : 10; // opcode
22426 uint32_t reserved0 : 4;
22427 uint32_t control : 2; // control
22428 uint32_t size : 16; // Size of third dimension for 3D transfers
22429#ifdef __cplusplus
22430 public:
22431 npu_set_dma0_size1_t(uint32_t _size) :
22432 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1)), reserved0(0),
22433 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(_size & ((1U << 16) - 1))
22434 {
22435 }
22437 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1)), reserved0(0),
22438 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), size(0)
22439 {
22440 }
22441 CONSTEXPR bool valid() const
22442 {
22443 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1) &&
22444 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22445 }
22446 CONSTEXPR void init()
22447 {
22448 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1);
22449 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22450 }
22451 operator uint32_t()
22452 {
22453 uint32_t word;
22454 std::memcpy(&word, this, sizeof(word));
22455 return word;
22456 }
22457 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22458 {
22459 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22460 }
22461 CONSTEXPR npu_set_dma0_size1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22462 {
22463 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22464 return *this;
22465 }
22466 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22467 {
22468 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22469 }
22470 CONSTEXPR npu_set_dma0_size1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22471 {
22472 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22473 return *this;
22474 }
22475 CONSTEXPR uint32_t get_size() const
22476 {
22477 return static_cast<uint32_t>(size);
22478 }
22479 CONSTEXPR npu_set_dma0_size1_t &set_size(uint32_t value)
22480 {
22481 size = static_cast<uint16_t>(value) & ((1U << 16) - 1);
22482 return *this;
22483 }
22484#ifdef NPU_DISASSEMBLE
22485 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22486 {
22487 fields.push_back(std::make_pair<std::string, std::string>("size", std::to_string(size)));
22488 }
22489#endif
22490#endif
22491 };
22492 // IFM2 broadcast configuration
22494 {
22495#ifdef __cplusplus
22496 private:
22497#endif
22498 uint32_t opcode : 10; // opcode
22499 uint32_t reserved0 : 4;
22500 uint32_t control : 2; // control
22501 uint32_t
22502 broadcast_h : 1; // Broadcast H dimension (if set then any accesses to IFM2 sets y=0 and IFM2 height=1)
22503 uint32_t broadcast_w : 1; // Broadcast W dimension (if set then any accesses to IFM2 sets x=0 and IFM2 width=1)
22504 uint32_t broadcast_c : 1; // Broadcast C dimension (if set then any accesses to IFM2 sets c=0 and IFM2 depth=1)
22505 uint32_t reserved1 : 3;
22506 uint32_t operand_order : 1; // Operand order
22507 uint32_t broadcast_constant : 1; // Broadcast constant given by NPU_SET_IFM2_SCALAR and so ignore BH, BW and BC
22508 uint32_t reserved2 : 8;
22509#ifdef __cplusplus
22510 public:
22511 npu_set_ifm2_broadcast_t(NPU_NAMESPACE::broadcast_mode _broadcast_h,
22512 NPU_NAMESPACE::broadcast_mode _broadcast_w,
22513 NPU_NAMESPACE::broadcast_mode _broadcast_c,
22514 NPU_NAMESPACE::ifm2_operand_order _operand_order,
22515 NPU_NAMESPACE::broadcast_mode _broadcast_constant) :
22516 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST)),
22517 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
22518 broadcast_h(static_cast<uint8_t>(_broadcast_h) & ((1U << 1) - 1)),
22519 broadcast_w(static_cast<uint8_t>(_broadcast_w) & ((1U << 1) - 1)),
22520 broadcast_c(static_cast<uint8_t>(_broadcast_c) & ((1U << 1) - 1)), reserved1(0),
22521 operand_order(static_cast<uint8_t>(_operand_order) & ((1U << 1) - 1)),
22522 broadcast_constant(static_cast<uint8_t>(_broadcast_constant) & ((1U << 1) - 1)), reserved2(0)
22523 {
22524 }
22526 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST)), reserved0(0),
22527 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), broadcast_h(0), broadcast_w(0),
22528 broadcast_c(0), reserved1(0), operand_order(0), broadcast_constant(0), reserved2(0)
22529 {
22530 }
22531 CONSTEXPR bool valid() const
22532 {
22533 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST) &&
22534 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22535 }
22536 CONSTEXPR void init()
22537 {
22538 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST);
22539 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22540 }
22541 operator uint32_t()
22542 {
22543 uint32_t word;
22544 std::memcpy(&word, this, sizeof(word));
22545 return word;
22546 }
22547 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22548 {
22549 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22550 }
22551 CONSTEXPR npu_set_ifm2_broadcast_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22552 {
22553 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22554 return *this;
22555 }
22556 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22557 {
22558 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22559 }
22560 CONSTEXPR npu_set_ifm2_broadcast_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22561 {
22562 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22563 return *this;
22564 }
22565 CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_h() const
22566 {
22567 return static_cast<NPU_NAMESPACE::broadcast_mode>(broadcast_h);
22568 }
22569 CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_h(NPU_NAMESPACE::broadcast_mode value)
22570 {
22571 broadcast_h = static_cast<uint8_t>(value) & ((1U << 1) - 1);
22572 return *this;
22573 }
22574 CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_w() const
22575 {
22576 return static_cast<NPU_NAMESPACE::broadcast_mode>(broadcast_w);
22577 }
22578 CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_w(NPU_NAMESPACE::broadcast_mode value)
22579 {
22580 broadcast_w = static_cast<uint8_t>(value) & ((1U << 1) - 1);
22581 return *this;
22582 }
22583 CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_c() const
22584 {
22585 return static_cast<NPU_NAMESPACE::broadcast_mode>(broadcast_c);
22586 }
22587 CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_c(NPU_NAMESPACE::broadcast_mode value)
22588 {
22589 broadcast_c = static_cast<uint8_t>(value) & ((1U << 1) - 1);
22590 return *this;
22591 }
22592 CONSTEXPR NPU_NAMESPACE::ifm2_operand_order get_operand_order() const
22593 {
22594 return static_cast<NPU_NAMESPACE::ifm2_operand_order>(operand_order);
22595 }
22596 CONSTEXPR npu_set_ifm2_broadcast_t &set_operand_order(NPU_NAMESPACE::ifm2_operand_order value)
22597 {
22598 operand_order = static_cast<uint8_t>(value) & ((1U << 1) - 1);
22599 return *this;
22600 }
22601 CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_constant() const
22602 {
22603 return static_cast<NPU_NAMESPACE::broadcast_mode>(broadcast_constant);
22604 }
22605 CONSTEXPR npu_set_ifm2_broadcast_t &set_broadcast_constant(NPU_NAMESPACE::broadcast_mode value)
22606 {
22607 broadcast_constant = static_cast<uint8_t>(value) & ((1U << 1) - 1);
22608 return *this;
22609 }
22610#ifdef NPU_DISASSEMBLE
22611 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22612 {
22613 fields.push_back(std::make_pair<std::string, std::string>(
22614 "broadcast_h",
22615 (broadcast_h < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ?
22616 broadcast_mode_str[broadcast_h] :
22617 "****")));
22618 fields.push_back(std::make_pair<std::string, std::string>(
22619 "broadcast_w",
22620 (broadcast_w < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ?
22621 broadcast_mode_str[broadcast_w] :
22622 "****")));
22623 fields.push_back(std::make_pair<std::string, std::string>(
22624 "broadcast_c",
22625 (broadcast_c < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ?
22626 broadcast_mode_str[broadcast_c] :
22627 "****")));
22628 fields.push_back(std::make_pair<std::string, std::string>(
22629 "operand_order",
22630 (operand_order < (sizeof(ifm2_operand_order_str) / sizeof(ifm2_operand_order_str[0])) ?
22631 ifm2_operand_order_str[operand_order] :
22632 "****")));
22633 fields.push_back(std::make_pair<std::string, std::string>(
22634 "broadcast_constant",
22635 (broadcast_constant < (sizeof(broadcast_mode_str) / sizeof(broadcast_mode_str[0])) ?
22636 broadcast_mode_str[broadcast_constant] :
22637 "****")));
22638 }
22639#endif
22640#endif
22641 };
22642 // IFM2 scalar value
22644 {
22645#ifdef __cplusplus
22646 private:
22647#endif
22648 uint32_t opcode : 10; // opcode
22649 uint32_t reserved0 : 4;
22650 uint32_t control : 2; // control
22651 uint32_t scalar : 16; // int16 or uint16 depending on ifm2_precision.type
22652#ifdef __cplusplus
22653 public:
22654 npu_set_ifm2_scalar_t(uint32_t _scalar) :
22655 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR)), reserved0(0),
22656 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), scalar(_scalar & ((1U << 16) - 1))
22657 {
22658 }
22660 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR)), reserved0(0),
22661 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), scalar(0)
22662 {
22663 }
22664 CONSTEXPR bool valid() const
22665 {
22666 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR) &&
22667 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22668 }
22669 CONSTEXPR void init()
22670 {
22671 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR);
22672 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22673 }
22674 operator uint32_t()
22675 {
22676 uint32_t word;
22677 std::memcpy(&word, this, sizeof(word));
22678 return word;
22679 }
22680 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22681 {
22682 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22683 }
22684 CONSTEXPR npu_set_ifm2_scalar_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22685 {
22686 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22687 return *this;
22688 }
22689 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22690 {
22691 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22692 }
22693 CONSTEXPR npu_set_ifm2_scalar_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22694 {
22695 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22696 return *this;
22697 }
22698 CONSTEXPR uint32_t get_scalar() const
22699 {
22700 return static_cast<uint32_t>(scalar);
22701 }
22702 CONSTEXPR npu_set_ifm2_scalar_t &set_scalar(uint32_t value)
22703 {
22704 scalar = static_cast<uint16_t>(value) & ((1U << 16) - 1);
22705 return *this;
22706 }
22707#ifdef NPU_DISASSEMBLE
22708 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22709 {
22710 fields.push_back(std::make_pair<std::string, std::string>("scalar", std::to_string(scalar)));
22711 }
22712#endif
22713#endif
22714 };
22715 // IFM2 Precision
22717 {
22718#ifdef __cplusplus
22719 private:
22720#endif
22721 uint32_t opcode : 10; // opcode
22722 uint32_t reserved0 : 4;
22723 uint32_t control : 2; // control
22724 uint32_t activation_type : 1; // IFM type - MUST MATCH IFM
22725 uint32_t reserved1 : 1;
22726 uint32_t activation_precision : 2; // IFM precision - MUST MATCH IFM
22727 uint32_t reserved2 : 2;
22728 uint32_t activation_format : 2; // IFM format
22729 uint32_t reserved3 : 8;
22730#ifdef __cplusplus
22731 public:
22732 npu_set_ifm2_precision_t(NPU_NAMESPACE::activation_type _activation_type,
22733 NPU_NAMESPACE::activation_precision _activation_precision,
22734 NPU_NAMESPACE::activation_format _activation_format) :
22735 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION)),
22736 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
22737 activation_type(static_cast<uint8_t>(_activation_type) & ((1U << 1) - 1)), reserved1(0),
22738 activation_precision(static_cast<uint8_t>(_activation_precision) & ((1U << 2) - 1)), reserved2(0),
22739 activation_format(static_cast<uint8_t>(_activation_format) & ((1U << 2) - 1)), reserved3(0)
22740 {
22741 }
22743 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION)), reserved0(0),
22744 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), activation_type(0), reserved1(0),
22745 activation_precision(0), reserved2(0), activation_format(0), reserved3(0)
22746 {
22747 }
22748 CONSTEXPR bool valid() const
22749 {
22750 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION) &&
22751 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22752 }
22753 CONSTEXPR void init()
22754 {
22755 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION);
22756 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22757 }
22758 operator uint32_t()
22759 {
22760 uint32_t word;
22761 std::memcpy(&word, this, sizeof(word));
22762 return word;
22763 }
22764 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22765 {
22766 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22767 }
22768 CONSTEXPR npu_set_ifm2_precision_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22769 {
22770 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22771 return *this;
22772 }
22773 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22774 {
22775 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22776 }
22777 CONSTEXPR npu_set_ifm2_precision_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22778 {
22779 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22780 return *this;
22781 }
22782 CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type() const
22783 {
22784 return static_cast<NPU_NAMESPACE::activation_type>(activation_type);
22785 }
22786 CONSTEXPR npu_set_ifm2_precision_t &set_activation_type(NPU_NAMESPACE::activation_type value)
22787 {
22788 activation_type = static_cast<uint8_t>(value) & ((1U << 1) - 1);
22789 return *this;
22790 }
22791 CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision() const
22792 {
22793 return static_cast<NPU_NAMESPACE::activation_precision>(activation_precision);
22794 }
22795 CONSTEXPR npu_set_ifm2_precision_t &set_activation_precision(NPU_NAMESPACE::activation_precision value)
22796 {
22797 activation_precision = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22798 return *this;
22799 }
22800 CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format() const
22801 {
22802 return static_cast<NPU_NAMESPACE::activation_format>(activation_format);
22803 }
22804 CONSTEXPR npu_set_ifm2_precision_t &set_activation_format(NPU_NAMESPACE::activation_format value)
22805 {
22806 activation_format = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22807 return *this;
22808 }
22809#ifdef NPU_DISASSEMBLE
22810 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22811 {
22812 fields.push_back(std::make_pair<std::string, std::string>(
22813 "activation_type",
22814 (activation_type < (sizeof(activation_type_str) / sizeof(activation_type_str[0])) ?
22815 activation_type_str[activation_type] :
22816 "****")));
22817 fields.push_back(std::make_pair<std::string, std::string>(
22818 "activation_precision",
22819 (activation_precision < (sizeof(activation_precision_str) / sizeof(activation_precision_str[0])) ?
22820 activation_precision_str[activation_precision] :
22821 "****")));
22822 fields.push_back(std::make_pair<std::string, std::string>(
22823 "activation_format",
22824 (activation_format < (sizeof(activation_format_str) / sizeof(activation_format_str[0])) ?
22825 activation_format_str[activation_format] :
22826 "****")));
22827 }
22828#endif
22829#endif
22830 };
22831 // IFM2 zero point
22833 {
22834#ifdef __cplusplus
22835 private:
22836#endif
22837 uint32_t opcode : 10; // opcode
22838 uint32_t reserved0 : 4;
22839 uint32_t control : 2; // control
22840 uint32_t zero_point : 16; // Zero point offset
22841#ifdef __cplusplus
22842 public:
22843 npu_set_ifm2_zero_point_t(uint32_t _zero_point) :
22844 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT)), reserved0(0),
22845 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)),
22846 zero_point(_zero_point & ((1U << 16) - 1))
22847 {
22848 }
22850 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT)), reserved0(0),
22851 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), zero_point(0)
22852 {
22853 }
22854 CONSTEXPR bool valid() const
22855 {
22856 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT) &&
22857 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22858 }
22859 CONSTEXPR void init()
22860 {
22861 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT);
22862 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22863 }
22864 operator uint32_t()
22865 {
22866 uint32_t word;
22867 std::memcpy(&word, this, sizeof(word));
22868 return word;
22869 }
22870 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22871 {
22872 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22873 }
22874 CONSTEXPR npu_set_ifm2_zero_point_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22875 {
22876 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22877 return *this;
22878 }
22879 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22880 {
22881 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22882 }
22883 CONSTEXPR npu_set_ifm2_zero_point_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22884 {
22885 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22886 return *this;
22887 }
22888 CONSTEXPR uint32_t get_zero_point() const
22889 {
22890 return static_cast<uint32_t>(zero_point);
22891 }
22892 CONSTEXPR npu_set_ifm2_zero_point_t &set_zero_point(uint32_t value)
22893 {
22894 zero_point = static_cast<uint16_t>(value) & ((1U << 16) - 1);
22895 return *this;
22896 }
22897#ifdef NPU_DISASSEMBLE
22898 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22899 {
22900 fields.push_back(std::make_pair<std::string, std::string>("zero_point", std::to_string(zero_point)));
22901 }
22902#endif
22903#endif
22904 };
22905 // IFM2 Tile 0 and tile 2 width
22907 {
22908#ifdef __cplusplus
22909 private:
22910#endif
22911 uint32_t opcode : 10; // opcode
22912 uint32_t reserved0 : 4;
22913 uint32_t control : 2; // control
22914 uint32_t width_m1 : 16; // IFM2 Tile 0 and tile 2 width
22915#ifdef __cplusplus
22916 public:
22917 npu_set_ifm2_width0_m1_t(uint32_t _width_m1) :
22918 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1)), reserved0(0),
22919 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
22920 {
22921 }
22923 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1)), reserved0(0),
22924 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), width_m1(0)
22925 {
22926 }
22927 CONSTEXPR bool valid() const
22928 {
22929 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1) &&
22930 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22931 }
22932 CONSTEXPR void init()
22933 {
22934 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1);
22935 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22936 }
22937 operator uint32_t()
22938 {
22939 uint32_t word;
22940 std::memcpy(&word, this, sizeof(word));
22941 return word;
22942 }
22943 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
22944 {
22945 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
22946 }
22947 CONSTEXPR npu_set_ifm2_width0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
22948 {
22949 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
22950 return *this;
22951 }
22952 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
22953 {
22954 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
22955 }
22956 CONSTEXPR npu_set_ifm2_width0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
22957 {
22958 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
22959 return *this;
22960 }
22961 CONSTEXPR uint32_t get_width_m1() const
22962 {
22963 return static_cast<uint32_t>(width_m1);
22964 }
22965 CONSTEXPR npu_set_ifm2_width0_m1_t &set_width_m1(uint32_t value)
22966 {
22967 width_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
22968 return *this;
22969 }
22970#ifdef NPU_DISASSEMBLE
22971 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
22972 {
22973 fields.push_back(std::make_pair<std::string, std::string>("width_m1", std::to_string(width_m1)));
22974 }
22975#endif
22976#endif
22977 };
22978 // IFM2 Tile 0 height
22980 {
22981#ifdef __cplusplus
22982 private:
22983#endif
22984 uint32_t opcode : 10; // opcode
22985 uint32_t reserved0 : 4;
22986 uint32_t control : 2; // control
22987 uint32_t height_m1 : 16; // IFM2 Tile 0 height
22988#ifdef __cplusplus
22989 public:
22990 npu_set_ifm2_height0_m1_t(uint32_t _height_m1) :
22991 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1)), reserved0(0),
22992 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
22993 {
22994 }
22996 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1)), reserved0(0),
22997 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
22998 {
22999 }
23000 CONSTEXPR bool valid() const
23001 {
23002 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1) &&
23003 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23004 }
23005 CONSTEXPR void init()
23006 {
23007 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1);
23008 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23009 }
23010 operator uint32_t()
23011 {
23012 uint32_t word;
23013 std::memcpy(&word, this, sizeof(word));
23014 return word;
23015 }
23016 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
23017 {
23018 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
23019 }
23020 CONSTEXPR npu_set_ifm2_height0_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
23021 {
23022 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
23023 return *this;
23024 }
23025 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
23026 {
23027 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
23028 }
23029 CONSTEXPR npu_set_ifm2_height0_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
23030 {
23031 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
23032 return *this;
23033 }
23034 CONSTEXPR uint32_t get_height_m1() const
23035 {
23036 return static_cast<uint32_t>(height_m1);
23037 }
23038 CONSTEXPR npu_set_ifm2_height0_m1_t &set_height_m1(uint32_t value)
23039 {
23040 height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
23041 return *this;
23042 }
23043#ifdef NPU_DISASSEMBLE
23044 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23045 {
23046 fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
23047 }
23048#endif
23049#endif
23050 };
23051 // IFM2 Tile 1 height
23053 {
23054#ifdef __cplusplus
23055 private:
23056#endif
23057 uint32_t opcode : 10; // opcode
23058 uint32_t reserved0 : 4;
23059 uint32_t control : 2; // control
23060 uint32_t height_m1 : 16; // IFM2 Tile 1 height
23061#ifdef __cplusplus
23062 public:
23063 npu_set_ifm2_height1_m1_t(uint32_t _height_m1) :
23064 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1)), reserved0(0),
23065 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
23066 {
23067 }
23069 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1)), reserved0(0),
23070 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), height_m1(0)
23071 {
23072 }
23073 CONSTEXPR bool valid() const
23074 {
23075 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1) &&
23076 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23077 }
23078 CONSTEXPR void init()
23079 {
23080 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1);
23081 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23082 }
23083 operator uint32_t()
23084 {
23085 uint32_t word;
23086 std::memcpy(&word, this, sizeof(word));
23087 return word;
23088 }
23089 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
23090 {
23091 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
23092 }
23093 CONSTEXPR npu_set_ifm2_height1_m1_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
23094 {
23095 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
23096 return *this;
23097 }
23098 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
23099 {
23100 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
23101 }
23102 CONSTEXPR npu_set_ifm2_height1_m1_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
23103 {
23104 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
23105 return *this;
23106 }
23107 CONSTEXPR uint32_t get_height_m1() const
23108 {
23109 return static_cast<uint32_t>(height_m1);
23110 }
23111 CONSTEXPR npu_set_ifm2_height1_m1_t &set_height_m1(uint32_t value)
23112 {
23113 height_m1 = static_cast<uint16_t>(value) & ((1U << 16) - 1);
23114 return *this;
23115 }
23116#ifdef NPU_DISASSEMBLE
23117 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23118 {
23119 fields.push_back(std::make_pair<std::string, std::string>("height_m1", std::to_string(height_m1)));
23120 }
23121#endif
23122#endif
23123 };
23124 // Start of IB0,IB1 buffers for IFM2
23126 {
23127#ifdef __cplusplus
23128 private:
23129#endif
23130 uint32_t opcode : 10; // opcode
23131 uint32_t reserved0 : 4;
23132 uint32_t control : 2; // control
23133 uint32_t ib_start : 6; // Start of IB0,IB1 buffers for IFM2 in the SHRAM in KB units. Multiple of 2
23134 uint32_t reserved1 : 10;
23135#ifdef __cplusplus
23136 public:
23137 npu_set_ifm2_ib_start_t(uint32_t _ib_start) :
23138 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START)), reserved0(0),
23139 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_start(_ib_start & ((1U << 6) - 1)),
23140 reserved1(0)
23141 {
23142 }
23144 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START)), reserved0(0),
23145 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), ib_start(0), reserved1(0)
23146 {
23147 }
23148 CONSTEXPR bool valid() const
23149 {
23150 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START) &&
23151 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23152 }
23153 CONSTEXPR void init()
23154 {
23155 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START);
23156 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23157 }
23158 operator uint32_t()
23159 {
23160 uint32_t word;
23161 std::memcpy(&word, this, sizeof(word));
23162 return word;
23163 }
23164 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
23165 {
23166 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
23167 }
23168 CONSTEXPR npu_set_ifm2_ib_start_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
23169 {
23170 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
23171 return *this;
23172 }
23173 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
23174 {
23175 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
23176 }
23177 CONSTEXPR npu_set_ifm2_ib_start_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
23178 {
23179 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
23180 return *this;
23181 }
23182 CONSTEXPR uint32_t get_ib_start() const
23183 {
23184 return static_cast<uint32_t>(ib_start);
23185 }
23186 CONSTEXPR npu_set_ifm2_ib_start_t &set_ib_start(uint32_t value)
23187 {
23188 ib_start = static_cast<uint8_t>(value) & ((1U << 6) - 1);
23189 return *this;
23190 }
23191#ifdef NPU_DISASSEMBLE
23192 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23193 {
23194 fields.push_back(std::make_pair<std::string, std::string>("ib_start", std::to_string(ib_start)));
23195 }
23196#endif
23197#endif
23198 };
23199 // Index n for IFM2 access
23201 {
23202#ifdef __cplusplus
23203 private:
23204#endif
23205 uint32_t opcode : 10; // opcode
23206 uint32_t reserved0 : 4;
23207 uint32_t control : 2; // control
23208 uint32_t region : 3; // Index n for IFM2 access
23209 uint32_t reserved1 : 13;
23210#ifdef __cplusplus
23211 public:
23212 npu_set_ifm2_region_t(uint32_t _region) :
23213 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION)), reserved0(0),
23214 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
23215 reserved1(0)
23216 {
23217 }
23219 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION)), reserved0(0),
23220 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
23221 {
23222 }
23223 CONSTEXPR bool valid() const
23224 {
23225 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION) &&
23226 control == static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23227 }
23228 CONSTEXPR void init()
23229 {
23230 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION);
23231 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23232 }
23233 operator uint32_t()
23234 {
23235 uint32_t word;
23236 std::memcpy(&word, this, sizeof(word));
23237 return word;
23238 }
23239 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode() const
23240 {
23241 return static_cast<NPU_NAMESPACE::cmd0_opcode>(opcode);
23242 }
23243 CONSTEXPR npu_set_ifm2_region_t &set_opcode(NPU_NAMESPACE::cmd0_opcode value)
23244 {
23245 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
23246 return *this;
23247 }
23248 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
23249 {
23250 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
23251 }
23252 CONSTEXPR npu_set_ifm2_region_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
23253 {
23254 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
23255 return *this;
23256 }
23257 CONSTEXPR uint32_t get_region() const
23258 {
23259 return static_cast<uint32_t>(region);
23260 }
23261 CONSTEXPR npu_set_ifm2_region_t &set_region(uint32_t value)
23262 {
23263 region = static_cast<uint8_t>(value) & ((1U << 3) - 1);
23264 return *this;
23265 }
23266#ifdef NPU_DISASSEMBLE
23267 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23268 {
23269 fields.push_back(std::make_pair<std::string, std::string>("region", std::to_string(region)));
23270 }
23271#endif
23272#endif
23273 };
23274 // IFM Tile 0 address
23275 struct npu_set_ifm_base0_t
23276 {
23277#ifdef __cplusplus
23278 private:
23279#endif
23280 uint32_t opcode : 10; // opcode
23281 uint32_t reserved0 : 4;
23282 uint32_t control : 2; // control
23283 uint32_t addr_hi : 8; // address extension
23284 uint32_t reserved1 : 8;
23285 uint32_t addr_lo : 32; // address offset
23286#ifdef __cplusplus
23287 public:
23288 npu_set_ifm_base0_t(uint64_t _addr) :
23289 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0)), reserved0(0),
23290 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23291 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23292 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23293 {
23294 }
23296 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0)), reserved0(0),
23297 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23298 {
23299 }
23300 CONSTEXPR bool valid() const
23301 {
23302 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0) && control >= 1 &&
23303 control <= 2;
23304 }
23305 CONSTEXPR void init()
23306 {
23307 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0);
23308 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23309 }
23310 operator uint64_t()
23311 {
23312 uint64_t word;
23313 std::memcpy(&word, this, sizeof(word));
23314 return word;
23315 }
23316 CONSTEXPR uint64_t get_addr() const
23317 {
23318 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23319 }
23320 CONSTEXPR npu_set_ifm_base0_t &set_addr(uint64_t value)
23321 {
23322 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23323 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23324 return *this;
23325 }
23326#ifdef NPU_DISASSEMBLE
23327 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23328 {
23329 std::stringstream saddr;
23330 saddr << std::hex << "0x" << get_addr();
23331 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23332 }
23333#endif
23334#endif
23335 };
23336 // IFM Tile 1 address
23337 struct npu_set_ifm_base1_t
23338 {
23339#ifdef __cplusplus
23340 private:
23341#endif
23342 uint32_t opcode : 10; // opcode
23343 uint32_t reserved0 : 4;
23344 uint32_t control : 2; // control
23345 uint32_t addr_hi : 8; // address extension
23346 uint32_t reserved1 : 8;
23347 uint32_t addr_lo : 32; // address offset
23348#ifdef __cplusplus
23349 public:
23350 npu_set_ifm_base1_t(uint64_t _addr) :
23351 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1)), reserved0(0),
23352 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23353 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23354 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23355 {
23356 }
23358 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1)), reserved0(0),
23359 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23360 {
23361 }
23362 CONSTEXPR bool valid() const
23363 {
23364 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1) && control >= 1 &&
23365 control <= 2;
23366 }
23367 CONSTEXPR void init()
23368 {
23369 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1);
23370 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23371 }
23372 operator uint64_t()
23373 {
23374 uint64_t word;
23375 std::memcpy(&word, this, sizeof(word));
23376 return word;
23377 }
23378 CONSTEXPR uint64_t get_addr() const
23379 {
23380 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23381 }
23382 CONSTEXPR npu_set_ifm_base1_t &set_addr(uint64_t value)
23383 {
23384 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23385 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23386 return *this;
23387 }
23388#ifdef NPU_DISASSEMBLE
23389 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23390 {
23391 std::stringstream saddr;
23392 saddr << std::hex << "0x" << get_addr();
23393 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23394 }
23395#endif
23396#endif
23397 };
23398 // IFM Tile 2 address
23399 struct npu_set_ifm_base2_t
23400 {
23401#ifdef __cplusplus
23402 private:
23403#endif
23404 uint32_t opcode : 10; // opcode
23405 uint32_t reserved0 : 4;
23406 uint32_t control : 2; // control
23407 uint32_t addr_hi : 8; // address extension
23408 uint32_t reserved1 : 8;
23409 uint32_t addr_lo : 32; // address offset
23410#ifdef __cplusplus
23411 public:
23412 npu_set_ifm_base2_t(uint64_t _addr) :
23413 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2)), reserved0(0),
23414 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23415 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23416 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23417 {
23418 }
23420 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2)), reserved0(0),
23421 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23422 {
23423 }
23424 CONSTEXPR bool valid() const
23425 {
23426 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2) && control >= 1 &&
23427 control <= 2;
23428 }
23429 CONSTEXPR void init()
23430 {
23431 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2);
23432 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23433 }
23434 operator uint64_t()
23435 {
23436 uint64_t word;
23437 std::memcpy(&word, this, sizeof(word));
23438 return word;
23439 }
23440 CONSTEXPR uint64_t get_addr() const
23441 {
23442 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23443 }
23444 CONSTEXPR npu_set_ifm_base2_t &set_addr(uint64_t value)
23445 {
23446 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23447 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23448 return *this;
23449 }
23450#ifdef NPU_DISASSEMBLE
23451 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23452 {
23453 std::stringstream saddr;
23454 saddr << std::hex << "0x" << get_addr();
23455 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23456 }
23457#endif
23458#endif
23459 };
23460 // IFM Tile 3 address
23461 struct npu_set_ifm_base3_t
23462 {
23463#ifdef __cplusplus
23464 private:
23465#endif
23466 uint32_t opcode : 10; // opcode
23467 uint32_t reserved0 : 4;
23468 uint32_t control : 2; // control
23469 uint32_t addr_hi : 8; // address extension
23470 uint32_t reserved1 : 8;
23471 uint32_t addr_lo : 32; // address offset
23472#ifdef __cplusplus
23473 public:
23474 npu_set_ifm_base3_t(uint64_t _addr) :
23475 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3)), reserved0(0),
23476 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23477 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23478 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23479 {
23480 }
23482 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3)), reserved0(0),
23483 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23484 {
23485 }
23486 CONSTEXPR bool valid() const
23487 {
23488 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3) && control >= 1 &&
23489 control <= 2;
23490 }
23491 CONSTEXPR void init()
23492 {
23493 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3);
23494 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23495 }
23496 operator uint64_t()
23497 {
23498 uint64_t word;
23499 std::memcpy(&word, this, sizeof(word));
23500 return word;
23501 }
23502 CONSTEXPR uint64_t get_addr() const
23503 {
23504 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23505 }
23506 CONSTEXPR npu_set_ifm_base3_t &set_addr(uint64_t value)
23507 {
23508 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23509 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23510 return *this;
23511 }
23512#ifdef NPU_DISASSEMBLE
23513 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23514 {
23515 std::stringstream saddr;
23516 saddr << std::hex << "0x" << get_addr();
23517 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23518 }
23519#endif
23520#endif
23521 };
23522 // IFM byte stride between horizontal values
23524 {
23525#ifdef __cplusplus
23526 private:
23527#endif
23528 uint32_t opcode : 10; // opcode
23529 uint32_t reserved0 : 4;
23530 uint32_t control : 2; // control
23531 uint32_t addr_hi : 8; // address extension
23532 uint32_t reserved1 : 8;
23533 uint32_t addr_lo : 32; // address offset
23534#ifdef __cplusplus
23535 public:
23536 npu_set_ifm_stride_x_t(uint64_t _addr) :
23537 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X)), reserved0(0),
23538 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23539 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23540 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23541 {
23542 }
23544 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X)), reserved0(0),
23545 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23546 {
23547 }
23548 CONSTEXPR bool valid() const
23549 {
23550 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X) && control >= 1 &&
23551 control <= 2;
23552 }
23553 CONSTEXPR void init()
23554 {
23555 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X);
23556 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23557 }
23558 operator uint64_t()
23559 {
23560 uint64_t word;
23561 std::memcpy(&word, this, sizeof(word));
23562 return word;
23563 }
23564 CONSTEXPR uint64_t get_addr() const
23565 {
23566 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23567 }
23568 CONSTEXPR npu_set_ifm_stride_x_t &set_addr(uint64_t value)
23569 {
23570 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23571 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23572 return *this;
23573 }
23574#ifdef NPU_DISASSEMBLE
23575 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23576 {
23577 std::stringstream saddr;
23578 saddr << std::hex << "0x" << get_addr();
23579 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23580 }
23581#endif
23582#endif
23583 };
23584 // IFM byte stride between vertical values
23586 {
23587#ifdef __cplusplus
23588 private:
23589#endif
23590 uint32_t opcode : 10; // opcode
23591 uint32_t reserved0 : 4;
23592 uint32_t control : 2; // control
23593 uint32_t addr_hi : 8; // address extension
23594 uint32_t reserved1 : 8;
23595 uint32_t addr_lo : 32; // address offset
23596#ifdef __cplusplus
23597 public:
23598 npu_set_ifm_stride_y_t(uint64_t _addr) :
23599 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y)), reserved0(0),
23600 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23601 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23602 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23603 {
23604 }
23606 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y)), reserved0(0),
23607 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23608 {
23609 }
23610 CONSTEXPR bool valid() const
23611 {
23612 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y) && control >= 1 &&
23613 control <= 2;
23614 }
23615 CONSTEXPR void init()
23616 {
23617 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y);
23618 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23619 }
23620 operator uint64_t()
23621 {
23622 uint64_t word;
23623 std::memcpy(&word, this, sizeof(word));
23624 return word;
23625 }
23626 CONSTEXPR uint64_t get_addr() const
23627 {
23628 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23629 }
23630 CONSTEXPR npu_set_ifm_stride_y_t &set_addr(uint64_t value)
23631 {
23632 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23633 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23634 return *this;
23635 }
23636#ifdef NPU_DISASSEMBLE
23637 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23638 {
23639 std::stringstream saddr;
23640 saddr << std::hex << "0x" << get_addr();
23641 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23642 }
23643#endif
23644#endif
23645 };
23646 // IFM byte stride between channel blocks (of 16 bytes each block)
23648 {
23649#ifdef __cplusplus
23650 private:
23651#endif
23652 uint32_t opcode : 10; // opcode
23653 uint32_t reserved0 : 4;
23654 uint32_t control : 2; // control
23655 uint32_t addr_hi : 8; // address extension
23656 uint32_t reserved1 : 8;
23657 uint32_t addr_lo : 32; // address offset
23658#ifdef __cplusplus
23659 public:
23660 npu_set_ifm_stride_c_t(uint64_t _addr) :
23661 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C)), reserved0(0),
23662 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23663 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23664 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23665 {
23666 }
23668 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C)), reserved0(0),
23669 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23670 {
23671 }
23672 CONSTEXPR bool valid() const
23673 {
23674 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C) && control >= 1 &&
23675 control <= 2;
23676 }
23677 CONSTEXPR void init()
23678 {
23679 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C);
23680 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23681 }
23682 operator uint64_t()
23683 {
23684 uint64_t word;
23685 std::memcpy(&word, this, sizeof(word));
23686 return word;
23687 }
23688 CONSTEXPR uint64_t get_addr() const
23689 {
23690 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23691 }
23692 CONSTEXPR npu_set_ifm_stride_c_t &set_addr(uint64_t value)
23693 {
23694 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23695 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23696 return *this;
23697 }
23698#ifdef NPU_DISASSEMBLE
23699 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23700 {
23701 std::stringstream saddr;
23702 saddr << std::hex << "0x" << get_addr();
23703 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23704 }
23705#endif
23706#endif
23707 };
23708 // OFM Tile 0 address
23709 struct npu_set_ofm_base0_t
23710 {
23711#ifdef __cplusplus
23712 private:
23713#endif
23714 uint32_t opcode : 10; // opcode
23715 uint32_t reserved0 : 4;
23716 uint32_t control : 2; // control
23717 uint32_t addr_hi : 8; // address extension
23718 uint32_t reserved1 : 8;
23719 uint32_t addr_lo : 32; // address offset
23720#ifdef __cplusplus
23721 public:
23722 npu_set_ofm_base0_t(uint64_t _addr) :
23723 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0)), reserved0(0),
23724 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23725 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23726 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23727 {
23728 }
23730 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0)), reserved0(0),
23731 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23732 {
23733 }
23734 CONSTEXPR bool valid() const
23735 {
23736 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0) && control >= 1 &&
23737 control <= 2;
23738 }
23739 CONSTEXPR void init()
23740 {
23741 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0);
23742 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23743 }
23744 operator uint64_t()
23745 {
23746 uint64_t word;
23747 std::memcpy(&word, this, sizeof(word));
23748 return word;
23749 }
23750 CONSTEXPR uint64_t get_addr() const
23751 {
23752 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23753 }
23754 CONSTEXPR npu_set_ofm_base0_t &set_addr(uint64_t value)
23755 {
23756 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23757 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23758 return *this;
23759 }
23760#ifdef NPU_DISASSEMBLE
23761 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23762 {
23763 std::stringstream saddr;
23764 saddr << std::hex << "0x" << get_addr();
23765 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23766 }
23767#endif
23768#endif
23769 };
23770 // OFM Tile 1 address
23771 struct npu_set_ofm_base1_t
23772 {
23773#ifdef __cplusplus
23774 private:
23775#endif
23776 uint32_t opcode : 10; // opcode
23777 uint32_t reserved0 : 4;
23778 uint32_t control : 2; // control
23779 uint32_t addr_hi : 8; // address extension
23780 uint32_t reserved1 : 8;
23781 uint32_t addr_lo : 32; // address offset
23782#ifdef __cplusplus
23783 public:
23784 npu_set_ofm_base1_t(uint64_t _addr) :
23785 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1)), reserved0(0),
23786 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23787 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23788 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23789 {
23790 }
23792 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1)), reserved0(0),
23793 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23794 {
23795 }
23796 CONSTEXPR bool valid() const
23797 {
23798 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1) && control >= 1 &&
23799 control <= 2;
23800 }
23801 CONSTEXPR void init()
23802 {
23803 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1);
23804 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23805 }
23806 operator uint64_t()
23807 {
23808 uint64_t word;
23809 std::memcpy(&word, this, sizeof(word));
23810 return word;
23811 }
23812 CONSTEXPR uint64_t get_addr() const
23813 {
23814 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23815 }
23816 CONSTEXPR npu_set_ofm_base1_t &set_addr(uint64_t value)
23817 {
23818 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23819 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23820 return *this;
23821 }
23822#ifdef NPU_DISASSEMBLE
23823 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23824 {
23825 std::stringstream saddr;
23826 saddr << std::hex << "0x" << get_addr();
23827 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23828 }
23829#endif
23830#endif
23831 };
23832 // OFM Tile 2 address
23833 struct npu_set_ofm_base2_t
23834 {
23835#ifdef __cplusplus
23836 private:
23837#endif
23838 uint32_t opcode : 10; // opcode
23839 uint32_t reserved0 : 4;
23840 uint32_t control : 2; // control
23841 uint32_t addr_hi : 8; // address extension
23842 uint32_t reserved1 : 8;
23843 uint32_t addr_lo : 32; // address offset
23844#ifdef __cplusplus
23845 public:
23846 npu_set_ofm_base2_t(uint64_t _addr) :
23847 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2)), reserved0(0),
23848 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23849 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23850 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23851 {
23852 }
23854 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2)), reserved0(0),
23855 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23856 {
23857 }
23858 CONSTEXPR bool valid() const
23859 {
23860 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2) && control >= 1 &&
23861 control <= 2;
23862 }
23863 CONSTEXPR void init()
23864 {
23865 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2);
23866 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23867 }
23868 operator uint64_t()
23869 {
23870 uint64_t word;
23871 std::memcpy(&word, this, sizeof(word));
23872 return word;
23873 }
23874 CONSTEXPR uint64_t get_addr() const
23875 {
23876 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23877 }
23878 CONSTEXPR npu_set_ofm_base2_t &set_addr(uint64_t value)
23879 {
23880 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23881 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23882 return *this;
23883 }
23884#ifdef NPU_DISASSEMBLE
23885 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23886 {
23887 std::stringstream saddr;
23888 saddr << std::hex << "0x" << get_addr();
23889 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23890 }
23891#endif
23892#endif
23893 };
23894 // OFM Tile 3 address
23895 struct npu_set_ofm_base3_t
23896 {
23897#ifdef __cplusplus
23898 private:
23899#endif
23900 uint32_t opcode : 10; // opcode
23901 uint32_t reserved0 : 4;
23902 uint32_t control : 2; // control
23903 uint32_t addr_hi : 8; // address extension
23904 uint32_t reserved1 : 8;
23905 uint32_t addr_lo : 32; // address offset
23906#ifdef __cplusplus
23907 public:
23908 npu_set_ofm_base3_t(uint64_t _addr) :
23909 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3)), reserved0(0),
23910 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23911 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23912 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23913 {
23914 }
23916 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3)), reserved0(0),
23917 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23918 {
23919 }
23920 CONSTEXPR bool valid() const
23921 {
23922 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3) && control >= 1 &&
23923 control <= 2;
23924 }
23925 CONSTEXPR void init()
23926 {
23927 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3);
23928 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23929 }
23930 operator uint64_t()
23931 {
23932 uint64_t word;
23933 std::memcpy(&word, this, sizeof(word));
23934 return word;
23935 }
23936 CONSTEXPR uint64_t get_addr() const
23937 {
23938 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
23939 }
23940 CONSTEXPR npu_set_ofm_base3_t &set_addr(uint64_t value)
23941 {
23942 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
23943 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
23944 return *this;
23945 }
23946#ifdef NPU_DISASSEMBLE
23947 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
23948 {
23949 std::stringstream saddr;
23950 saddr << std::hex << "0x" << get_addr();
23951 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
23952 }
23953#endif
23954#endif
23955 };
23956 // OFM byte stride between horizontal values
23958 {
23959#ifdef __cplusplus
23960 private:
23961#endif
23962 uint32_t opcode : 10; // opcode
23963 uint32_t reserved0 : 4;
23964 uint32_t control : 2; // control
23965 uint32_t addr_hi : 8; // address extension
23966 uint32_t reserved1 : 8;
23967 uint32_t addr_lo : 32; // address offset
23968#ifdef __cplusplus
23969 public:
23970 npu_set_ofm_stride_x_t(uint64_t _addr) :
23971 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X)), reserved0(0),
23972 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
23973 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
23974 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
23975 {
23976 }
23978 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X)), reserved0(0),
23979 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23980 {
23981 }
23982 CONSTEXPR bool valid() const
23983 {
23984 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X) && control >= 1 &&
23985 control <= 2;
23986 }
23987 CONSTEXPR void init()
23988 {
23989 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X);
23990 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23991 }
23992 operator uint64_t()
23993 {
23994 uint64_t word;
23995 std::memcpy(&word, this, sizeof(word));
23996 return word;
23997 }
23998 CONSTEXPR uint64_t get_addr() const
23999 {
24000 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
24001 }
24002 CONSTEXPR npu_set_ofm_stride_x_t &set_addr(uint64_t value)
24003 {
24004 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
24005 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
24006 return *this;
24007 }
24008#ifdef NPU_DISASSEMBLE
24009 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24010 {
24011 std::stringstream saddr;
24012 saddr << std::hex << "0x" << get_addr();
24013 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
24014 }
24015#endif
24016#endif
24017 };
24018 // OFM byte stride between vertical values
24020 {
24021#ifdef __cplusplus
24022 private:
24023#endif
24024 uint32_t opcode : 10; // opcode
24025 uint32_t reserved0 : 4;
24026 uint32_t control : 2; // control
24027 uint32_t addr_hi : 8; // address extension
24028 uint32_t reserved1 : 8;
24029 uint32_t addr_lo : 32; // address offset
24030#ifdef __cplusplus
24031 public:
24032 npu_set_ofm_stride_y_t(uint64_t _addr) :
24033 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y)), reserved0(0),
24034 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
24035 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
24036 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
24037 {
24038 }
24040 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y)), reserved0(0),
24041 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24042 {
24043 }
24044 CONSTEXPR bool valid() const
24045 {
24046 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y) && control >= 1 &&
24047 control <= 2;
24048 }
24049 CONSTEXPR void init()
24050 {
24051 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y);
24052 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24053 }
24054 operator uint64_t()
24055 {
24056 uint64_t word;
24057 std::memcpy(&word, this, sizeof(word));
24058 return word;
24059 }
24060 CONSTEXPR uint64_t get_addr() const
24061 {
24062 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
24063 }
24064 CONSTEXPR npu_set_ofm_stride_y_t &set_addr(uint64_t value)
24065 {
24066 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
24067 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
24068 return *this;
24069 }
24070#ifdef NPU_DISASSEMBLE
24071 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24072 {
24073 std::stringstream saddr;
24074 saddr << std::hex << "0x" << get_addr();
24075 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
24076 }
24077#endif
24078#endif
24079 };
24080 // OFM byte stride between channel blocks (of 16 bytes each block)
24082 {
24083#ifdef __cplusplus
24084 private:
24085#endif
24086 uint32_t opcode : 10; // opcode
24087 uint32_t reserved0 : 4;
24088 uint32_t control : 2; // control
24089 uint32_t addr_hi : 8; // address extension
24090 uint32_t reserved1 : 8;
24091 uint32_t addr_lo : 32; // address offset
24092#ifdef __cplusplus
24093 public:
24094 npu_set_ofm_stride_c_t(uint64_t _addr) :
24095 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C)), reserved0(0),
24096 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
24097 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
24098 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
24099 {
24100 }
24102 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C)), reserved0(0),
24103 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24104 {
24105 }
24106 CONSTEXPR bool valid() const
24107 {
24108 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C) && control >= 1 &&
24109 control <= 2;
24110 }
24111 CONSTEXPR void init()
24112 {
24113 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C);
24114 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24115 }
24116 operator uint64_t()
24117 {
24118 uint64_t word;
24119 std::memcpy(&word, this, sizeof(word));
24120 return word;
24121 }
24122 CONSTEXPR uint64_t get_addr() const
24123 {
24124 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
24125 }
24126 CONSTEXPR npu_set_ofm_stride_c_t &set_addr(uint64_t value)
24127 {
24128 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
24129 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
24130 return *this;
24131 }
24132#ifdef NPU_DISASSEMBLE
24133 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24134 {
24135 std::stringstream saddr;
24136 saddr << std::hex << "0x" << get_addr();
24137 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
24138 }
24139#endif
24140#endif
24141 };
24142 // Weight stream byte offset in WEIGHT_REGION
24144 {
24145#ifdef __cplusplus
24146 private:
24147#endif
24148 uint32_t opcode : 10; // opcode
24149 uint32_t reserved0 : 4;
24150 uint32_t control : 2; // control
24151 uint32_t addr_hi : 8; // address extension
24152 uint32_t reserved1 : 8;
24153 uint32_t addr_lo : 32; // address offset
24154#ifdef __cplusplus
24155 public:
24156 npu_set_weight_base_t(uint64_t _addr) :
24157 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE)), reserved0(0),
24158 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
24159 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
24160 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
24161 {
24162 }
24164 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE)), reserved0(0),
24165 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24166 {
24167 }
24168 CONSTEXPR bool valid() const
24169 {
24170 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE) && control >= 1 &&
24171 control <= 2;
24172 }
24173 CONSTEXPR void init()
24174 {
24175 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE);
24176 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24177 }
24178 operator uint64_t()
24179 {
24180 uint64_t word;
24181 std::memcpy(&word, this, sizeof(word));
24182 return word;
24183 }
24184 CONSTEXPR uint64_t get_addr() const
24185 {
24186 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
24187 }
24188 CONSTEXPR npu_set_weight_base_t &set_addr(uint64_t value)
24189 {
24190 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
24191 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
24192 return *this;
24193 }
24194#ifdef NPU_DISASSEMBLE
24195 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24196 {
24197 std::stringstream saddr;
24198 saddr << std::hex << "0x" << get_addr();
24199 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
24200 }
24201#endif
24202#endif
24203 };
24204 // Weight stream byte length
24206 {
24207#ifdef __cplusplus
24208 private:
24209#endif
24210 uint32_t opcode : 10; // opcode
24211 uint32_t reserved0 : 4;
24212 uint32_t control : 2; // control
24213 uint32_t reserved1 : 16;
24214 uint32_t length : 32; // Weight stream byte length
24215#ifdef __cplusplus
24216 public:
24217 npu_set_weight_length_t(uint32_t _length) :
24218 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH)), reserved0(0),
24219 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(_length)
24220 {
24221 }
24223 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH)), reserved0(0),
24224 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0)
24225 {
24226 }
24227 CONSTEXPR bool valid() const
24228 {
24229 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH) && control >= 1 &&
24230 control <= 2;
24231 }
24232 CONSTEXPR void init()
24233 {
24234 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH);
24235 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24236 }
24237 operator uint64_t()
24238 {
24239 uint64_t word;
24240 std::memcpy(&word, this, sizeof(word));
24241 return word;
24242 }
24243 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const
24244 {
24245 return static_cast<NPU_NAMESPACE::cmd1_opcode>(opcode);
24246 }
24247 CONSTEXPR npu_set_weight_length_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value)
24248 {
24249 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
24250 return *this;
24251 }
24252 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
24253 {
24254 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
24255 }
24256 CONSTEXPR npu_set_weight_length_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
24257 {
24258 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
24259 return *this;
24260 }
24261 CONSTEXPR uint32_t get_length() const
24262 {
24263 return static_cast<uint32_t>(length);
24264 }
24265 CONSTEXPR npu_set_weight_length_t &set_length(uint32_t value)
24266 {
24267 length = value;
24268 return *this;
24269 }
24270#ifdef NPU_DISASSEMBLE
24271 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24272 {
24273 fields.push_back(std::make_pair<std::string, std::string>("length", std::to_string(length)));
24274 }
24275#endif
24276#endif
24277 };
24278 // Scale and bias stream input byte offset from SCALE_REGION
24280 {
24281#ifdef __cplusplus
24282 private:
24283#endif
24284 uint32_t opcode : 10; // opcode
24285 uint32_t reserved0 : 4;
24286 uint32_t control : 2; // control
24287 uint32_t addr_hi : 8; // address extension
24288 uint32_t reserved1 : 8;
24289 uint32_t addr_lo : 32; // address offset
24290#ifdef __cplusplus
24291 public:
24292 npu_set_scale_base_t(uint64_t _addr) :
24293 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE)), reserved0(0),
24294 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
24295 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
24296 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
24297 {
24298 }
24300 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE)), reserved0(0),
24301 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24302 {
24303 }
24304 CONSTEXPR bool valid() const
24305 {
24306 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE) && control >= 1 &&
24307 control <= 2;
24308 }
24309 CONSTEXPR void init()
24310 {
24311 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE);
24312 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24313 }
24314 operator uint64_t()
24315 {
24316 uint64_t word;
24317 std::memcpy(&word, this, sizeof(word));
24318 return word;
24319 }
24320 CONSTEXPR uint64_t get_addr() const
24321 {
24322 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
24323 }
24324 CONSTEXPR npu_set_scale_base_t &set_addr(uint64_t value)
24325 {
24326 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
24327 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
24328 return *this;
24329 }
24330#ifdef NPU_DISASSEMBLE
24331 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24332 {
24333 std::stringstream saddr;
24334 saddr << std::hex << "0x" << get_addr();
24335 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
24336 }
24337#endif
24338#endif
24339 };
24340 // Scale and bias stream input byte length
24342 {
24343#ifdef __cplusplus
24344 private:
24345#endif
24346 uint32_t opcode : 10; // opcode
24347 uint32_t reserved0 : 4;
24348 uint32_t control : 2; // control
24349 uint32_t reserved1 : 16;
24350 uint32_t length : 20; // Scale and bias stream byte length
24351 uint32_t reserved2 : 12;
24352#ifdef __cplusplus
24353 public:
24354 npu_set_scale_length_t(uint32_t _length) :
24355 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH)), reserved0(0),
24356 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0),
24357 length(_length & ((1U << 20) - 1)), reserved2(0)
24358 {
24359 }
24361 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH)), reserved0(0),
24362 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0), reserved2(0)
24363 {
24364 }
24365 CONSTEXPR bool valid() const
24366 {
24367 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH) && control >= 1 &&
24368 control <= 2;
24369 }
24370 CONSTEXPR void init()
24371 {
24372 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH);
24373 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24374 }
24375 operator uint64_t()
24376 {
24377 uint64_t word;
24378 std::memcpy(&word, this, sizeof(word));
24379 return word;
24380 }
24381 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const
24382 {
24383 return static_cast<NPU_NAMESPACE::cmd1_opcode>(opcode);
24384 }
24385 CONSTEXPR npu_set_scale_length_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value)
24386 {
24387 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
24388 return *this;
24389 }
24390 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
24391 {
24392 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
24393 }
24394 CONSTEXPR npu_set_scale_length_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
24395 {
24396 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
24397 return *this;
24398 }
24399 CONSTEXPR uint32_t get_length() const
24400 {
24401 return static_cast<uint32_t>(length);
24402 }
24403 CONSTEXPR npu_set_scale_length_t &set_length(uint32_t value)
24404 {
24405 length = value & ((1U << 20) - 1);
24406 return *this;
24407 }
24408#ifdef NPU_DISASSEMBLE
24409 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24410 {
24411 fields.push_back(std::make_pair<std::string, std::string>("length", std::to_string(length)));
24412 }
24413#endif
24414#endif
24415 };
24416 // OFM scale
24417 struct npu_set_ofm_scale_t
24418 {
24419#ifdef __cplusplus
24420 private:
24421#endif
24422 uint32_t opcode : 10; // opcode
24423 uint32_t reserved0 : 4;
24424 uint32_t control : 2; // control
24425 uint32_t shift : 6; // Shift
24426 uint32_t reserved1 : 10;
24427 uint32_t scale : 32; // Scale. Not applied for 32-bit operations
24428#ifdef __cplusplus
24429 public:
24430 npu_set_ofm_scale_t(uint32_t _shift, uint32_t _scale) :
24431 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE)), reserved0(0),
24432 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(_shift & ((1U << 6) - 1)),
24433 reserved1(0), scale(_scale)
24434 {
24435 }
24437 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE)), reserved0(0),
24438 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(0), reserved1(0), scale(0)
24439 {
24440 }
24441 CONSTEXPR bool valid() const
24442 {
24443 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE) && control >= 1 &&
24444 control <= 2;
24445 }
24446 CONSTEXPR void init()
24447 {
24448 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE);
24449 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24450 }
24451 operator uint64_t()
24452 {
24453 uint64_t word;
24454 std::memcpy(&word, this, sizeof(word));
24455 return word;
24456 }
24457 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const
24458 {
24459 return static_cast<NPU_NAMESPACE::cmd1_opcode>(opcode);
24460 }
24461 CONSTEXPR npu_set_ofm_scale_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value)
24462 {
24463 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
24464 return *this;
24465 }
24466 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
24467 {
24468 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
24469 }
24470 CONSTEXPR npu_set_ofm_scale_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
24471 {
24472 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
24473 return *this;
24474 }
24475 CONSTEXPR uint32_t get_shift() const
24476 {
24477 return static_cast<uint32_t>(shift);
24478 }
24479 CONSTEXPR npu_set_ofm_scale_t &set_shift(uint32_t value)
24480 {
24481 shift = static_cast<uint8_t>(value) & ((1U << 6) - 1);
24482 return *this;
24483 }
24484 CONSTEXPR uint32_t get_scale() const
24485 {
24486 return static_cast<uint32_t>(scale);
24487 }
24488 CONSTEXPR npu_set_ofm_scale_t &set_scale(uint32_t value)
24489 {
24490 scale = value;
24491 return *this;
24492 }
24493#ifdef NPU_DISASSEMBLE
24494 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24495 {
24496 fields.push_back(std::make_pair<std::string, std::string>("shift", std::to_string(shift)));
24497 fields.push_back(std::make_pair<std::string, std::string>("scale", std::to_string(scale)));
24498 }
24499#endif
24500#endif
24501 };
24502 // Input operand A scale
24503 struct npu_set_opa_scale_t
24504 {
24505#ifdef __cplusplus
24506 private:
24507#endif
24508 uint32_t opcode : 10; // opcode
24509 uint32_t reserved0 : 4;
24510 uint32_t control : 2; // control
24511 uint32_t shift : 6; // Shift. Ignored if IFM scale mode is 0
24512 uint32_t reserved1 : 10;
24513 uint32_t scale : 32; // Scale. 16-bit if IFM scale mode is 0
24514#ifdef __cplusplus
24515 public:
24516 npu_set_opa_scale_t(uint32_t _shift, uint32_t _scale) :
24517 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE)), reserved0(0),
24518 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(_shift & ((1U << 6) - 1)),
24519 reserved1(0), scale(_scale)
24520 {
24521 }
24523 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE)), reserved0(0),
24524 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), shift(0), reserved1(0), scale(0)
24525 {
24526 }
24527 CONSTEXPR bool valid() const
24528 {
24529 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE) && control >= 1 &&
24530 control <= 2;
24531 }
24532 CONSTEXPR void init()
24533 {
24534 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE);
24535 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24536 }
24537 operator uint64_t()
24538 {
24539 uint64_t word;
24540 std::memcpy(&word, this, sizeof(word));
24541 return word;
24542 }
24543 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const
24544 {
24545 return static_cast<NPU_NAMESPACE::cmd1_opcode>(opcode);
24546 }
24547 CONSTEXPR npu_set_opa_scale_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value)
24548 {
24549 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
24550 return *this;
24551 }
24552 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
24553 {
24554 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
24555 }
24556 CONSTEXPR npu_set_opa_scale_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
24557 {
24558 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
24559 return *this;
24560 }
24561 CONSTEXPR uint32_t get_shift() const
24562 {
24563 return static_cast<uint32_t>(shift);
24564 }
24565 CONSTEXPR npu_set_opa_scale_t &set_shift(uint32_t value)
24566 {
24567 shift = static_cast<uint8_t>(value) & ((1U << 6) - 1);
24568 return *this;
24569 }
24570 CONSTEXPR uint32_t get_scale() const
24571 {
24572 return static_cast<uint32_t>(scale);
24573 }
24574 CONSTEXPR npu_set_opa_scale_t &set_scale(uint32_t value)
24575 {
24576 scale = value;
24577 return *this;
24578 }
24579#ifdef NPU_DISASSEMBLE
24580 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24581 {
24582 fields.push_back(std::make_pair<std::string, std::string>("shift", std::to_string(shift)));
24583 fields.push_back(std::make_pair<std::string, std::string>("scale", std::to_string(scale)));
24584 }
24585#endif
24586#endif
24587 };
24588 // Input operand B scale
24589 struct npu_set_opb_scale_t
24590 {
24591#ifdef __cplusplus
24592 private:
24593#endif
24594 uint32_t opcode : 10; // opcode
24595 uint32_t reserved0 : 4;
24596 uint32_t control : 2; // control
24597 uint32_t reserved1 : 16;
24598 uint32_t scale : 16; // Scale. Not used if IFM scale mode is 1 or 2
24599 uint32_t reserved2 : 16;
24600#ifdef __cplusplus
24601 public:
24602 npu_set_opb_scale_t(uint32_t _scale) :
24603 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE)), reserved0(0),
24604 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0),
24605 scale(_scale & ((1U << 16) - 1)), reserved2(0)
24606 {
24607 }
24609 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE)), reserved0(0),
24610 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), scale(0), reserved2(0)
24611 {
24612 }
24613 CONSTEXPR bool valid() const
24614 {
24615 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE) && control >= 1 &&
24616 control <= 2;
24617 }
24618 CONSTEXPR void init()
24619 {
24620 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE);
24621 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24622 }
24623 operator uint64_t()
24624 {
24625 uint64_t word;
24626 std::memcpy(&word, this, sizeof(word));
24627 return word;
24628 }
24629 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const
24630 {
24631 return static_cast<NPU_NAMESPACE::cmd1_opcode>(opcode);
24632 }
24633 CONSTEXPR npu_set_opb_scale_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value)
24634 {
24635 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
24636 return *this;
24637 }
24638 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
24639 {
24640 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
24641 }
24642 CONSTEXPR npu_set_opb_scale_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
24643 {
24644 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
24645 return *this;
24646 }
24647 CONSTEXPR uint32_t get_scale() const
24648 {
24649 return static_cast<uint32_t>(scale);
24650 }
24651 CONSTEXPR npu_set_opb_scale_t &set_scale(uint32_t value)
24652 {
24653 scale = static_cast<uint16_t>(value) & ((1U << 16) - 1);
24654 return *this;
24655 }
24656#ifdef NPU_DISASSEMBLE
24657 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24658 {
24659 fields.push_back(std::make_pair<std::string, std::string>("scale", std::to_string(scale)));
24660 }
24661#endif
24662#endif
24663 };
24664 // DMA user channel 0 source byte offset from DMA0_SRC_REGION
24665 struct npu_set_dma0_src_t
24666 {
24667#ifdef __cplusplus
24668 private:
24669#endif
24670 uint32_t opcode : 10; // opcode
24671 uint32_t reserved0 : 4;
24672 uint32_t control : 2; // control
24673 uint32_t addr_hi : 8; // address extension
24674 uint32_t reserved1 : 8;
24675 uint32_t addr_lo : 32; // address offset
24676#ifdef __cplusplus
24677 public:
24678 npu_set_dma0_src_t(uint64_t _addr) :
24679 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC)), reserved0(0),
24680 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
24681 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
24682 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
24683 {
24684 }
24686 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC)), reserved0(0),
24687 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24688 {
24689 }
24690 CONSTEXPR bool valid() const
24691 {
24692 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC) && control >= 1 &&
24693 control <= 2;
24694 }
24695 CONSTEXPR void init()
24696 {
24697 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC);
24698 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24699 }
24700 operator uint64_t()
24701 {
24702 uint64_t word;
24703 std::memcpy(&word, this, sizeof(word));
24704 return word;
24705 }
24706 CONSTEXPR uint64_t get_addr() const
24707 {
24708 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
24709 }
24710 CONSTEXPR npu_set_dma0_src_t &set_addr(uint64_t value)
24711 {
24712 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
24713 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
24714 return *this;
24715 }
24716#ifdef NPU_DISASSEMBLE
24717 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24718 {
24719 std::stringstream saddr;
24720 saddr << std::hex << "0x" << get_addr();
24721 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
24722 }
24723#endif
24724#endif
24725 };
24726 // DMA user channel 0 destination byte offset from DMA0_DST_REGION
24727 struct npu_set_dma0_dst_t
24728 {
24729#ifdef __cplusplus
24730 private:
24731#endif
24732 uint32_t opcode : 10; // opcode
24733 uint32_t reserved0 : 4;
24734 uint32_t control : 2; // control
24735 uint32_t addr_hi : 8; // address extension
24736 uint32_t reserved1 : 8;
24737 uint32_t addr_lo : 32; // address offset
24738#ifdef __cplusplus
24739 public:
24740 npu_set_dma0_dst_t(uint64_t _addr) :
24741 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST)), reserved0(0),
24742 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
24743 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
24744 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
24745 {
24746 }
24748 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST)), reserved0(0),
24749 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24750 {
24751 }
24752 CONSTEXPR bool valid() const
24753 {
24754 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST) && control >= 1 &&
24755 control <= 2;
24756 }
24757 CONSTEXPR void init()
24758 {
24759 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST);
24760 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24761 }
24762 operator uint64_t()
24763 {
24764 uint64_t word;
24765 std::memcpy(&word, this, sizeof(word));
24766 return word;
24767 }
24768 CONSTEXPR uint64_t get_addr() const
24769 {
24770 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
24771 }
24772 CONSTEXPR npu_set_dma0_dst_t &set_addr(uint64_t value)
24773 {
24774 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
24775 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
24776 return *this;
24777 }
24778#ifdef NPU_DISASSEMBLE
24779 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24780 {
24781 std::stringstream saddr;
24782 saddr << std::hex << "0x" << get_addr();
24783 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
24784 }
24785#endif
24786#endif
24787 };
24788 // DMA user channel 0 transfer length in bytes for each 1D transfer
24789 struct npu_set_dma0_len_t
24790 {
24791#ifdef __cplusplus
24792 private:
24793#endif
24794 uint32_t opcode : 10; // opcode
24795 uint32_t reserved0 : 4;
24796 uint32_t control : 2; // control
24797 uint32_t addr_hi : 8; // address extension
24798 uint32_t reserved1 : 8;
24799 uint32_t addr_lo : 32; // address offset
24800#ifdef __cplusplus
24801 public:
24802 npu_set_dma0_len_t(uint64_t _addr) :
24803 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN)), reserved0(0),
24804 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
24805 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
24806 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
24807 {
24808 }
24810 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN)), reserved0(0),
24811 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24812 {
24813 }
24814 CONSTEXPR bool valid() const
24815 {
24816 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN) && control >= 1 &&
24817 control <= 2;
24818 }
24819 CONSTEXPR void init()
24820 {
24821 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN);
24822 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24823 }
24824 operator uint64_t()
24825 {
24826 uint64_t word;
24827 std::memcpy(&word, this, sizeof(word));
24828 return word;
24829 }
24830 CONSTEXPR uint64_t get_addr() const
24831 {
24832 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
24833 }
24834 CONSTEXPR npu_set_dma0_len_t &set_addr(uint64_t value)
24835 {
24836 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
24837 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
24838 return *this;
24839 }
24840#ifdef NPU_DISASSEMBLE
24841 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24842 {
24843 std::stringstream saddr;
24844 saddr << std::hex << "0x" << get_addr();
24845 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
24846 }
24847#endif
24848#endif
24849 };
24850 // byte distance to skip after each inner (1D) transfer (2D/3D mode) (any alignment)
24852 {
24853#ifdef __cplusplus
24854 private:
24855#endif
24856 uint32_t opcode : 10; // opcode
24857 uint32_t reserved0 : 4;
24858 uint32_t control : 2; // control
24859 uint32_t addr_hi : 8; // address extension
24860 uint32_t reserved1 : 8;
24861 uint32_t addr_lo : 32; // address offset
24862#ifdef __cplusplus
24863 public:
24864 npu_set_dma0_skip0_t(uint64_t _addr) :
24865 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0)), reserved0(0),
24866 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
24867 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
24868 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
24869 {
24870 }
24872 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0)), reserved0(0),
24873 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24874 {
24875 }
24876 CONSTEXPR bool valid() const
24877 {
24878 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0) && control >= 1 &&
24879 control <= 2;
24880 }
24881 CONSTEXPR void init()
24882 {
24883 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0);
24884 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24885 }
24886 operator uint64_t()
24887 {
24888 uint64_t word;
24889 std::memcpy(&word, this, sizeof(word));
24890 return word;
24891 }
24892 CONSTEXPR uint64_t get_addr() const
24893 {
24894 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
24895 }
24896 CONSTEXPR npu_set_dma0_skip0_t &set_addr(uint64_t value)
24897 {
24898 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
24899 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
24900 return *this;
24901 }
24902#ifdef NPU_DISASSEMBLE
24903 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24904 {
24905 std::stringstream saddr;
24906 saddr << std::hex << "0x" << get_addr();
24907 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
24908 }
24909#endif
24910#endif
24911 };
24912 // byte distance to skip after each 2D transfer (3D mode) (any alignment)
24914 {
24915#ifdef __cplusplus
24916 private:
24917#endif
24918 uint32_t opcode : 10; // opcode
24919 uint32_t reserved0 : 4;
24920 uint32_t control : 2; // control
24921 uint32_t addr_hi : 8; // address extension
24922 uint32_t reserved1 : 8;
24923 uint32_t addr_lo : 32; // address offset
24924#ifdef __cplusplus
24925 public:
24926 npu_set_dma0_skip1_t(uint64_t _addr) :
24927 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1)), reserved0(0),
24928 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
24929 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
24930 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
24931 {
24932 }
24934 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1)), reserved0(0),
24935 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24936 {
24937 }
24938 CONSTEXPR bool valid() const
24939 {
24940 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1) && control >= 1 &&
24941 control <= 2;
24942 }
24943 CONSTEXPR void init()
24944 {
24945 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1);
24946 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24947 }
24948 operator uint64_t()
24949 {
24950 uint64_t word;
24951 std::memcpy(&word, this, sizeof(word));
24952 return word;
24953 }
24954 CONSTEXPR uint64_t get_addr() const
24955 {
24956 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
24957 }
24958 CONSTEXPR npu_set_dma0_skip1_t &set_addr(uint64_t value)
24959 {
24960 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
24961 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
24962 return *this;
24963 }
24964#ifdef NPU_DISASSEMBLE
24965 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
24966 {
24967 std::stringstream saddr;
24968 saddr << std::hex << "0x" << get_addr();
24969 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
24970 }
24971#endif
24972#endif
24973 };
24974 // IFM2 Tile 0 address
24976 {
24977#ifdef __cplusplus
24978 private:
24979#endif
24980 uint32_t opcode : 10; // opcode
24981 uint32_t reserved0 : 4;
24982 uint32_t control : 2; // control
24983 uint32_t addr_hi : 8; // address extension
24984 uint32_t reserved1 : 8;
24985 uint32_t addr_lo : 32; // address offset
24986#ifdef __cplusplus
24987 public:
24988 npu_set_ifm2_base0_t(uint64_t _addr) :
24989 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0)), reserved0(0),
24990 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
24991 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
24992 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
24993 {
24994 }
24996 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0)), reserved0(0),
24997 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24998 {
24999 }
25000 CONSTEXPR bool valid() const
25001 {
25002 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0) && control >= 1 &&
25003 control <= 2;
25004 }
25005 CONSTEXPR void init()
25006 {
25007 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0);
25008 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25009 }
25010 operator uint64_t()
25011 {
25012 uint64_t word;
25013 std::memcpy(&word, this, sizeof(word));
25014 return word;
25015 }
25016 CONSTEXPR uint64_t get_addr() const
25017 {
25018 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
25019 }
25020 CONSTEXPR npu_set_ifm2_base0_t &set_addr(uint64_t value)
25021 {
25022 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
25023 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
25024 return *this;
25025 }
25026#ifdef NPU_DISASSEMBLE
25027 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25028 {
25029 std::stringstream saddr;
25030 saddr << std::hex << "0x" << get_addr();
25031 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
25032 }
25033#endif
25034#endif
25035 };
25036 // IFM2 Tile 1 address
25038 {
25039#ifdef __cplusplus
25040 private:
25041#endif
25042 uint32_t opcode : 10; // opcode
25043 uint32_t reserved0 : 4;
25044 uint32_t control : 2; // control
25045 uint32_t addr_hi : 8; // address extension
25046 uint32_t reserved1 : 8;
25047 uint32_t addr_lo : 32; // address offset
25048#ifdef __cplusplus
25049 public:
25050 npu_set_ifm2_base1_t(uint64_t _addr) :
25051 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1)), reserved0(0),
25052 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
25053 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
25054 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
25055 {
25056 }
25058 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1)), reserved0(0),
25059 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25060 {
25061 }
25062 CONSTEXPR bool valid() const
25063 {
25064 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1) && control >= 1 &&
25065 control <= 2;
25066 }
25067 CONSTEXPR void init()
25068 {
25069 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1);
25070 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25071 }
25072 operator uint64_t()
25073 {
25074 uint64_t word;
25075 std::memcpy(&word, this, sizeof(word));
25076 return word;
25077 }
25078 CONSTEXPR uint64_t get_addr() const
25079 {
25080 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
25081 }
25082 CONSTEXPR npu_set_ifm2_base1_t &set_addr(uint64_t value)
25083 {
25084 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
25085 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
25086 return *this;
25087 }
25088#ifdef NPU_DISASSEMBLE
25089 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25090 {
25091 std::stringstream saddr;
25092 saddr << std::hex << "0x" << get_addr();
25093 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
25094 }
25095#endif
25096#endif
25097 };
25098 // IFM2 Tile 2 address
25100 {
25101#ifdef __cplusplus
25102 private:
25103#endif
25104 uint32_t opcode : 10; // opcode
25105 uint32_t reserved0 : 4;
25106 uint32_t control : 2; // control
25107 uint32_t addr_hi : 8; // address extension
25108 uint32_t reserved1 : 8;
25109 uint32_t addr_lo : 32; // address offset
25110#ifdef __cplusplus
25111 public:
25112 npu_set_ifm2_base2_t(uint64_t _addr) :
25113 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2)), reserved0(0),
25114 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
25115 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
25116 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
25117 {
25118 }
25120 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2)), reserved0(0),
25121 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25122 {
25123 }
25124 CONSTEXPR bool valid() const
25125 {
25126 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2) && control >= 1 &&
25127 control <= 2;
25128 }
25129 CONSTEXPR void init()
25130 {
25131 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2);
25132 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25133 }
25134 operator uint64_t()
25135 {
25136 uint64_t word;
25137 std::memcpy(&word, this, sizeof(word));
25138 return word;
25139 }
25140 CONSTEXPR uint64_t get_addr() const
25141 {
25142 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
25143 }
25144 CONSTEXPR npu_set_ifm2_base2_t &set_addr(uint64_t value)
25145 {
25146 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
25147 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
25148 return *this;
25149 }
25150#ifdef NPU_DISASSEMBLE
25151 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25152 {
25153 std::stringstream saddr;
25154 saddr << std::hex << "0x" << get_addr();
25155 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
25156 }
25157#endif
25158#endif
25159 };
25160 // IFM2 Tile 3 address
25162 {
25163#ifdef __cplusplus
25164 private:
25165#endif
25166 uint32_t opcode : 10; // opcode
25167 uint32_t reserved0 : 4;
25168 uint32_t control : 2; // control
25169 uint32_t addr_hi : 8; // address extension
25170 uint32_t reserved1 : 8;
25171 uint32_t addr_lo : 32; // address offset
25172#ifdef __cplusplus
25173 public:
25174 npu_set_ifm2_base3_t(uint64_t _addr) :
25175 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3)), reserved0(0),
25176 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
25177 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
25178 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
25179 {
25180 }
25182 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3)), reserved0(0),
25183 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25184 {
25185 }
25186 CONSTEXPR bool valid() const
25187 {
25188 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3) && control >= 1 &&
25189 control <= 2;
25190 }
25191 CONSTEXPR void init()
25192 {
25193 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3);
25194 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25195 }
25196 operator uint64_t()
25197 {
25198 uint64_t word;
25199 std::memcpy(&word, this, sizeof(word));
25200 return word;
25201 }
25202 CONSTEXPR uint64_t get_addr() const
25203 {
25204 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
25205 }
25206 CONSTEXPR npu_set_ifm2_base3_t &set_addr(uint64_t value)
25207 {
25208 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
25209 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
25210 return *this;
25211 }
25212#ifdef NPU_DISASSEMBLE
25213 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25214 {
25215 std::stringstream saddr;
25216 saddr << std::hex << "0x" << get_addr();
25217 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
25218 }
25219#endif
25220#endif
25221 };
25222 // IFM2 byte stride between horizontal values
25224 {
25225#ifdef __cplusplus
25226 private:
25227#endif
25228 uint32_t opcode : 10; // opcode
25229 uint32_t reserved0 : 4;
25230 uint32_t control : 2; // control
25231 uint32_t addr_hi : 8; // address extension
25232 uint32_t reserved1 : 8;
25233 uint32_t addr_lo : 32; // address offset
25234#ifdef __cplusplus
25235 public:
25236 npu_set_ifm2_stride_x_t(uint64_t _addr) :
25237 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X)), reserved0(0),
25238 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
25239 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
25240 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
25241 {
25242 }
25244 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X)), reserved0(0),
25245 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25246 {
25247 }
25248 CONSTEXPR bool valid() const
25249 {
25250 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X) && control >= 1 &&
25251 control <= 2;
25252 }
25253 CONSTEXPR void init()
25254 {
25255 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X);
25256 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25257 }
25258 operator uint64_t()
25259 {
25260 uint64_t word;
25261 std::memcpy(&word, this, sizeof(word));
25262 return word;
25263 }
25264 CONSTEXPR uint64_t get_addr() const
25265 {
25266 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
25267 }
25268 CONSTEXPR npu_set_ifm2_stride_x_t &set_addr(uint64_t value)
25269 {
25270 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
25271 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
25272 return *this;
25273 }
25274#ifdef NPU_DISASSEMBLE
25275 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25276 {
25277 std::stringstream saddr;
25278 saddr << std::hex << "0x" << get_addr();
25279 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
25280 }
25281#endif
25282#endif
25283 };
25284 // IFM2 byte stride between vertical values
25286 {
25287#ifdef __cplusplus
25288 private:
25289#endif
25290 uint32_t opcode : 10; // opcode
25291 uint32_t reserved0 : 4;
25292 uint32_t control : 2; // control
25293 uint32_t addr_hi : 8; // address extension
25294 uint32_t reserved1 : 8;
25295 uint32_t addr_lo : 32; // address offset
25296#ifdef __cplusplus
25297 public:
25298 npu_set_ifm2_stride_y_t(uint64_t _addr) :
25299 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y)), reserved0(0),
25300 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
25301 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
25302 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
25303 {
25304 }
25306 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y)), reserved0(0),
25307 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25308 {
25309 }
25310 CONSTEXPR bool valid() const
25311 {
25312 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y) && control >= 1 &&
25313 control <= 2;
25314 }
25315 CONSTEXPR void init()
25316 {
25317 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y);
25318 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25319 }
25320 operator uint64_t()
25321 {
25322 uint64_t word;
25323 std::memcpy(&word, this, sizeof(word));
25324 return word;
25325 }
25326 CONSTEXPR uint64_t get_addr() const
25327 {
25328 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
25329 }
25330 CONSTEXPR npu_set_ifm2_stride_y_t &set_addr(uint64_t value)
25331 {
25332 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
25333 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
25334 return *this;
25335 }
25336#ifdef NPU_DISASSEMBLE
25337 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25338 {
25339 std::stringstream saddr;
25340 saddr << std::hex << "0x" << get_addr();
25341 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
25342 }
25343#endif
25344#endif
25345 };
25346 // IFM2 byte stride between channel blocks (of 16 bytes each block)
25348 {
25349#ifdef __cplusplus
25350 private:
25351#endif
25352 uint32_t opcode : 10; // opcode
25353 uint32_t reserved0 : 4;
25354 uint32_t control : 2; // control
25355 uint32_t addr_hi : 8; // address extension
25356 uint32_t reserved1 : 8;
25357 uint32_t addr_lo : 32; // address offset
25358#ifdef __cplusplus
25359 public:
25360 npu_set_ifm2_stride_c_t(uint64_t _addr) :
25361 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C)), reserved0(0),
25362 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
25363 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
25364 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
25365 {
25366 }
25368 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C)), reserved0(0),
25369 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25370 {
25371 }
25372 CONSTEXPR bool valid() const
25373 {
25374 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C) && control >= 1 &&
25375 control <= 2;
25376 }
25377 CONSTEXPR void init()
25378 {
25379 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C);
25380 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25381 }
25382 operator uint64_t()
25383 {
25384 uint64_t word;
25385 std::memcpy(&word, this, sizeof(word));
25386 return word;
25387 }
25388 CONSTEXPR uint64_t get_addr() const
25389 {
25390 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
25391 }
25392 CONSTEXPR npu_set_ifm2_stride_c_t &set_addr(uint64_t value)
25393 {
25394 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
25395 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
25396 return *this;
25397 }
25398#ifdef NPU_DISASSEMBLE
25399 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25400 {
25401 std::stringstream saddr;
25402 saddr << std::hex << "0x" << get_addr();
25403 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
25404 }
25405#endif
25406#endif
25407 };
25408 // Weight stream byte offset in WEIGHT_REGION for core 1
25410 {
25411#ifdef __cplusplus
25412 private:
25413#endif
25414 uint32_t opcode : 10; // opcode
25415 uint32_t reserved0 : 4;
25416 uint32_t control : 2; // control
25417 uint32_t addr_hi : 8; // address extension
25418 uint32_t reserved1 : 8;
25419 uint32_t addr_lo : 32; // address offset
25420#ifdef __cplusplus
25421 public:
25422 npu_set_weight1_base_t(uint64_t _addr) :
25423 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE)), reserved0(0),
25424 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
25425 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
25426 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
25427 {
25428 }
25430 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE)), reserved0(0),
25431 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25432 {
25433 }
25434 CONSTEXPR bool valid() const
25435 {
25436 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE) && control >= 1 &&
25437 control <= 2;
25438 }
25439 CONSTEXPR void init()
25440 {
25441 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE);
25442 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25443 }
25444 operator uint64_t()
25445 {
25446 uint64_t word;
25447 std::memcpy(&word, this, sizeof(word));
25448 return word;
25449 }
25450 CONSTEXPR uint64_t get_addr() const
25451 {
25452 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
25453 }
25454 CONSTEXPR npu_set_weight1_base_t &set_addr(uint64_t value)
25455 {
25456 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
25457 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
25458 return *this;
25459 }
25460#ifdef NPU_DISASSEMBLE
25461 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25462 {
25463 std::stringstream saddr;
25464 saddr << std::hex << "0x" << get_addr();
25465 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
25466 }
25467#endif
25468#endif
25469 };
25470 // Weight stream byte length for core 1
25472 {
25473#ifdef __cplusplus
25474 private:
25475#endif
25476 uint32_t opcode : 10; // opcode
25477 uint32_t reserved0 : 4;
25478 uint32_t control : 2; // control
25479 uint32_t reserved1 : 16;
25480 uint32_t length : 32; // Weight stream byte length
25481#ifdef __cplusplus
25482 public:
25483 npu_set_weight1_length_t(uint32_t _length) :
25484 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH)), reserved0(0),
25485 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(_length)
25486 {
25487 }
25489 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH)), reserved0(0),
25490 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0)
25491 {
25492 }
25493 CONSTEXPR bool valid() const
25494 {
25495 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH) &&
25496 control >= 1 && control <= 2;
25497 }
25498 CONSTEXPR void init()
25499 {
25500 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH);
25501 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25502 }
25503 operator uint64_t()
25504 {
25505 uint64_t word;
25506 std::memcpy(&word, this, sizeof(word));
25507 return word;
25508 }
25509 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const
25510 {
25511 return static_cast<NPU_NAMESPACE::cmd1_opcode>(opcode);
25512 }
25513 CONSTEXPR npu_set_weight1_length_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value)
25514 {
25515 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
25516 return *this;
25517 }
25518 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
25519 {
25520 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
25521 }
25522 CONSTEXPR npu_set_weight1_length_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
25523 {
25524 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
25525 return *this;
25526 }
25527 CONSTEXPR uint32_t get_length() const
25528 {
25529 return static_cast<uint32_t>(length);
25530 }
25531 CONSTEXPR npu_set_weight1_length_t &set_length(uint32_t value)
25532 {
25533 length = value;
25534 return *this;
25535 }
25536#ifdef NPU_DISASSEMBLE
25537 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25538 {
25539 fields.push_back(std::make_pair<std::string, std::string>("length", std::to_string(length)));
25540 }
25541#endif
25542#endif
25543 };
25544 // Scale and bias stream input byte offset from SCALE_REGION for core 1
25546 {
25547#ifdef __cplusplus
25548 private:
25549#endif
25550 uint32_t opcode : 10; // opcode
25551 uint32_t reserved0 : 4;
25552 uint32_t control : 2; // control
25553 uint32_t addr_hi : 8; // address extension
25554 uint32_t reserved1 : 8;
25555 uint32_t addr_lo : 32; // address offset
25556#ifdef __cplusplus
25557 public:
25558 npu_set_scale1_base_t(uint64_t _addr) :
25559 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE)), reserved0(0),
25560 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)),
25561 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::max())), reserved1(0),
25562 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::max()))
25563 {
25564 }
25566 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE)), reserved0(0),
25567 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25568 {
25569 }
25570 CONSTEXPR bool valid() const
25571 {
25572 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE) && control >= 1 &&
25573 control <= 2;
25574 }
25575 CONSTEXPR void init()
25576 {
25577 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE);
25578 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25579 }
25580 operator uint64_t()
25581 {
25582 uint64_t word;
25583 std::memcpy(&word, this, sizeof(word));
25584 return word;
25585 }
25586 CONSTEXPR uint64_t get_addr() const
25587 {
25588 return (static_cast<uint64_t>(addr_hi) << 32) | addr_lo;
25589 }
25590 CONSTEXPR npu_set_scale1_base_t &set_addr(uint64_t value)
25591 {
25592 addr_lo = static_cast<uint32_t>((value)&std::numeric_limits<uint64_t>::max());
25593 addr_hi = static_cast<uint8_t>((value >> 32) & std::numeric_limits<uint64_t>::max());
25594 return *this;
25595 }
25596#ifdef NPU_DISASSEMBLE
25597 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25598 {
25599 std::stringstream saddr;
25600 saddr << std::hex << "0x" << get_addr();
25601 fields.push_back(std::make_pair<std::string, std::string>("addr", saddr.str()));
25602 }
25603#endif
25604#endif
25605 };
25606 // Scale and bias stream input byte length for core 1
25608 {
25609#ifdef __cplusplus
25610 private:
25611#endif
25612 uint32_t opcode : 10; // opcode
25613 uint32_t reserved0 : 4;
25614 uint32_t control : 2; // control
25615 uint32_t reserved1 : 16;
25616 uint32_t length : 20; // Scale and bias stream byte length
25617 uint32_t reserved2 : 12;
25618#ifdef __cplusplus
25619 public:
25620 npu_set_scale1_length_t(uint32_t _length) :
25621 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH)), reserved0(0),
25622 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0),
25623 length(_length & ((1U << 20) - 1)), reserved2(0)
25624 {
25625 }
25627 opcode(static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH)), reserved0(0),
25628 control(static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0), reserved2(0)
25629 {
25630 }
25631 CONSTEXPR bool valid() const
25632 {
25633 return opcode == static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH) && control >= 1 &&
25634 control <= 2;
25635 }
25636 CONSTEXPR void init()
25637 {
25638 opcode = static_cast<uint16_t>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH);
25639 control = static_cast<uint8_t>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25640 }
25641 operator uint64_t()
25642 {
25643 uint64_t word;
25644 std::memcpy(&word, this, sizeof(word));
25645 return word;
25646 }
25647 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode() const
25648 {
25649 return static_cast<NPU_NAMESPACE::cmd1_opcode>(opcode);
25650 }
25651 CONSTEXPR npu_set_scale1_length_t &set_opcode(NPU_NAMESPACE::cmd1_opcode value)
25652 {
25653 opcode = static_cast<uint16_t>(value) & ((1U << 10) - 1);
25654 return *this;
25655 }
25656 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control() const
25657 {
25658 return static_cast<NPU_NAMESPACE::cmd_ctrl>(control);
25659 }
25660 CONSTEXPR npu_set_scale1_length_t &set_control(NPU_NAMESPACE::cmd_ctrl value)
25661 {
25662 control = static_cast<uint8_t>(value) & ((1U << 2) - 1);
25663 return *this;
25664 }
25665 CONSTEXPR uint32_t get_length() const
25666 {
25667 return static_cast<uint32_t>(length);
25668 }
25669 CONSTEXPR npu_set_scale1_length_t &set_length(uint32_t value)
25670 {
25671 length = value & ((1U << 20) - 1);
25672 return *this;
25673 }
25674#ifdef NPU_DISASSEMBLE
25675 void disassemble(std::vector<std::pair<std::string, std::string>> &fields) const
25676 {
25677 fields.push_back(std::make_pair<std::string, std::string>("length", std::to_string(length)));
25678 }
25679#endif
25680#endif
25681 };
25682#ifdef __cplusplus
25683};
25684#endif
25685#define NPU_OP_STRUCTS \
25686 NPU_OP_(stop) \
25687 NPU_OP_(irq) \
25688 NPU_OP_(conv) \
25689 NPU_OP_(depthwise) \
25690 NPU_OP_(pool) \
25691 NPU_OP_(elementwise) \
25692 NPU_OP_(dma_start) \
25693 NPU_OP_(dma_wait) \
25694 NPU_OP_(kernel_wait) \
25695 NPU_OP_(pmu_mask)
25696
25697#define NPU_SET_STRUCTS \
25698 NPU_SET_(ifm_pad_top) \
25699 NPU_SET_(ifm_pad_left) \
25700 NPU_SET_(ifm_pad_right) \
25701 NPU_SET_(ifm_pad_bottom) \
25702 NPU_SET_(ifm_depth_m1) \
25703 NPU_SET_(ifm_precision) \
25704 NPU_SET_(ifm_upscale) \
25705 NPU_SET_(ifm_zero_point) \
25706 NPU_SET_(ifm_width0_m1) \
25707 NPU_SET_(ifm_height0_m1) \
25708 NPU_SET_(ifm_height1_m1) \
25709 NPU_SET_(ifm_ib_end) \
25710 NPU_SET_(ifm_region) \
25711 NPU_SET_(ofm_width_m1) \
25712 NPU_SET_(ofm_height_m1) \
25713 NPU_SET_(ofm_depth_m1) \
25714 NPU_SET_(ofm_precision) \
25715 NPU_SET_(ofm_blk_width_m1) \
25716 NPU_SET_(ofm_blk_height_m1) \
25717 NPU_SET_(ofm_blk_depth_m1) \
25718 NPU_SET_(ofm_zero_point) \
25719 NPU_SET_(ofm_width0_m1) \
25720 NPU_SET_(ofm_height0_m1) \
25721 NPU_SET_(ofm_height1_m1) \
25722 NPU_SET_(ofm_region) \
25723 NPU_SET_(kernel_width_m1) \
25724 NPU_SET_(kernel_height_m1) \
25725 NPU_SET_(kernel_stride) \
25726 NPU_SET_(parallel_mode) \
25727 NPU_SET_(acc_format) \
25728 NPU_SET_(activation) \
25729 NPU_SET_(activation_min) \
25730 NPU_SET_(activation_max) \
25731 NPU_SET_(weight_region) \
25732 NPU_SET_(scale_region) \
25733 NPU_SET_(ab_start) \
25734 NPU_SET_(blockdep) \
25735 NPU_SET_(dma0_src_region) \
25736 NPU_SET_(dma0_dst_region) \
25737 NPU_SET_(dma0_size0) \
25738 NPU_SET_(dma0_size1) \
25739 NPU_SET_(ifm2_broadcast) \
25740 NPU_SET_(ifm2_scalar) \
25741 NPU_SET_(ifm2_precision) \
25742 NPU_SET_(ifm2_zero_point) \
25743 NPU_SET_(ifm2_width0_m1) \
25744 NPU_SET_(ifm2_height0_m1) \
25745 NPU_SET_(ifm2_height1_m1) \
25746 NPU_SET_(ifm2_ib_start) \
25747 NPU_SET_(ifm2_region) \
25748 NPU_SET_(ifm_base0) \
25749 NPU_SET_(ifm_base1) \
25750 NPU_SET_(ifm_base2) \
25751 NPU_SET_(ifm_base3) \
25752 NPU_SET_(ifm_stride_x) \
25753 NPU_SET_(ifm_stride_y) \
25754 NPU_SET_(ifm_stride_c) \
25755 NPU_SET_(ofm_base0) \
25756 NPU_SET_(ofm_base1) \
25757 NPU_SET_(ofm_base2) \
25758 NPU_SET_(ofm_base3) \
25759 NPU_SET_(ofm_stride_x) \
25760 NPU_SET_(ofm_stride_y) \
25761 NPU_SET_(ofm_stride_c) \
25762 NPU_SET_(weight_base) \
25763 NPU_SET_(weight_length) \
25764 NPU_SET_(scale_base) \
25765 NPU_SET_(scale_length) \
25766 NPU_SET_(ofm_scale) \
25767 NPU_SET_(opa_scale) \
25768 NPU_SET_(opb_scale) \
25769 NPU_SET_(dma0_src) \
25770 NPU_SET_(dma0_dst) \
25771 NPU_SET_(dma0_len) \
25772 NPU_SET_(dma0_skip0) \
25773 NPU_SET_(dma0_skip1) \
25774 NPU_SET_(ifm2_base0) \
25775 NPU_SET_(ifm2_base1) \
25776 NPU_SET_(ifm2_base2) \
25777 NPU_SET_(ifm2_base3) \
25778 NPU_SET_(ifm2_stride_x) \
25779 NPU_SET_(ifm2_stride_y) \
25780 NPU_SET_(ifm2_stride_c) \
25781 NPU_SET_(weight1_base) \
25782 NPU_SET_(weight1_length) \
25783 NPU_SET_(scale1_base) \
25784 NPU_SET_(scale1_length)
25785
25786#define EXPAND_ACC_FORMAT(FUNC, SEP) FUNC(acc_format, I32) SEP FUNC(acc_format, I40) SEP FUNC(acc_format, F16)
25787
25788#define EXPAND_ACTIVATION_CLIP_RANGE(FUNC, SEP) \
25789 FUNC(activation_clip_range, OFM_PRECISION) \
25790 SEP FUNC(activation_clip_range, FORCE_UINT8) SEP FUNC(activation_clip_range, FORCE_INT8) \
25791 SEP FUNC(activation_clip_range, FORCE_INT16)
25792
25793#define EXPAND_ACTIVATION_FORMAT(FUNC, SEP) FUNC(activation_format, NHWC) SEP FUNC(activation_format, NHCWB16)
25794
25795#define EXPAND_ACTIVATION_FUNCTION(FUNC, SEP) \
25796 FUNC(activation_function, RELU) \
25797 SEP FUNC(activation_function, TANH) SEP FUNC(activation_function, SIGMOID) SEP FUNC(activation_function, TABLE_0) \
25798 SEP FUNC(activation_function, TABLE_1) SEP FUNC(activation_function, TABLE_2) \
25799 SEP FUNC(activation_function, TABLE_3) SEP FUNC(activation_function, TABLE_4) \
25800 SEP FUNC(activation_function, TABLE_5) SEP FUNC(activation_function, TABLE_6) \
25801 SEP FUNC(activation_function, TABLE_7)
25802
25803#define EXPAND_ACTIVATION_PRECISION(FUNC, SEP) \
25804 FUNC(activation_precision, B8) \
25805 SEP FUNC(activation_precision, B16) SEP FUNC(activation_precision, B32) SEP FUNC(activation_precision, B64)
25806
25807#define EXPAND_ACTIVATION_TYPE(FUNC, SEP) FUNC(activation_type, UNSIGNED) SEP FUNC(activation_type, SIGNED)
25808
25809#define EXPAND_AXI_MEM_ENCODING(FUNC, SEP) \
25810 FUNC(axi_mem_encoding, DEVICE_NON_BUFFERABLE) \
25811 SEP FUNC(axi_mem_encoding, DEVICE_BUFFERABLE) SEP FUNC(axi_mem_encoding, NORMAL_NON_CACHEABLE_NON_BUFFERABLE) \
25812 SEP FUNC(axi_mem_encoding, NORMAL_NON_CACHEABLE_BUFFERABLE) \
25813 SEP FUNC(axi_mem_encoding, WRITE_THROUGH_NO_ALLOCATE) \
25814 SEP FUNC(axi_mem_encoding, WRITE_THROUGH_READ_ALLOCATE) \
25815 SEP FUNC(axi_mem_encoding, WRITE_THROUGH_WRITE_ALLOCATE) \
25816 SEP FUNC(axi_mem_encoding, WRITE_THROUGH_READ_AND_WRITE_ALLOCATE) \
25817 SEP FUNC(axi_mem_encoding, WRITE_BACK_NO_ALLOCATE) \
25818 SEP FUNC(axi_mem_encoding, WRITE_BACK_READ_ALLOCATE) \
25819 SEP FUNC(axi_mem_encoding, WRITE_BACK_WRITE_ALLOCATE) \
25820 SEP FUNC(axi_mem_encoding, WRITE_BACK_READ_AND_WRITE_ALLOCATE)
25821
25822#define EXPAND_BROADCAST_MODE(FUNC, SEP) FUNC(broadcast_mode, DISABLE) SEP FUNC(broadcast_mode, ENABLE)
25823
25824#define EXPAND_CMD0_OPCODE(FUNC, SEP) \
25825 FUNC(cmd0_opcode, NPU_OP_STOP) \
25826 SEP FUNC(cmd0_opcode, NPU_OP_IRQ) SEP FUNC(cmd0_opcode, NPU_OP_CONV) SEP FUNC( \
25827 cmd0_opcode, NPU_OP_DEPTHWISE) SEP FUNC(cmd0_opcode, NPU_OP_POOL) SEP FUNC(cmd0_opcode, NPU_OP_ELEMENTWISE) \
25828 SEP FUNC(cmd0_opcode, NPU_OP_DMA_START) SEP FUNC(cmd0_opcode, NPU_OP_DMA_WAIT) SEP FUNC( \
25829 cmd0_opcode, NPU_OP_KERNEL_WAIT) SEP FUNC(cmd0_opcode, NPU_OP_PMU_MASK) SEP FUNC(cmd0_opcode, \
25830 NPU_SET_IFM_PAD_TOP) \
25831 SEP FUNC(cmd0_opcode, NPU_SET_IFM_PAD_LEFT) SEP FUNC(cmd0_opcode, NPU_SET_IFM_PAD_RIGHT) SEP FUNC( \
25832 cmd0_opcode, NPU_SET_IFM_PAD_BOTTOM) SEP FUNC(cmd0_opcode, \
25833 NPU_SET_IFM_DEPTH_M1) SEP FUNC(cmd0_opcode, \
25834 NPU_SET_IFM_PRECISION) \
25835 SEP FUNC(cmd0_opcode, NPU_SET_IFM_UPSCALE) SEP FUNC(cmd0_opcode, NPU_SET_IFM_ZERO_POINT) SEP FUNC( \
25836 cmd0_opcode, NPU_SET_IFM_WIDTH0_M1) SEP FUNC(cmd0_opcode, NPU_SET_IFM_HEIGHT0_M1) \
25837 SEP FUNC(cmd0_opcode, NPU_SET_IFM_HEIGHT1_M1) SEP FUNC(cmd0_opcode, NPU_SET_IFM_IB_END) SEP FUNC( \
25838 cmd0_opcode, NPU_SET_IFM_REGION) SEP FUNC(cmd0_opcode, NPU_SET_OFM_WIDTH_M1) \
25839 SEP FUNC(cmd0_opcode, NPU_SET_OFM_HEIGHT_M1) SEP FUNC(cmd0_opcode, NPU_SET_OFM_DEPTH_M1) \
25840 SEP FUNC(cmd0_opcode, NPU_SET_OFM_PRECISION) SEP FUNC( \
25841 cmd0_opcode, NPU_SET_OFM_BLK_WIDTH_M1) SEP FUNC(cmd0_opcode, \
25842 NPU_SET_OFM_BLK_HEIGHT_M1) \
25843 SEP FUNC(cmd0_opcode, NPU_SET_OFM_BLK_DEPTH_M1) SEP FUNC( \
25844 cmd0_opcode, NPU_SET_OFM_ZERO_POINT) SEP FUNC(cmd0_opcode, NPU_SET_OFM_WIDTH0_M1) \
25845 SEP FUNC(cmd0_opcode, NPU_SET_OFM_HEIGHT0_M1) SEP FUNC( \
25846 cmd0_opcode, \
25847 NPU_SET_OFM_HEIGHT1_M1) SEP FUNC(cmd0_opcode, NPU_SET_OFM_REGION) \
25848 SEP FUNC(cmd0_opcode, NPU_SET_KERNEL_WIDTH_M1) SEP FUNC( \
25849 cmd0_opcode, \
25850 NPU_SET_KERNEL_HEIGHT_M1) SEP FUNC(cmd0_opcode, NPU_SET_KERNEL_STRIDE) \
25851 SEP FUNC(cmd0_opcode, NPU_SET_PARALLEL_MODE) SEP FUNC( \
25852 cmd0_opcode, \
25853 NPU_SET_ACC_FORMAT) SEP FUNC(cmd0_opcode, NPU_SET_ACTIVATION) \
25854 SEP FUNC(cmd0_opcode, \
25855 NPU_SET_ACTIVATION_MIN) SEP FUNC(cmd0_opcode, \
25856 NPU_SET_ACTIVATION_MAX) \
25857 SEP FUNC(cmd0_opcode, NPU_SET_WEIGHT_REGION) SEP FUNC( \
25858 cmd0_opcode, \
25859 NPU_SET_SCALE_REGION) SEP FUNC(cmd0_opcode, NPU_SET_AB_START) \
25860 SEP FUNC(cmd0_opcode, NPU_SET_BLOCKDEP) \
25861 SEP FUNC(cmd0_opcode, NPU_SET_DMA0_SRC_REGION) SEP FUNC( \
25862 cmd0_opcode, \
25863 NPU_SET_DMA0_DST_REGION) SEP FUNC(cmd0_opcode, \
25864 NPU_SET_DMA0_SIZE0) \
25865 SEP FUNC(cmd0_opcode, NPU_SET_DMA0_SIZE1) SEP FUNC( \
25866 cmd0_opcode, \
25867 NPU_SET_IFM2_BROADCAST) SEP \
25868 FUNC(cmd0_opcode, NPU_SET_IFM2_SCALAR) SEP FUNC( \
25869 cmd0_opcode, \
25870 NPU_SET_IFM2_PRECISION) SEP \
25871 FUNC(cmd0_opcode, NPU_SET_IFM2_ZERO_POINT) SEP \
25872 FUNC(cmd0_opcode, \
25873 NPU_SET_IFM2_WIDTH0_M1) SEP \
25874 FUNC(cmd0_opcode, \
25875 NPU_SET_IFM2_HEIGHT0_M1) SEP \
25876 FUNC(cmd0_opcode, \
25877 NPU_SET_IFM2_HEIGHT1_M1) \
25878 SEP FUNC( \
25879 cmd0_opcode, \
25880 NPU_SET_IFM2_IB_START) \
25881 SEP FUNC( \
25882 cmd0_opcode, \
25883 NPU_SET_IFM2_REGION)
25884
25885#define EXPAND_CMD1_OPCODE(FUNC, SEP) \
25886 FUNC(cmd1_opcode, NPU_SET_IFM_BASE0) \
25887 SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE1) SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE2) \
25888 SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE3) SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_X) \
25889 SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_Y) SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_C) SEP FUNC( \
25890 cmd1_opcode, NPU_SET_OFM_BASE0) SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE1) \
25891 SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE2) SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE3) SEP FUNC( \
25892 cmd1_opcode, NPU_SET_OFM_STRIDE_X) SEP FUNC(cmd1_opcode, NPU_SET_OFM_STRIDE_Y) \
25893 SEP FUNC(cmd1_opcode, NPU_SET_OFM_STRIDE_C) SEP FUNC(cmd1_opcode, NPU_SET_WEIGHT_BASE) SEP FUNC( \
25894 cmd1_opcode, NPU_SET_WEIGHT_LENGTH) SEP FUNC(cmd1_opcode, NPU_SET_SCALE_BASE) \
25895 SEP FUNC(cmd1_opcode, NPU_SET_SCALE_LENGTH) SEP FUNC(cmd1_opcode, NPU_SET_OFM_SCALE) \
25896 SEP FUNC(cmd1_opcode, NPU_SET_OPA_SCALE) SEP FUNC(cmd1_opcode, NPU_SET_OPB_SCALE) \
25897 SEP FUNC(cmd1_opcode, NPU_SET_DMA0_SRC) SEP FUNC(cmd1_opcode, NPU_SET_DMA0_DST) \
25898 SEP FUNC(cmd1_opcode, NPU_SET_DMA0_LEN) SEP FUNC(cmd1_opcode, NPU_SET_DMA0_SKIP0) \
25899 SEP FUNC(cmd1_opcode, NPU_SET_DMA0_SKIP1) SEP FUNC( \
25900 cmd1_opcode, NPU_SET_IFM2_BASE0) SEP FUNC(cmd1_opcode, NPU_SET_IFM2_BASE1) \
25901 SEP FUNC(cmd1_opcode, NPU_SET_IFM2_BASE2) SEP FUNC(cmd1_opcode, \
25902 NPU_SET_IFM2_BASE3) \
25903 SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_X) \
25904 SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_Y) \
25905 SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_C) \
25906 SEP FUNC(cmd1_opcode, NPU_SET_WEIGHT1_BASE) \
25907 SEP FUNC(cmd1_opcode, NPU_SET_WEIGHT1_LENGTH) \
25908 SEP FUNC(cmd1_opcode, NPU_SET_SCALE1_BASE) \
25909 SEP FUNC(cmd1_opcode, NPU_SET_SCALE1_LENGTH)
25910
25911#define EXPAND_CMD_CTRL(FUNC, SEP) FUNC(cmd_ctrl, CMD0_CTRL) SEP FUNC(cmd_ctrl, CMD1_CTRL)
25912
25913#define EXPAND_CUSTOM_DMA(FUNC, SEP) FUNC(custom_dma, NOT_IMPLEMENTED) SEP FUNC(custom_dma, IMPLEMENTED)
25914
25915#define EXPAND_DMA_FAULT_SRC(FUNC, SEP) FUNC(dma_fault_src, AXI_M0) SEP FUNC(dma_fault_src, AXI_M1)
25916
25917#define EXPAND_DMA_REGION_MODE(FUNC, SEP) FUNC(dma_region_mode, EXTERNAL) SEP FUNC(dma_region_mode, INTERNAL)
25918
25919#define EXPAND_DMA_STRIDE_MODE(FUNC, SEP) \
25920 FUNC(dma_stride_mode, D1) SEP FUNC(dma_stride_mode, D2) SEP FUNC(dma_stride_mode, D3)
25921
25922#define EXPAND_ELEMENTWISE_MODE(FUNC, SEP) \
25923 FUNC(elementwise_mode, MUL) \
25924 SEP FUNC(elementwise_mode, ADD) SEP FUNC(elementwise_mode, SUB) SEP FUNC(elementwise_mode, MIN) \
25925 SEP FUNC(elementwise_mode, MAX) SEP FUNC(elementwise_mode, LRELU) SEP FUNC(elementwise_mode, ABS) \
25926 SEP FUNC(elementwise_mode, CLZ) SEP FUNC(elementwise_mode, SHR) SEP FUNC(elementwise_mode, SHL)
25927
25928#define EXPAND_FUNCTIONAL_SAFETY(FUNC, SEP) \
25929 FUNC(functional_safety, NOT_IMPLEMENTED) SEP FUNC(functional_safety, IMPLEMENTED)
25930
25931#define EXPAND_IFM2_OPERAND_ORDER(FUNC, SEP) FUNC(ifm2_operand_order, ORDER_B) SEP FUNC(ifm2_operand_order, ORDER_A)
25932
25933#define EXPAND_IFM_SCALE_MODE(FUNC, SEP) \
25934 FUNC(ifm_scale_mode, OPA_OPB_16) SEP FUNC(ifm_scale_mode, OPA_32) SEP FUNC(ifm_scale_mode, OPB_32)
25935
25936#define EXPAND_IFM_UPSCALE_MODE(FUNC, SEP) \
25937 FUNC(ifm_upscale_mode, NONE) SEP FUNC(ifm_upscale_mode, NEAREST) SEP FUNC(ifm_upscale_mode, ZEROS)
25938
25939#define EXPAND_KERNEL_DECOMPOSITION(FUNC, SEP) FUNC(kernel_decomposition, D8X8) SEP FUNC(kernel_decomposition, D4X4)
25940
25941#define EXPAND_KERNEL_DILATION(FUNC, SEP) FUNC(kernel_dilation, NONE) SEP FUNC(kernel_dilation, X2)
25942
25943#define EXPAND_MAX_BEATS(FUNC, SEP) FUNC(max_beats, B64) SEP FUNC(max_beats, B128) SEP FUNC(max_beats, B256)
25944
25945#define EXPAND_MEM_ATTR(FUNC, SEP) \
25946 FUNC(mem_attr, AXI0_OUTSTANDING_COUNTER0) \
25947 SEP FUNC(mem_attr, AXI0_OUTSTANDING_COUNTER1) SEP FUNC(mem_attr, AXI1_OUTSTANDING_COUNTER2) \
25948 SEP FUNC(mem_attr, AXI1_OUTSTANDING_COUNTER3)
25949
25950#define EXPAND_OFM_SCALE_MODE(FUNC, SEP) FUNC(ofm_scale_mode, PER_CHANNEL) SEP FUNC(ofm_scale_mode, GLOBAL)
25951
25952#define EXPAND_PARALLEL_MODE(FUNC, SEP) FUNC(parallel_mode, SINGLE_CORE) SEP FUNC(parallel_mode, DUAL_CORE_DEPTH)
25953
25954#define EXPAND_PMU_AXI_CHANNEL(FUNC, SEP) \
25955 FUNC(pmu_axi_channel, RD_CMD) \
25956 SEP FUNC(pmu_axi_channel, RD_IFM) SEP FUNC(pmu_axi_channel, RD_WEIGHTS) SEP FUNC(pmu_axi_channel, RD_SCALE_BIAS) \
25957 SEP FUNC(pmu_axi_channel, RD_MEM2MEM) SEP FUNC(pmu_axi_channel, WR_OFM) SEP FUNC(pmu_axi_channel, WR_MEM2MEM)
25958
25959#define EXPAND_PMU_EVENT(FUNC, SEP) \
25960 FUNC(pmu_event, NO_EVENT) \
25961 SEP FUNC(pmu_event, CYCLE) SEP FUNC(pmu_event, NPU_IDLE) SEP FUNC(pmu_event, CC_STALLED_ON_BLOCKDEP) SEP FUNC( \
25962 pmu_event, CC_STALLED_ON_SHRAM_RECONFIG) SEP FUNC(pmu_event, NPU_ACTIVE) SEP FUNC(pmu_event, MAC_ACTIVE) \
25963 SEP FUNC(pmu_event, MAC_ACTIVE_8BIT) SEP FUNC(pmu_event, MAC_ACTIVE_16BIT) SEP FUNC( \
25964 pmu_event, MAC_DPU_ACTIVE) SEP FUNC(pmu_event, MAC_STALLED_BY_WD_ACC) SEP FUNC(pmu_event, \
25965 MAC_STALLED_BY_WD) \
25966 SEP FUNC(pmu_event, MAC_STALLED_BY_ACC) SEP FUNC(pmu_event, MAC_STALLED_BY_IB) SEP FUNC( \
25967 pmu_event, \
25968 MAC_ACTIVE_32BIT) SEP FUNC(pmu_event, \
25969 MAC_STALLED_BY_INT_W) SEP FUNC(pmu_event, \
25970 MAC_STALLED_BY_INT_ACC) SEP FUNC(pmu_event, \
25971 AO_ACTIVE) \
25972 SEP FUNC(pmu_event, AO_ACTIVE_8BIT) SEP FUNC(pmu_event, AO_ACTIVE_16BIT) SEP FUNC( \
25973 pmu_event, AO_STALLED_BY_OFMP_OB) SEP FUNC(pmu_event, AO_STALLED_BY_OFMP) SEP \
25974 FUNC(pmu_event, AO_STALLED_BY_OB) SEP FUNC(pmu_event, AO_STALLED_BY_ACC_IB) SEP FUNC( \
25975 pmu_event, AO_STALLED_BY_ACC) SEP FUNC(pmu_event, AO_STALLED_BY_IB) SEP \
25976 FUNC(pmu_event, WD_ACTIVE) SEP FUNC(pmu_event, WD_STALLED) SEP FUNC(pmu_event, WD_STALLED_BY_WS) SEP FUNC( \
25977 pmu_event, WD_STALLED_BY_WD_BUF) SEP FUNC(pmu_event, \
25978 WD_PARSE_ACTIVE) SEP \
25979 FUNC(pmu_event, WD_PARSE_STALLED) SEP FUNC(pmu_event, WD_PARSE_STALLED_IN) SEP FUNC( \
25980 pmu_event, WD_PARSE_STALLED_OUT) SEP FUNC(pmu_event, \
25981 WD_TRANS_WS) SEP \
25982 FUNC(pmu_event, WD_TRANS_WB) SEP FUNC(pmu_event, WD_TRANS_DW0) SEP FUNC( \
25983 pmu_event, WD_TRANS_DW1) SEP FUNC(pmu_event, \
25984 AXI0_RD_TRANS_ACCEPTED) SEP \
25985 FUNC(pmu_event, AXI0_RD_TRANS_COMPLETED) SEP FUNC(pmu_event, AXI0_RD_DATA_BEAT_RECEIVED) SEP FUNC( \
25986 pmu_event, AXI0_RD_TRAN_REQ_STALLED) SEP FUNC(pmu_event, \
25987 AXI0_WR_TRANS_ACCEPTED) SEP \
25988 FUNC(pmu_event, AXI0_WR_TRANS_COMPLETED_M) SEP FUNC( \
25989 pmu_event, AXI0_WR_TRANS_COMPLETED_S) SEP \
25990 FUNC(pmu_event, AXI0_WR_DATA_BEAT_WRITTEN) SEP FUNC( \
25991 pmu_event, AXI0_WR_TRAN_REQ_STALLED) SEP \
25992 FUNC(pmu_event, AXI0_WR_DATA_BEAT_STALLED) SEP FUNC( \
25993 pmu_event, \
25994 AXI0_ENABLED_CYCLES) SEP FUNC(pmu_event, \
25995 AXI0_RD_STALL_LIMIT) SEP \
25996 FUNC(pmu_event, AXI0_WR_STALL_LIMIT) SEP FUNC( \
25997 pmu_event, \
25998 AXI_LATENCY_ANY) SEP FUNC(pmu_event, \
25999 AXI_LATENCY_32) SEP \
26000 FUNC(pmu_event, \
26001 AXI_LATENCY_64) SEP FUNC(pmu_event, \
26002 AXI_LATENCY_128) SEP \
26003 FUNC(pmu_event, AXI_LATENCY_256) SEP FUNC( \
26004 pmu_event, \
26005 AXI_LATENCY_512) SEP FUNC(pmu_event, \
26006 AXI_LATENCY_1024) SEP \
26007 FUNC(pmu_event, ECC_DMA) SEP FUNC( \
26008 pmu_event, \
26009 ECC_SB0) SEP FUNC(pmu_event, \
26010 AXI1_RD_TRANS_ACCEPTED) SEP \
26011 FUNC(pmu_event, AXI1_RD_TRANS_COMPLETED) SEP FUNC( \
26012 pmu_event, AXI1_RD_DATA_BEAT_RECEIVED) SEP \
26013 FUNC(pmu_event, AXI1_RD_TRAN_REQ_STALLED) SEP FUNC( \
26014 pmu_event, AXI1_WR_TRANS_ACCEPTED) SEP \
26015 FUNC(pmu_event, AXI1_WR_TRANS_COMPLETED_M) SEP FUNC( \
26016 pmu_event, \
26017 AXI1_WR_TRANS_COMPLETED_S) SEP \
26018 FUNC(pmu_event, \
26019 AXI1_WR_DATA_BEAT_WRITTEN) SEP \
26020 FUNC(pmu_event, \
26021 AXI1_WR_TRAN_REQ_STALLED) SEP \
26022 FUNC( \
26023 pmu_event, \
26024 AXI1_WR_DATA_BEAT_STALLED) SEP \
26025 FUNC( \
26026 pmu_event, \
26027 AXI1_ENABLED_CYCLES) SEP \
26028 FUNC( \
26029 pmu_event, \
26030 AXI1_RD_STALL_LIMIT) SEP \
26031 FUNC( \
26032 pmu_event, \
26033 AXI1_WR_STALL_LIMIT) \
26034 SEP FUNC( \
26035 pmu_event, \
26036 ECC_SB1)
26037
26038#define EXPAND_POOLING_MODE(FUNC, SEP) \
26039 FUNC(pooling_mode, MAX) SEP FUNC(pooling_mode, AVERAGE) SEP FUNC(pooling_mode, REDUCE_SUM)
26040
26041#define EXPAND_PRIVILEGE_LEVEL(FUNC, SEP) FUNC(privilege_level, USER) SEP FUNC(privilege_level, PRIVILEGED)
26042
26043#define EXPAND_ROUND_MODE(FUNC, SEP) FUNC(round_mode, DBL) SEP FUNC(round_mode, TRUNCATE) SEP FUNC(round_mode, NATURAL)
26044
26045#define EXPAND_SECURITY_LEVEL(FUNC, SEP) FUNC(security_level, SECURE) SEP FUNC(security_level, NON_SECURE)
26046
26047#define EXPAND_STATE(FUNC, SEP) FUNC(state, STOPPED) SEP FUNC(state, RUNNING)
26048
26049#define EXPAND_WD_CORE_SLICE_STATE(FUNC, SEP) \
26050 FUNC(wd_core_slice_state, HEADER) SEP FUNC(wd_core_slice_state, PALETTE) SEP FUNC(wd_core_slice_state, WEIGHTS)
26051
26052#define EXPAND_WD_CTRL_STATE(FUNC, SEP) \
26053 FUNC(wd_ctrl_state, IDLE) \
26054 SEP FUNC(wd_ctrl_state, DRAIN) SEP FUNC(wd_ctrl_state, OFD_INIT) SEP FUNC(wd_ctrl_state, OFD_RUN)
26055
26056#define EXPAND_WEIGHT_ORDER(FUNC, SEP) FUNC(weight_order, DEPTH_FIRST) SEP FUNC(weight_order, PART_KERNEL_FIRST)
26057
26058#ifdef __cplusplus
26059}
26060#endif
26061#endif
#define MAX(A, B)
Definition arm_nnsupportfunctions.h:48
#define MIN(A, B)
Definition arm_nnsupportfunctions.h:49
int offset
Definition mirror_pad.cpp:27
int zero_point
Definition batch_matmul_test.cc:45
float scale
Definition batch_matmul_test.cc:44
#define max(a, b)
Definition common_functions.h:29
kernel_dilation
Definition ethosu55_interface.h:1069
@ KERNEL_DILATION_NONE
Definition ethosu55_interface.h:1070
@ KERNEL_DILATION_X2
Definition ethosu55_interface.h:1071
privilege_level
Definition ethosu55_interface.h:1192
@ PRIVILEGE_LEVEL_USER
Definition ethosu55_interface.h:1193
@ PRIVILEGE_LEVEL_PRIVILEGED
Definition ethosu55_interface.h:1194
ifm2_operand_order
Definition ethosu55_interface.h:1043
@ IFM2_OPERAND_ORDER_ORDER_A
Definition ethosu55_interface.h:1045
@ IFM2_OPERAND_ORDER_ORDER_B
Definition ethosu55_interface.h:1044
wd_ctrl_state
Definition ethosu55_interface.h:1224
@ WD_CTRL_STATE_IDLE
Definition ethosu55_interface.h:1225
@ WD_CTRL_STATE_DRAIN
Definition ethosu55_interface.h:1226
@ WD_CTRL_STATE_OFD_RUN
Definition ethosu55_interface.h:1228
@ WD_CTRL_STATE_OFD_INIT
Definition ethosu55_interface.h:1227
weight_order
Definition ethosu55_interface.h:1232
@ WEIGHT_ORDER_DEPTH_FIRST
Definition ethosu55_interface.h:1233
@ WEIGHT_ORDER_PART_KERNEL_FIRST
Definition ethosu55_interface.h:1234
dma_region_mode
Definition ethosu55_interface.h:1012
@ DMA_REGION_MODE_INTERNAL
Definition ethosu55_interface.h:1014
@ DMA_REGION_MODE_EXTERNAL
Definition ethosu55_interface.h:1013
round_mode
Definition ethosu55_interface.h:1198
@ ROUND_MODE_DBL
Definition ethosu55_interface.h:1199
@ ROUND_MODE_TRUNCATE
Definition ethosu55_interface.h:1200
@ ROUND_MODE_NATURAL
Definition ethosu55_interface.h:1201
security_level
Definition ethosu55_interface.h:1205
@ SECURITY_LEVEL_NON_SECURE
Definition ethosu55_interface.h:1207
@ SECURITY_LEVEL_SECURE
Definition ethosu55_interface.h:1206
activation_format
Definition ethosu55_interface.h:825
@ ACTIVATION_FORMAT_NHWC
Definition ethosu55_interface.h:826
@ ACTIVATION_FORMAT_NHCWB16
Definition ethosu55_interface.h:827
pooling_mode
Definition ethosu55_interface.h:1185
@ POOLING_MODE_AVERAGE
Definition ethosu55_interface.h:1187
@ POOLING_MODE_MAX
Definition ethosu55_interface.h:1186
@ POOLING_MODE_REDUCE_SUM
Definition ethosu55_interface.h:1188
cmd0_opcode
Definition ethosu55_interface.h:882
@ CMD0_OPCODE_NPU_SET_IFM_PRECISION
Definition ethosu55_interface.h:898
@ CMD0_OPCODE_NPU_SET_ACTIVATION_MIN
Definition ethosu55_interface.h:923
@ CMD0_OPCODE_NPU_OP_POOL
Definition ethosu55_interface.h:887
@ CMD0_OPCODE_NPU_SET_OFM_WIDTH_M1
Definition ethosu55_interface.h:906
@ CMD0_OPCODE_NPU_SET_KERNEL_WIDTH_M1
Definition ethosu55_interface.h:918
@ CMD0_OPCODE_NPU_SET_IFM2_SCALAR
Definition ethosu55_interface.h:934
@ CMD0_OPCODE_NPU_SET_IFM_DEPTH_M1
Definition ethosu55_interface.h:897
@ CMD0_OPCODE_NPU_OP_IRQ
Definition ethosu55_interface.h:884
@ CMD0_OPCODE_NPU_SET_DMA0_SRC_REGION
Definition ethosu55_interface.h:929
@ CMD0_OPCODE_NPU_SET_KERNEL_HEIGHT_M1
Definition ethosu55_interface.h:919
@ CMD0_OPCODE_NPU_SET_IFM2_ZERO_POINT
Definition ethosu55_interface.h:936
@ CMD0_OPCODE_NPU_SET_OFM_HEIGHT0_M1
Definition ethosu55_interface.h:915
@ CMD0_OPCODE_NPU_SET_IFM_PAD_BOTTOM
Definition ethosu55_interface.h:896
@ CMD0_OPCODE_NPU_SET_KERNEL_STRIDE
Definition ethosu55_interface.h:920
@ CMD0_OPCODE_NPU_SET_IFM_UPSCALE
Definition ethosu55_interface.h:899
@ CMD0_OPCODE_NPU_SET_OFM_BLK_WIDTH_M1
Definition ethosu55_interface.h:910
@ CMD0_OPCODE_NPU_OP_PMU_MASK
Definition ethosu55_interface.h:892
@ CMD0_OPCODE_NPU_SET_IFM2_PRECISION
Definition ethosu55_interface.h:935
@ CMD0_OPCODE_NPU_SET_OFM_HEIGHT1_M1
Definition ethosu55_interface.h:916
@ CMD0_OPCODE_NPU_OP_ELEMENTWISE
Definition ethosu55_interface.h:888
@ CMD0_OPCODE_NPU_SET_ACTIVATION
Definition ethosu55_interface.h:922
@ CMD0_OPCODE_NPU_SET_OFM_DEPTH_M1
Definition ethosu55_interface.h:908
@ CMD0_OPCODE_NPU_SET_OFM_WIDTH0_M1
Definition ethosu55_interface.h:914
@ CMD0_OPCODE_NPU_SET_IFM2_BROADCAST
Definition ethosu55_interface.h:933
@ CMD0_OPCODE_NPU_SET_IFM_PAD_TOP
Definition ethosu55_interface.h:893
@ CMD0_OPCODE_NPU_SET_IFM2_REGION
Definition ethosu55_interface.h:941
@ CMD0_OPCODE_NPU_OP_STOP
Definition ethosu55_interface.h:883
@ CMD0_OPCODE_NPU_SET_IFM_HEIGHT1_M1
Definition ethosu55_interface.h:903
@ CMD0_OPCODE_NPU_SET_IFM_HEIGHT0_M1
Definition ethosu55_interface.h:902
@ CMD0_OPCODE_NPU_SET_BLOCKDEP
Definition ethosu55_interface.h:928
@ CMD0_OPCODE_NPU_SET_OFM_BLK_DEPTH_M1
Definition ethosu55_interface.h:912
@ CMD0_OPCODE_NPU_SET_IFM_WIDTH0_M1
Definition ethosu55_interface.h:901
@ CMD0_OPCODE_NPU_SET_AB_START
Definition ethosu55_interface.h:927
@ CMD0_OPCODE_NPU_SET_ACTIVATION_MAX
Definition ethosu55_interface.h:924
@ CMD0_OPCODE_NPU_SET_DMA0_SIZE1
Definition ethosu55_interface.h:932
@ CMD0_OPCODE_NPU_SET_DMA0_DST_REGION
Definition ethosu55_interface.h:930
@ CMD0_OPCODE_NPU_SET_IFM2_HEIGHT1_M1
Definition ethosu55_interface.h:939
@ CMD0_OPCODE_NPU_SET_SCALE_REGION
Definition ethosu55_interface.h:926
@ CMD0_OPCODE_NPU_SET_IFM2_WIDTH0_M1
Definition ethosu55_interface.h:937
@ CMD0_OPCODE_NPU_SET_DMA0_SIZE0
Definition ethosu55_interface.h:931
@ CMD0_OPCODE_NPU_SET_WEIGHT_REGION
Definition ethosu55_interface.h:925
@ CMD0_OPCODE_NPU_SET_OFM_PRECISION
Definition ethosu55_interface.h:909
@ CMD0_OPCODE_NPU_SET_IFM_ZERO_POINT
Definition ethosu55_interface.h:900
@ CMD0_OPCODE_NPU_SET_IFM_PAD_RIGHT
Definition ethosu55_interface.h:895
@ CMD0_OPCODE_NPU_SET_OFM_HEIGHT_M1
Definition ethosu55_interface.h:907
@ CMD0_OPCODE_NPU_SET_IFM_PAD_LEFT
Definition ethosu55_interface.h:894
@ CMD0_OPCODE_NPU_SET_ACC_FORMAT
Definition ethosu55_interface.h:921
@ CMD0_OPCODE_NPU_OP_DEPTHWISE
Definition ethosu55_interface.h:886
@ CMD0_OPCODE_NPU_SET_IFM_IB_END
Definition ethosu55_interface.h:904
@ CMD0_OPCODE_NPU_SET_OFM_REGION
Definition ethosu55_interface.h:917
@ CMD0_OPCODE_NPU_OP_DMA_START
Definition ethosu55_interface.h:889
@ CMD0_OPCODE_NPU_OP_CONV
Definition ethosu55_interface.h:885
@ CMD0_OPCODE_NPU_SET_IFM2_HEIGHT0_M1
Definition ethosu55_interface.h:938
@ CMD0_OPCODE_NPU_SET_OFM_BLK_HEIGHT_M1
Definition ethosu55_interface.h:911
@ CMD0_OPCODE_NPU_SET_IFM2_IB_START
Definition ethosu55_interface.h:940
@ CMD0_OPCODE_NPU_SET_OFM_ZERO_POINT
Definition ethosu55_interface.h:913
@ CMD0_OPCODE_NPU_SET_IFM_REGION
Definition ethosu55_interface.h:905
@ CMD0_OPCODE_NPU_OP_DMA_WAIT
Definition ethosu55_interface.h:890
@ CMD0_OPCODE_NPU_OP_KERNEL_WAIT
Definition ethosu55_interface.h:891
custom_dma
Definition ethosu55_interface.h:1000
@ CUSTOM_DMA_NOT_IMPLEMENTED
Definition ethosu55_interface.h:1001
@ CUSTOM_DMA_IMPLEMENTED
Definition ethosu55_interface.h:1002
pmu_axi_channel
Definition ethosu55_interface.h:1096
@ PMU_AXI_CHANNEL_RD_MEM2MEM
Definition ethosu55_interface.h:1101
@ PMU_AXI_CHANNEL_RD_WEIGHTS
Definition ethosu55_interface.h:1099
@ PMU_AXI_CHANNEL_RD_CMD
Definition ethosu55_interface.h:1097
@ PMU_AXI_CHANNEL_WR_MEM2MEM
Definition ethosu55_interface.h:1103
@ PMU_AXI_CHANNEL_RD_SCALE_BIAS
Definition ethosu55_interface.h:1100
@ PMU_AXI_CHANNEL_RD_IFM
Definition ethosu55_interface.h:1098
@ PMU_AXI_CHANNEL_WR_OFM
Definition ethosu55_interface.h:1102
dma_stride_mode
Definition ethosu55_interface.h:1018
@ DMA_STRIDE_MODE_D1
Definition ethosu55_interface.h:1019
#define STRUCT
Definition ethosu55_interface.h:36
activation_type
Definition ethosu55_interface.h:854
@ ACTIVATION_TYPE_SIGNED
Definition ethosu55_interface.h:856
@ ACTIVATION_TYPE_UNSIGNED
Definition ethosu55_interface.h:855
activation_clip_range
Definition ethosu55_interface.h:817
@ ACTIVATION_CLIP_RANGE_FORCE_INT16
Definition ethosu55_interface.h:821
@ ACTIVATION_CLIP_RANGE_FORCE_UINT8
Definition ethosu55_interface.h:819
@ ACTIVATION_CLIP_RANGE_OFM_PRECISION
Definition ethosu55_interface.h:818
@ ACTIVATION_CLIP_RANGE_FORCE_INT8
Definition ethosu55_interface.h:820
cmd_ctrl
Definition ethosu55_interface.h:988
@ CMD_CTRL_CMD1_CTRL
Definition ethosu55_interface.h:990
@ CMD_CTRL_CMD0_CTRL
Definition ethosu55_interface.h:989
activation_function
Definition ethosu55_interface.h:831
@ ACTIVATION_FUNCTION_TABLE_7
Definition ethosu55_interface.h:842
@ ACTIVATION_FUNCTION_TABLE_4
Definition ethosu55_interface.h:839
@ ACTIVATION_FUNCTION_RELU
Definition ethosu55_interface.h:832
@ ACTIVATION_FUNCTION_TABLE_2
Definition ethosu55_interface.h:837
@ ACTIVATION_FUNCTION_TABLE_1
Definition ethosu55_interface.h:836
@ ACTIVATION_FUNCTION_TANH
Definition ethosu55_interface.h:833
@ ACTIVATION_FUNCTION_TABLE_6
Definition ethosu55_interface.h:841
@ ACTIVATION_FUNCTION_SIGMOID
Definition ethosu55_interface.h:834
@ ACTIVATION_FUNCTION_TABLE_0
Definition ethosu55_interface.h:835
@ ACTIVATION_FUNCTION_TABLE_3
Definition ethosu55_interface.h:838
@ ACTIVATION_FUNCTION_TABLE_5
Definition ethosu55_interface.h:840
mem_attr
Definition ethosu55_interface.h:1082
@ MEM_ATTR_AXI1_OUTSTANDING_COUNTER3
Definition ethosu55_interface.h:1086
@ MEM_ATTR_AXI0_OUTSTANDING_COUNTER1
Definition ethosu55_interface.h:1084
@ MEM_ATTR_AXI0_OUTSTANDING_COUNTER0
Definition ethosu55_interface.h:1083
@ MEM_ATTR_AXI1_OUTSTANDING_COUNTER2
Definition ethosu55_interface.h:1085
activation_precision
Definition ethosu55_interface.h:846
@ ACTIVATION_PRECISION_B64
Definition ethosu55_interface.h:850
@ ACTIVATION_PRECISION_B32
Definition ethosu55_interface.h:849
@ ACTIVATION_PRECISION_B16
Definition ethosu55_interface.h:848
@ ACTIVATION_PRECISION_B8
Definition ethosu55_interface.h:847
broadcast_mode
Definition ethosu55_interface.h:876
@ BROADCAST_MODE_DISABLE
Definition ethosu55_interface.h:877
@ BROADCAST_MODE_ENABLE
Definition ethosu55_interface.h:878
pmu_event
Definition ethosu55_interface.h:1107
@ PMU_EVENT_AXI0_WR_TRANS_ACCEPTED
Definition ethosu55_interface.h:1150
@ PMU_EVENT_MAC_STALLED_BY_ACC
Definition ethosu55_interface.h:1120
@ PMU_EVENT_MAC_ACTIVE_32BIT
Definition ethosu55_interface.h:1122
@ PMU_EVENT_AXI_LATENCY_ANY
Definition ethosu55_interface.h:1159
@ PMU_EVENT_AXI0_WR_DATA_BEAT_WRITTEN
Definition ethosu55_interface.h:1153
@ PMU_EVENT_MAC_ACTIVE
Definition ethosu55_interface.h:1114
@ PMU_EVENT_AXI1_RD_TRAN_REQ_STALLED
Definition ethosu55_interface.h:1171
@ PMU_EVENT_AXI0_RD_STALL_LIMIT
Definition ethosu55_interface.h:1157
@ PMU_EVENT_AXI1_WR_DATA_BEAT_WRITTEN
Definition ethosu55_interface.h:1175
@ PMU_EVENT_AXI0_RD_TRANS_COMPLETED
Definition ethosu55_interface.h:1147
@ PMU_EVENT_ECC_DMA
Definition ethosu55_interface.h:1166
@ PMU_EVENT_WD_TRANS_WS
Definition ethosu55_interface.h:1142
@ PMU_EVENT_WD_PARSE_STALLED_OUT
Definition ethosu55_interface.h:1141
@ PMU_EVENT_MAC_STALLED_BY_WD
Definition ethosu55_interface.h:1119
@ PMU_EVENT_WD_STALLED
Definition ethosu55_interface.h:1135
@ PMU_EVENT_AXI1_RD_STALL_LIMIT
Definition ethosu55_interface.h:1179
@ PMU_EVENT_MAC_ACTIVE_8BIT
Definition ethosu55_interface.h:1115
@ PMU_EVENT_MAC_ACTIVE_16BIT
Definition ethosu55_interface.h:1116
@ PMU_EVENT_NO_EVENT
Definition ethosu55_interface.h:1108
@ PMU_EVENT_AXI1_WR_TRANS_COMPLETED_S
Definition ethosu55_interface.h:1174
@ PMU_EVENT_WD_PARSE_STALLED_IN
Definition ethosu55_interface.h:1140
@ PMU_EVENT_AO_STALLED_BY_ACC_IB
Definition ethosu55_interface.h:1131
@ PMU_EVENT_MAC_STALLED_BY_IB
Definition ethosu55_interface.h:1121
@ PMU_EVENT_CYCLE
Definition ethosu55_interface.h:1109
@ PMU_EVENT_WD_TRANS_WB
Definition ethosu55_interface.h:1143
@ PMU_EVENT_WD_PARSE_ACTIVE
Definition ethosu55_interface.h:1138
@ PMU_EVENT_AXI1_WR_TRANS_COMPLETED_M
Definition ethosu55_interface.h:1173
@ PMU_EVENT_WD_STALLED_BY_WD_BUF
Definition ethosu55_interface.h:1137
@ PMU_EVENT_WD_STALLED_BY_WS
Definition ethosu55_interface.h:1136
@ PMU_EVENT_AXI_LATENCY_64
Definition ethosu55_interface.h:1161
@ PMU_EVENT_AXI_LATENCY_512
Definition ethosu55_interface.h:1164
@ PMU_EVENT_AO_STALLED_BY_OFMP
Definition ethosu55_interface.h:1129
@ PMU_EVENT_NPU_ACTIVE
Definition ethosu55_interface.h:1113
@ PMU_EVENT_AXI1_RD_TRANS_COMPLETED
Definition ethosu55_interface.h:1169
@ PMU_EVENT_AXI1_ENABLED_CYCLES
Definition ethosu55_interface.h:1178
@ PMU_EVENT_AXI1_WR_TRAN_REQ_STALLED
Definition ethosu55_interface.h:1176
@ PMU_EVENT_AO_STALLED_BY_IB
Definition ethosu55_interface.h:1133
@ PMU_EVENT_AXI0_WR_TRAN_REQ_STALLED
Definition ethosu55_interface.h:1154
@ PMU_EVENT_AXI0_WR_TRANS_COMPLETED_S
Definition ethosu55_interface.h:1152
@ PMU_EVENT_NPU_IDLE
Definition ethosu55_interface.h:1110
@ PMU_EVENT_AXI_LATENCY_1024
Definition ethosu55_interface.h:1165
@ PMU_EVENT_AXI0_RD_TRAN_REQ_STALLED
Definition ethosu55_interface.h:1149
@ PMU_EVENT_AXI1_RD_TRANS_ACCEPTED
Definition ethosu55_interface.h:1168
@ PMU_EVENT_AXI0_WR_TRANS_COMPLETED_M
Definition ethosu55_interface.h:1151
@ PMU_EVENT_AXI0_RD_TRANS_ACCEPTED
Definition ethosu55_interface.h:1146
@ PMU_EVENT_ECC_SB0
Definition ethosu55_interface.h:1167
@ PMU_EVENT_CC_STALLED_ON_BLOCKDEP
Definition ethosu55_interface.h:1111
@ PMU_EVENT_AO_ACTIVE_8BIT
Definition ethosu55_interface.h:1126
@ PMU_EVENT_CC_STALLED_ON_SHRAM_RECONFIG
Definition ethosu55_interface.h:1112
@ PMU_EVENT_AO_ACTIVE_16BIT
Definition ethosu55_interface.h:1127
@ PMU_EVENT_AXI0_WR_DATA_BEAT_STALLED
Definition ethosu55_interface.h:1155
@ PMU_EVENT_AXI1_WR_STALL_LIMIT
Definition ethosu55_interface.h:1180
@ PMU_EVENT_AXI1_WR_DATA_BEAT_STALLED
Definition ethosu55_interface.h:1177
@ PMU_EVENT_AXI0_WR_STALL_LIMIT
Definition ethosu55_interface.h:1158
@ PMU_EVENT_AXI0_ENABLED_CYCLES
Definition ethosu55_interface.h:1156
@ PMU_EVENT_AO_STALLED_BY_OB
Definition ethosu55_interface.h:1130
@ PMU_EVENT_MAC_STALLED_BY_INT_ACC
Definition ethosu55_interface.h:1124
@ PMU_EVENT_AO_STALLED_BY_OFMP_OB
Definition ethosu55_interface.h:1128
@ PMU_EVENT_AXI_LATENCY_256
Definition ethosu55_interface.h:1163
@ PMU_EVENT_ECC_SB1
Definition ethosu55_interface.h:1181
@ PMU_EVENT_MAC_DPU_ACTIVE
Definition ethosu55_interface.h:1117
@ PMU_EVENT_AXI_LATENCY_128
Definition ethosu55_interface.h:1162
@ PMU_EVENT_AXI1_RD_DATA_BEAT_RECEIVED
Definition ethosu55_interface.h:1170
@ PMU_EVENT_WD_ACTIVE
Definition ethosu55_interface.h:1134
@ PMU_EVENT_WD_PARSE_STALLED
Definition ethosu55_interface.h:1139
@ PMU_EVENT_MAC_STALLED_BY_INT_W
Definition ethosu55_interface.h:1123
@ PMU_EVENT_WD_TRANS_DW0
Definition ethosu55_interface.h:1144
@ PMU_EVENT_AXI1_WR_TRANS_ACCEPTED
Definition ethosu55_interface.h:1172
@ PMU_EVENT_WD_TRANS_DW1
Definition ethosu55_interface.h:1145
@ PMU_EVENT_MAC_STALLED_BY_WD_ACC
Definition ethosu55_interface.h:1118
@ PMU_EVENT_AO_STALLED_BY_ACC
Definition ethosu55_interface.h:1132
@ PMU_EVENT_AO_ACTIVE
Definition ethosu55_interface.h:1125
@ PMU_EVENT_AXI0_RD_DATA_BEAT_RECEIVED
Definition ethosu55_interface.h:1148
@ PMU_EVENT_AXI_LATENCY_32
Definition ethosu55_interface.h:1160
wd_core_slice_state
Definition ethosu55_interface.h:1217
@ WD_CORE_SLICE_STATE_PALETTE
Definition ethosu55_interface.h:1219
@ WD_CORE_SLICE_STATE_WEIGHTS
Definition ethosu55_interface.h:1220
@ WD_CORE_SLICE_STATE_HEADER
Definition ethosu55_interface.h:1218
ofm_scale_mode
Definition ethosu55_interface.h:1090
@ OFM_SCALE_MODE_GLOBAL
Definition ethosu55_interface.h:1092
@ OFM_SCALE_MODE_PER_CHANNEL
Definition ethosu55_interface.h:1091
ifm_scale_mode
Definition ethosu55_interface.h:1049
@ IFM_SCALE_MODE_OPA_OPB_16
Definition ethosu55_interface.h:1050
@ IFM_SCALE_MODE_OPA_32
Definition ethosu55_interface.h:1051
@ IFM_SCALE_MODE_OPB_32
Definition ethosu55_interface.h:1052
acc_format
Definition ethosu55_interface.h:810
@ ACC_FORMAT_I40
Definition ethosu55_interface.h:812
@ ACC_FORMAT_I32
Definition ethosu55_interface.h:811
@ ACC_FORMAT_F16
Definition ethosu55_interface.h:813
#define CONSTEXPR
Definition ethosu55_interface.h:30
cmd1_opcode
Definition ethosu55_interface.h:945
@ CMD1_OPCODE_NPU_SET_OFM_STRIDE_X
Definition ethosu55_interface.h:957
@ CMD1_OPCODE_NPU_SET_DMA0_LEN
Definition ethosu55_interface.h:969
@ CMD1_OPCODE_NPU_SET_IFM2_BASE2
Definition ethosu55_interface.h:972
@ CMD1_OPCODE_NPU_SET_IFM_STRIDE_X
Definition ethosu55_interface.h:950
@ CMD1_OPCODE_NPU_SET_OFM_STRIDE_C
Definition ethosu55_interface.h:959
@ CMD1_OPCODE_NPU_SET_IFM_BASE1
Definition ethosu55_interface.h:947
@ CMD1_OPCODE_NPU_SET_SCALE_BASE
Definition ethosu55_interface.h:962
@ CMD1_OPCODE_NPU_SET_SCALE_LENGTH
Definition ethosu55_interface.h:963
@ CMD1_OPCODE_NPU_SET_OPB_SCALE
Definition ethosu55_interface.h:966
@ CMD1_OPCODE_NPU_SET_DMA0_SRC
Definition ethosu55_interface.h:967
@ CMD1_OPCODE_NPU_SET_OFM_BASE2
Definition ethosu55_interface.h:955
@ CMD1_OPCODE_NPU_SET_IFM2_STRIDE_X
Definition ethosu55_interface.h:974
@ CMD1_OPCODE_NPU_SET_IFM2_BASE1
Definition ethosu55_interface.h:971
@ CMD1_OPCODE_NPU_SET_IFM_BASE3
Definition ethosu55_interface.h:949
@ CMD1_OPCODE_NPU_SET_OFM_BASE0
Definition ethosu55_interface.h:953
@ CMD1_OPCODE_NPU_SET_IFM_BASE0
Definition ethosu55_interface.h:946
@ CMD1_OPCODE_NPU_SET_WEIGHT_LENGTH
Definition ethosu55_interface.h:961
@ CMD1_OPCODE_NPU_SET_IFM2_BASE0
Definition ethosu55_interface.h:970
@ CMD1_OPCODE_NPU_SET_OFM_SCALE
Definition ethosu55_interface.h:964
@ CMD1_OPCODE_NPU_SET_IFM2_BASE3
Definition ethosu55_interface.h:973
@ CMD1_OPCODE_NPU_SET_DMA0_DST
Definition ethosu55_interface.h:968
@ CMD1_OPCODE_NPU_SET_OFM_BASE3
Definition ethosu55_interface.h:956
@ CMD1_OPCODE_NPU_SET_IFM_STRIDE_C
Definition ethosu55_interface.h:952
@ CMD1_OPCODE_NPU_SET_IFM2_STRIDE_C
Definition ethosu55_interface.h:976
@ CMD1_OPCODE_NPU_SET_WEIGHT_BASE
Definition ethosu55_interface.h:960
@ CMD1_OPCODE_NPU_SET_OPA_SCALE
Definition ethosu55_interface.h:965
@ CMD1_OPCODE_NPU_SET_IFM_STRIDE_Y
Definition ethosu55_interface.h:951
@ CMD1_OPCODE_NPU_SET_IFM2_STRIDE_Y
Definition ethosu55_interface.h:975
@ CMD1_OPCODE_NPU_SET_IFM_BASE2
Definition ethosu55_interface.h:948
@ CMD1_OPCODE_NPU_SET_OFM_STRIDE_Y
Definition ethosu55_interface.h:958
@ CMD1_OPCODE_NPU_SET_OFM_BASE1
Definition ethosu55_interface.h:954
state
Definition ethosu55_interface.h:1211
@ STATE_STOPPED
Definition ethosu55_interface.h:1212
@ STATE_RUNNING
Definition ethosu55_interface.h:1213
ifm_upscale_mode
Definition ethosu55_interface.h:1056
@ IFM_UPSCALE_MODE_ZEROS
Definition ethosu55_interface.h:1059
@ IFM_UPSCALE_MODE_NONE
Definition ethosu55_interface.h:1057
@ IFM_UPSCALE_MODE_NEAREST
Definition ethosu55_interface.h:1058
max_beats
Definition ethosu55_interface.h:1075
@ MAX_BEATS_B64
Definition ethosu55_interface.h:1076
@ MAX_BEATS_B256
Definition ethosu55_interface.h:1078
@ MAX_BEATS_B128
Definition ethosu55_interface.h:1077
axi_mem_encoding
Definition ethosu55_interface.h:860
@ AXI_MEM_ENCODING_WRITE_BACK_READ_ALLOCATE
Definition ethosu55_interface.h:870
@ AXI_MEM_ENCODING_WRITE_BACK_READ_AND_WRITE_ALLOCATE
Definition ethosu55_interface.h:872
@ AXI_MEM_ENCODING_WRITE_THROUGH_WRITE_ALLOCATE
Definition ethosu55_interface.h:867
@ AXI_MEM_ENCODING_WRITE_BACK_WRITE_ALLOCATE
Definition ethosu55_interface.h:871
@ AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_NON_BUFFERABLE
Definition ethosu55_interface.h:863
@ AXI_MEM_ENCODING_WRITE_THROUGH_READ_ALLOCATE
Definition ethosu55_interface.h:866
@ AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_BUFFERABLE
Definition ethosu55_interface.h:864
@ AXI_MEM_ENCODING_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE
Definition ethosu55_interface.h:868
@ AXI_MEM_ENCODING_WRITE_BACK_NO_ALLOCATE
Definition ethosu55_interface.h:869
@ AXI_MEM_ENCODING_DEVICE_BUFFERABLE
Definition ethosu55_interface.h:862
@ AXI_MEM_ENCODING_DEVICE_NON_BUFFERABLE
Definition ethosu55_interface.h:861
@ AXI_MEM_ENCODING_WRITE_THROUGH_NO_ALLOCATE
Definition ethosu55_interface.h:865
kernel_decomposition
Definition ethosu55_interface.h:1063
@ KERNEL_DECOMPOSITION_D4X4
Definition ethosu55_interface.h:1065
@ KERNEL_DECOMPOSITION_D8X8
Definition ethosu55_interface.h:1064
functional_safety
Definition ethosu55_interface.h:1037
@ FUNCTIONAL_SAFETY_NOT_IMPLEMENTED
Definition ethosu55_interface.h:1038
@ FUNCTIONAL_SAFETY_IMPLEMENTED
Definition ethosu55_interface.h:1039
dma_fault_src
Definition ethosu55_interface.h:1006
@ DMA_FAULT_SRC_AXI_M0
Definition ethosu55_interface.h:1007
@ DMA_FAULT_SRC_AXI_M1
Definition ethosu55_interface.h:1008
elementwise_mode
Definition ethosu55_interface.h:1023
@ ELEMENTWISE_MODE_SHR
Definition ethosu55_interface.h:1032
@ ELEMENTWISE_MODE_SHL
Definition ethosu55_interface.h:1033
@ ELEMENTWISE_MODE_SUB
Definition ethosu55_interface.h:1026
@ ELEMENTWISE_MODE_MAX
Definition ethosu55_interface.h:1028
@ ELEMENTWISE_MODE_MUL
Definition ethosu55_interface.h:1024
@ ELEMENTWISE_MODE_CLZ
Definition ethosu55_interface.h:1031
@ ELEMENTWISE_MODE_ABS
Definition ethosu55_interface.h:1030
@ ELEMENTWISE_MODE_ADD
Definition ethosu55_interface.h:1025
@ ELEMENTWISE_MODE_MIN
Definition ethosu55_interface.h:1027
@ ELEMENTWISE_MODE_LRELU
Definition ethosu55_interface.h:1029
cmd0_opcode
Definition ethosu65_interface.h:895
@ CMD0_OPCODE_NPU_SET_PARALLEL_MODE
Definition ethosu65_interface.h:934
@ DMA_STRIDE_MODE_D2
Definition ethosu65_interface.h:1026
@ DMA_STRIDE_MODE_D3
Definition ethosu65_interface.h:1027
cmd_ctrl
Definition ethosu65_interface.h:1000
parallel_mode
Definition ethosu65_interface.h:1104
@ PARALLEL_MODE_SINGLE_CORE
Definition ethosu65_interface.h:1105
@ PARALLEL_MODE_DUAL_CORE_DEPTH
Definition ethosu65_interface.h:1106
cmd1_opcode
Definition ethosu65_interface.h:959
@ CMD1_OPCODE_NPU_SET_SCALE1_LENGTH
Definition ethosu65_interface.h:996
@ CMD1_OPCODE_NPU_SET_WEIGHT1_LENGTH
Definition ethosu65_interface.h:994
@ CMD1_OPCODE_NPU_SET_DMA0_SKIP1
Definition ethosu65_interface.h:985
@ CMD1_OPCODE_NPU_SET_WEIGHT1_BASE
Definition ethosu65_interface.h:993
@ CMD1_OPCODE_NPU_SET_SCALE1_BASE
Definition ethosu65_interface.h:995
@ CMD1_OPCODE_NPU_SET_DMA0_SKIP0
Definition ethosu65_interface.h:984
int size
Definition hello_world_model.cc:113
Definition ethosu55_interface.h:15885
STRUCT debugcore_r DEBUGCORE
Definition ethosu65_interface.h:16345
STRUCT scale1_base_r SCALE1_BASE
Definition ethosu65_interface.h:16502
STRUCT scale1_length_r SCALE1_LENGTH
Definition ethosu65_interface.h:16503
STRUCT parallel_mode_r PARALLEL_MODE
Definition ethosu65_interface.h:16431
STRUCT dma0_skip0_r DMA0_SKIP0
Definition ethosu65_interface.h:16489
STRUCT weight1_base_r WEIGHT1_BASE
Definition ethosu65_interface.h:16500
STRUCT weight1_length_r WEIGHT1_LENGTH
Definition ethosu65_interface.h:16501
STRUCT dma0_skip1_r DMA0_SKIP1
Definition ethosu65_interface.h:16490
Definition ethosu55_interface.h:12439
Definition ethosu55_interface.h:12067
Definition ethosu55_interface.h:12253
Definition ethosu55_interface.h:12191
Definition ethosu55_interface.h:12129
Definition ethosu55_interface.h:5243
Definition ethosu55_interface.h:4006
Definition ethosu55_interface.h:4139
Definition ethosu55_interface.h:4272
Definition ethosu55_interface.h:4405
Definition ethosu55_interface.h:4539
uint32_t offset_HI
Definition ethosu65_interface.h:4543
uint32_t offset_LO
Definition ethosu65_interface.h:4542
Definition ethosu55_interface.h:12501
Definition ethosu55_interface.h:15638
Definition ethosu55_interface.h:15700
Definition ethosu55_interface.h:15762
Definition ethosu55_interface.h:15824
Definition ethosu55_interface.h:6739
Definition ethosu55_interface.h:2980
Definition ethosu55_interface.h:3564
Definition ethosu55_interface.h:9958
Definition ethosu55_interface.h:10082
Definition ethosu55_interface.h:10020
Definition ethosu55_interface.h:9846
Definition ethosu55_interface.h:6907
Definition ethosu55_interface.h:7032
Definition ethosu55_interface.h:6969
Definition ethosu65_interface.h:7029
uint32_t word
Definition ethosu65_interface.h:7037
uint32_t core
Definition ethosu65_interface.h:7035
Definition ethosu55_interface.h:14629
Definition ethosu55_interface.h:12625
Definition ethosu55_interface.h:14679
Definition ethosu55_interface.h:12687
Definition ethosu55_interface.h:12749
Definition ethosu65_interface.h:14858
uint32_t value_LO
Definition ethosu65_interface.h:14864
uint32_t value_HI
Definition ethosu65_interface.h:14865
Definition ethosu65_interface.h:14908
uint32_t value_HI
Definition ethosu65_interface.h:14915
uint32_t value_LO
Definition ethosu65_interface.h:14914
Definition ethosu55_interface.h:14579
Definition ethosu55_interface.h:12563
Definition ethosu55_interface.h:9684
Definition ethosu55_interface.h:9634
uint32_t offset_HI
Definition ethosu65_interface.h:9704
uint32_t offset_LO
Definition ethosu65_interface.h:9703
Definition ethosu55_interface.h:9410
Definition ethosu55_interface.h:9360
uint32_t offset_LO
Definition ethosu65_interface.h:9426
uint32_t offset_HI
Definition ethosu65_interface.h:9427
Definition ethosu55_interface.h:9796
uint32_t offset_HI
Definition ethosu65_interface.h:9868
uint32_t offset_LO
Definition ethosu65_interface.h:9867
Definition ethosu55_interface.h:9746
uint32_t offset_HI
Definition ethosu65_interface.h:9817
uint32_t offset_LO
Definition ethosu65_interface.h:9816
Definition ethosu55_interface.h:9534
uint32_t offset_HI
Definition ethosu65_interface.h:9602
uint32_t offset_LO
Definition ethosu65_interface.h:9601
Definition ethosu55_interface.h:9472
Definition ethosu55_interface.h:9908
uint32_t offset_LO
Definition ethosu65_interface.h:9980
uint32_t offset_HI
Definition ethosu65_interface.h:9981
Definition ethosu55_interface.h:5475
Definition ethosu55_interface.h:6191
Definition ethosu55_interface.h:9584
uint32_t offset_HI
Definition ethosu65_interface.h:9653
uint32_t offset_LO
Definition ethosu65_interface.h:9652
Definition ethosu55_interface.h:2486
Definition ethosu55_interface.h:14729
Definition ethosu55_interface.h:14779
Definition ethosu55_interface.h:14829
Definition ethosu55_interface.h:14879
Definition ethosu55_interface.h:12811
Definition ethosu55_interface.h:13121
Definition ethosu55_interface.h:13183
Definition ethosu55_interface.h:13245
Definition ethosu55_interface.h:12935
Definition ethosu55_interface.h:13307
Definition ethosu55_interface.h:12873
Definition ethosu55_interface.h:15029
Definition ethosu55_interface.h:14929
Definition ethosu55_interface.h:14979
Definition ethosu55_interface.h:13059
Definition ethosu55_interface.h:12997
Definition ethosu55_interface.h:13369
Definition ethosu55_interface.h:13419
Definition ethosu55_interface.h:13469
Definition ethosu55_interface.h:13519
Definition ethosu55_interface.h:8802
Definition ethosu55_interface.h:9298
Definition ethosu55_interface.h:9236
Definition ethosu55_interface.h:10579
Definition ethosu55_interface.h:10889
Definition ethosu55_interface.h:10951
Definition ethosu55_interface.h:11013
Definition ethosu55_interface.h:10517
Definition ethosu55_interface.h:10393
Definition ethosu55_interface.h:10455
Definition ethosu55_interface.h:10331
Definition ethosu55_interface.h:10641
Definition ethosu55_interface.h:11075
Definition ethosu55_interface.h:13669
Definition ethosu55_interface.h:13569
Definition ethosu55_interface.h:13619
Definition ethosu55_interface.h:10703
Definition ethosu55_interface.h:10827
Definition ethosu55_interface.h:9050
Definition ethosu55_interface.h:10765
Definition ethosu55_interface.h:8554
Definition ethosu55_interface.h:11943
Definition ethosu55_interface.h:12005
Definition ethosu55_interface.h:8492
Definition ethosu55_interface.h:11881
Definition ethosu55_interface.h:8368
Definition ethosu55_interface.h:8430
Definition ethosu55_interface.h:3734
Definition ethosu55_interface.h:4864
Definition ethosu55_interface.h:18112
Definition ethosu55_interface.h:18168
Definition ethosu55_interface.h:18382
Definition ethosu55_interface.h:18438
Definition ethosu55_interface.h:18303
Definition ethosu55_interface.h:18039
Definition ethosu55_interface.h:18512
Definition ethosu55_interface.h:18586
Definition ethosu55_interface.h:18224
Definition ethosu55_interface.h:17966
Definition ethosu55_interface.h:21524
Definition ethosu55_interface.h:21020
Definition ethosu55_interface.h:21270
Definition ethosu55_interface.h:21196
Definition ethosu55_interface.h:21098
Definition ethosu55_interface.h:21599
Definition ethosu55_interface.h:21802
Definition ethosu55_interface.h:24549
uint32_t addr_lo
Definition ethosu65_interface.h:24737
uint32_t addr_hi
Definition ethosu65_interface.h:24735
Definition ethosu55_interface.h:24625
uint32_t addr_hi
Definition ethosu65_interface.h:24797
uint32_t addr_lo
Definition ethosu65_interface.h:24799
Definition ethosu55_interface.h:21931
Definition ethosu55_interface.h:22004
Definition ethosu65_interface.h:24852
uint32_t addr_lo
Definition ethosu65_interface.h:24861
uint32_t reserved0
Definition ethosu65_interface.h:24857
uint32_t addr_hi
Definition ethosu65_interface.h:24859
uint32_t control
Definition ethosu65_interface.h:24858
uint32_t reserved1
Definition ethosu65_interface.h:24860
uint32_t opcode
Definition ethosu65_interface.h:24856
Definition ethosu65_interface.h:24914
uint32_t control
Definition ethosu65_interface.h:24920
uint32_t opcode
Definition ethosu65_interface.h:24918
uint32_t reserved0
Definition ethosu65_interface.h:24919
uint32_t addr_lo
Definition ethosu65_interface.h:24923
uint32_t reserved1
Definition ethosu65_interface.h:24922
uint32_t addr_hi
Definition ethosu65_interface.h:24921
Definition ethosu55_interface.h:21674
Definition ethosu55_interface.h:24473
uint32_t addr_lo
Definition ethosu65_interface.h:24675
uint32_t addr_hi
Definition ethosu65_interface.h:24673
Definition ethosu55_interface.h:24701
uint32_t addr_hi
Definition ethosu65_interface.h:24983
uint32_t addr_lo
Definition ethosu65_interface.h:24985
Definition ethosu55_interface.h:24777
uint32_t addr_hi
Definition ethosu65_interface.h:25045
uint32_t addr_lo
Definition ethosu65_interface.h:25047
Definition ethosu55_interface.h:24853
uint32_t addr_lo
Definition ethosu65_interface.h:25109
uint32_t addr_hi
Definition ethosu65_interface.h:25107
Definition ethosu55_interface.h:24929
uint32_t addr_hi
Definition ethosu65_interface.h:25169
uint32_t addr_lo
Definition ethosu65_interface.h:25171
Definition ethosu55_interface.h:22077
Definition ethosu55_interface.h:22563
Definition ethosu55_interface.h:22636
Definition ethosu55_interface.h:22709
Definition ethosu55_interface.h:22300
Definition ethosu55_interface.h:22784
Definition ethosu55_interface.h:22227
Definition ethosu55_interface.h:25157
uint32_t addr_hi
Definition ethosu65_interface.h:25355
uint32_t addr_lo
Definition ethosu65_interface.h:25357
Definition ethosu55_interface.h:25005
uint32_t addr_lo
Definition ethosu65_interface.h:25233
uint32_t addr_hi
Definition ethosu65_interface.h:25231
Definition ethosu55_interface.h:25081
uint32_t addr_hi
Definition ethosu65_interface.h:25293
uint32_t addr_lo
Definition ethosu65_interface.h:25295
Definition ethosu55_interface.h:22490
Definition ethosu55_interface.h:22416
Definition ethosu55_interface.h:22859
uint32_t addr_hi
Definition ethosu65_interface.h:23283
uint32_t addr_lo
Definition ethosu65_interface.h:23285
Definition ethosu55_interface.h:22935
uint32_t addr_lo
Definition ethosu65_interface.h:23347
uint32_t addr_hi
Definition ethosu65_interface.h:23345
Definition ethosu55_interface.h:23011
uint32_t addr_lo
Definition ethosu65_interface.h:23409
uint32_t addr_hi
Definition ethosu65_interface.h:23407
Definition ethosu55_interface.h:23087
uint32_t addr_hi
Definition ethosu65_interface.h:23469
uint32_t addr_lo
Definition ethosu65_interface.h:23471
Definition ethosu55_interface.h:18957
Definition ethosu55_interface.h:19404
Definition ethosu55_interface.h:19477
Definition ethosu55_interface.h:19550
Definition ethosu55_interface.h:18883
Definition ethosu55_interface.h:18735
Definition ethosu55_interface.h:18809
Definition ethosu55_interface.h:18661
Definition ethosu55_interface.h:19030
Definition ethosu55_interface.h:19625
Definition ethosu55_interface.h:23315
uint32_t addr_lo
Definition ethosu65_interface.h:23657
uint32_t addr_hi
Definition ethosu65_interface.h:23655
Definition ethosu55_interface.h:23163
uint32_t addr_hi
Definition ethosu65_interface.h:23531
uint32_t addr_lo
Definition ethosu65_interface.h:23533
Definition ethosu55_interface.h:23239
uint32_t addr_hi
Definition ethosu65_interface.h:23593
uint32_t addr_lo
Definition ethosu65_interface.h:23595
Definition ethosu55_interface.h:19179
Definition ethosu55_interface.h:19331
Definition ethosu55_interface.h:19257
Definition ethosu55_interface.h:20763
Definition ethosu55_interface.h:20836
Definition ethosu55_interface.h:20690
Definition ethosu55_interface.h:23391
uint32_t addr_hi
Definition ethosu65_interface.h:23717
uint32_t addr_lo
Definition ethosu65_interface.h:23719
Definition ethosu55_interface.h:23467
uint32_t addr_hi
Definition ethosu65_interface.h:23779
uint32_t addr_lo
Definition ethosu65_interface.h:23781
Definition ethosu55_interface.h:23543
uint32_t addr_lo
Definition ethosu65_interface.h:23843
uint32_t addr_hi
Definition ethosu65_interface.h:23841
Definition ethosu55_interface.h:23619
uint32_t addr_hi
Definition ethosu65_interface.h:23903
uint32_t addr_lo
Definition ethosu65_interface.h:23905
Definition ethosu55_interface.h:20232
Definition ethosu55_interface.h:20157
Definition ethosu55_interface.h:20082
Definition ethosu55_interface.h:19861
Definition ethosu55_interface.h:20454
Definition ethosu55_interface.h:20527
Definition ethosu55_interface.h:19788
Definition ethosu55_interface.h:19934
Definition ethosu55_interface.h:20600
Definition ethosu55_interface.h:24225
Definition ethosu55_interface.h:23847
uint32_t addr_lo
Definition ethosu65_interface.h:24091
uint32_t addr_hi
Definition ethosu65_interface.h:24089
Definition ethosu55_interface.h:23695
uint32_t addr_lo
Definition ethosu65_interface.h:23967
uint32_t addr_hi
Definition ethosu65_interface.h:23965
Definition ethosu55_interface.h:23771
uint32_t addr_hi
Definition ethosu65_interface.h:24027
uint32_t addr_lo
Definition ethosu65_interface.h:24029
Definition ethosu55_interface.h:20381
Definition ethosu55_interface.h:19715
Definition ethosu55_interface.h:20307
Definition ethosu55_interface.h:24311
Definition ethosu55_interface.h:24397
Definition ethosu65_interface.h:21422
uint32_t parallel_mode
Definition ethosu65_interface.h:21429
uint32_t reserved1
Definition ethosu65_interface.h:21430
uint32_t opcode
Definition ethosu65_interface.h:21426
uint32_t control
Definition ethosu65_interface.h:21428
uint32_t reserved0
Definition ethosu65_interface.h:21427
Definition ethosu65_interface.h:25546
uint32_t addr_lo
Definition ethosu65_interface.h:25555
uint32_t control
Definition ethosu65_interface.h:25552
uint32_t reserved1
Definition ethosu65_interface.h:25554
uint32_t addr_hi
Definition ethosu65_interface.h:25553
uint32_t reserved0
Definition ethosu65_interface.h:25551
uint32_t opcode
Definition ethosu65_interface.h:25550
Definition ethosu65_interface.h:25608
uint32_t reserved0
Definition ethosu65_interface.h:25613
uint32_t length
Definition ethosu65_interface.h:25616
uint32_t control
Definition ethosu65_interface.h:25614
uint32_t reserved2
Definition ethosu65_interface.h:25617
uint32_t reserved1
Definition ethosu65_interface.h:25615
uint32_t opcode
Definition ethosu65_interface.h:25612
Definition ethosu55_interface.h:24073
uint32_t addr_lo
Definition ethosu65_interface.h:24289
uint32_t addr_hi
Definition ethosu65_interface.h:24287
Definition ethosu55_interface.h:24149
Definition ethosu55_interface.h:21434
Definition ethosu65_interface.h:25410
uint32_t control
Definition ethosu65_interface.h:25416
uint32_t addr_hi
Definition ethosu65_interface.h:25417
uint32_t reserved0
Definition ethosu65_interface.h:25415
uint32_t reserved1
Definition ethosu65_interface.h:25418
uint32_t addr_lo
Definition ethosu65_interface.h:25419
uint32_t opcode
Definition ethosu65_interface.h:25414
Definition ethosu65_interface.h:25472
uint32_t reserved0
Definition ethosu65_interface.h:25477
uint32_t reserved1
Definition ethosu65_interface.h:25479
uint32_t length
Definition ethosu65_interface.h:25480
uint32_t control
Definition ethosu65_interface.h:25478
uint32_t opcode
Definition ethosu65_interface.h:25476
Definition ethosu55_interface.h:23923
uint32_t addr_lo
Definition ethosu65_interface.h:24153
uint32_t addr_hi
Definition ethosu65_interface.h:24151
Definition ethosu55_interface.h:23999
Definition ethosu55_interface.h:21344
Definition ethosu55_interface.h:13719
Definition ethosu55_interface.h:13769
Definition ethosu55_interface.h:13819
Definition ethosu55_interface.h:13869
Definition ethosu55_interface.h:11509
Definition ethosu55_interface.h:11447
Definition ethosu55_interface.h:11385
Definition ethosu55_interface.h:8740
Definition ethosu55_interface.h:8678
Definition ethosu55_interface.h:8616
Definition ethosu55_interface.h:11261
Definition ethosu55_interface.h:11695
Definition ethosu55_interface.h:11757
Definition ethosu55_interface.h:11199
Definition ethosu55_interface.h:11323
Definition ethosu55_interface.h:11819
Definition ethosu55_interface.h:14269
Definition ethosu55_interface.h:14331
Definition ethosu55_interface.h:14019
Definition ethosu55_interface.h:13919
Definition ethosu55_interface.h:13969
Definition ethosu55_interface.h:11633
Definition ethosu55_interface.h:11137
Definition ethosu55_interface.h:8864
Definition ethosu55_interface.h:8926
Definition ethosu55_interface.h:8988
Definition ethosu55_interface.h:11571
Definition ethosu55_interface.h:14393
Definition ethosu55_interface.h:14455
Definition ethosu55_interface.h:14517
Definition ethosu55_interface.h:9174
Definition ethosu55_interface.h:9112
Definition ethosu65_interface.h:12134
uint32_t value
Definition ethosu65_interface.h:12140
uint32_t word
Definition ethosu65_interface.h:12142
Definition ethosu55_interface.h:15389
Definition ethosu55_interface.h:15452
Definition ethosu55_interface.h:15514
Definition ethosu55_interface.h:15576
Definition ethosu55_interface.h:15141
Definition ethosu55_interface.h:15203
Definition ethosu55_interface.h:15265
Definition ethosu55_interface.h:15327
Definition ethosu55_interface.h:8260
Definition ethosu55_interface.h:8175
Definition ethosu55_interface.h:8124
Definition ethosu55_interface.h:7389
Definition ethosu55_interface.h:7242
Definition ethosu55_interface.h:7094
Definition ethosu55_interface.h:10144
Definition ethosu55_interface.h:10206
Definition ethosu55_interface.h:7977
Definition ethosu55_interface.h:7830
Definition ethosu55_interface.h:7683
Definition ethosu55_interface.h:7536
Definition ethosu55_interface.h:3476
Definition ethosu55_interface.h:3239
uint32_t offset_LO
Definition ethosu65_interface.h:3241
uint32_t offset_HI
Definition ethosu65_interface.h:3242
Definition ethosu55_interface.h:3351
Definition ethosu55_interface.h:3289
Definition ethosu55_interface.h:3414
Definition ethosu55_interface.h:3796
Definition ethosu55_interface.h:3151
Definition ethosu55_interface.h:15079
Definition ethosu65_interface.h:15408
uint32_t value_LO
Definition ethosu65_interface.h:15414
uint32_t value_HI
Definition ethosu65_interface.h:15415
Definition ethosu65_interface.h:15458
uint32_t value_HI
Definition ethosu65_interface.h:15465
uint32_t value_LO
Definition ethosu65_interface.h:15464
Definition ethosu55_interface.h:14169
Definition ethosu55_interface.h:14219
Definition ethosu55_interface.h:12377
Definition ethosu55_interface.h:10269
Definition ethosu55_interface.h:2676
Definition ethosu55_interface.h:4589
Definition ethosu65_interface.h:15308
uint32_t value_LO
Definition ethosu65_interface.h:15314
uint32_t value_HI
Definition ethosu65_interface.h:15315
Definition ethosu65_interface.h:15358
uint32_t value_LO
Definition ethosu65_interface.h:15364
uint32_t value_HI
Definition ethosu65_interface.h:15365
Definition ethosu55_interface.h:14069
Definition ethosu55_interface.h:14119
Definition ethosu55_interface.h:12315
uint8_t value
Definition wm8960_regs.h:134
const uint16_t mask
Definition wm8960_regs.h:94
const uint8_t shift
Definition wm8960_regs.h:95