20#ifndef ETHOSU65_INTERFACE_H
21#define ETHOSU65_INTERFACE_H
24#include <linux/types.h>
29#if !defined(__cplusplus) || __cplusplus < 201402L
32#define CONSTEXPR constexpr
41#if defined(__cplusplus) && defined(NPU_DISASSEMBLE)
47#if defined(__cplusplus) && !defined(NPU_NAMESPACE)
48#define NPU_NAMESPACE npu
57namespace NPU_NAMESPACE
60#define NNX_ARCH_VERSION_MAJOR 1
61#define NNX_ARCH_VERSION_MINOR 0
62#define NNX_ARCH_VERSION_PATCH 6
68#define NPU_REG_ID 0x0000
69#define NPU_REG_STATUS 0x0004
70#define NPU_REG_CMD 0x0008
71#define NPU_REG_RESET 0x000C
72#define NPU_REG_QBASE 0x0010
73#define NPU_REG_QBASE_HI 0x0014
74#define NPU_REG_QREAD 0x0018
75#define NPU_REG_QCONFIG 0x001C
76#define NPU_REG_QSIZE 0x0020
77#define NPU_REG_PROT 0x0024
78#define NPU_REG_CONFIG 0x0028
79#define NPU_REG_LOCK 0x002C
80#define NPU_REG_REGIONCFG 0x003C
81#define NPU_REG_AXI_LIMIT0 0x0040
82#define NPU_REG_AXI_LIMIT1 0x0044
83#define NPU_REG_AXI_LIMIT2 0x0048
84#define NPU_REG_AXI_LIMIT3 0x004C
85#define BASE_REGISTERS_SIZE 0x0080
90#define NPU_REG_BASEP_BASE 0x0080
91#define NPU_REG_BASEP_ARRLEN 0x0008
92#define BASE_POINTERS_REGISTERS_SIZE 0x0100
97#define NPU_REG_WD_STATUS 0x0100
98#define NPU_REG_MAC_STATUS 0x0104
99#define NPU_REG_AO_STATUS 0x0108
100#define NPU_REG_DMA_STATUS0 0x0110
101#define NPU_REG_DMA_STATUS1 0x0114
102#define NPU_REG_CLKFORCE 0x0140
103#define NPU_REG_DEBUG_ADDRESS 0x0144
104#define NPU_REG_DEBUG_MISC 0x0148
105#define NPU_REG_DEBUGCORE 0x014C
106#define NPU_REG_DEBUG_BLOCK 0x0150
107#define DEBUG_REGISTERS_SIZE 0x0180
112#define NPU_REG_PMCR 0x0180
113#define NPU_REG_PMCNTENSET 0x0184
114#define NPU_REG_PMCNTENCLR 0x0188
115#define NPU_REG_PMOVSSET 0x018C
116#define NPU_REG_PMOVSCLR 0x0190
117#define NPU_REG_PMINTSET 0x0194
118#define NPU_REG_PMINTCLR 0x0198
119#define NPU_REG_PMCCNTR 0x01A0
120#define NPU_REG_PMCCNTR_HI 0x01A4
121#define NPU_REG_PMCCNTR_CFG 0x01A8
122#define NPU_REG_PMCAXI_CHAN 0x01AC
123#define PMU_REGISTERS_SIZE 0x0200
128#define NPU_REG_KERNEL_X 0x0200
129#define NPU_REG_KERNEL_Y 0x0204
130#define NPU_REG_KERNEL_W_M1 0x0208
131#define NPU_REG_KERNEL_H_M1 0x020C
132#define NPU_REG_OFM_CBLK_WIDTH_M1 0x0210
133#define NPU_REG_OFM_CBLK_HEIGHT_M1 0x0214
134#define NPU_REG_OFM_CBLK_DEPTH_M1 0x0218
135#define NPU_REG_IFM_CBLK_DEPTH_M1 0x021C
136#define NPU_REG_OFM_X 0x0220
137#define NPU_REG_OFM_Y 0x0224
138#define NPU_REG_OFM_Z 0x0228
139#define NPU_REG_IFM_Z 0x022C
140#define NPU_REG_PAD_TOP 0x0230
141#define NPU_REG_PAD_LEFT 0x0234
142#define NPU_REG_IFM_CBLK_WIDTH 0x0238
143#define NPU_REG_IFM_CBLK_HEIGHT 0x023C
144#define NPU_REG_DMA_IFM_SRC 0x0240
145#define NPU_REG_DMA_IFM_SRC_HI 0x0244
146#define NPU_REG_DMA_IFM_DST 0x0248
147#define NPU_REG_DMA_OFM_SRC 0x024C
148#define NPU_REG_DMA_OFM_DST 0x0250
149#define NPU_REG_DMA_OFM_DST_HI 0x0254
150#define NPU_REG_DMA_WEIGHT_SRC 0x0258
151#define NPU_REG_DMA_WEIGHT_SRC_HI 0x025C
152#define NPU_REG_DMA_CMD_SRC 0x0260
153#define NPU_REG_DMA_CMD_SRC_HI 0x0264
154#define NPU_REG_DMA_CMD_SIZE 0x0268
155#define NPU_REG_DMA_M2M_SRC 0x026C
156#define NPU_REG_DMA_M2M_SRC_HI 0x0270
157#define NPU_REG_DMA_M2M_DST 0x0274
158#define NPU_REG_DMA_M2M_DST_HI 0x0278
159#define NPU_REG_CURRENT_QREAD 0x027C
160#define NPU_REG_DMA_SCALE_SRC 0x0280
161#define NPU_REG_DMA_SCALE_SRC_HI 0x0284
162#define NPU_REG_CURRENT_BLOCK 0x02B4
163#define NPU_REG_CURRENT_OP 0x02B8
164#define NPU_REG_CURRENT_CMD 0x02BC
165#define TSU_DEBUG_REGISTERS_SIZE 0x02C0
170#define NPU_REG_PMEVCNTR_BASE 0x0300
171#define NPU_REG_PMEVCNTR_ARRLEN 0x0004
172#define NPU_REG_PMEVTYPER_BASE 0x0380
173#define NPU_REG_PMEVTYPER_ARRLEN 0x0004
174#define PMU_COUNTERS_REGISTERS_SIZE 0x0400
179#define NPU_REG_SHARED_BUFFER_BASE 0x0400
180#define NPU_REG_SHARED_BUFFER_ARRLEN 0x0100
181#define SHARED_BUFFER_REGISTERS_SIZE 0x0800
186#define NPU_REG_IFM_PAD_TOP 0x0800
187#define NPU_REG_IFM_PAD_LEFT 0x0804
188#define NPU_REG_IFM_PAD_RIGHT 0x0808
189#define NPU_REG_IFM_PAD_BOTTOM 0x080C
190#define NPU_REG_IFM_DEPTH_M1 0x0810
191#define NPU_REG_IFM_PRECISION 0x0814
192#define NPU_REG_IFM_UPSCALE 0x081C
193#define NPU_REG_IFM_ZERO_POINT 0x0824
194#define NPU_REG_IFM_WIDTH0_M1 0x0828
195#define NPU_REG_IFM_HEIGHT0_M1 0x082C
196#define NPU_REG_IFM_HEIGHT1_M1 0x0830
197#define NPU_REG_IFM_IB_END 0x0834
198#define NPU_REG_IFM_REGION 0x083C
199#define TSU_IFM_REGISTERS_SIZE 0x0840
204#define NPU_REG_OFM_WIDTH_M1 0x0844
205#define NPU_REG_OFM_HEIGHT_M1 0x0848
206#define NPU_REG_OFM_DEPTH_M1 0x084C
207#define NPU_REG_OFM_PRECISION 0x0850
208#define NPU_REG_OFM_BLK_WIDTH_M1 0x0854
209#define NPU_REG_OFM_BLK_HEIGHT_M1 0x0858
210#define NPU_REG_OFM_BLK_DEPTH_M1 0x085C
211#define NPU_REG_OFM_ZERO_POINT 0x0860
212#define NPU_REG_OFM_WIDTH0_M1 0x0868
213#define NPU_REG_OFM_HEIGHT0_M1 0x086C
214#define NPU_REG_OFM_HEIGHT1_M1 0x0870
215#define NPU_REG_OFM_REGION 0x087C
216#define TSU_OFM_REGISTERS_SIZE 0x0880
221#define NPU_REG_KERNEL_WIDTH_M1 0x0880
222#define NPU_REG_KERNEL_HEIGHT_M1 0x0884
223#define NPU_REG_KERNEL_STRIDE 0x0888
224#define NPU_REG_PARALLEL_MODE 0x088C
225#define NPU_REG_ACC_FORMAT 0x0890
226#define NPU_REG_ACTIVATION 0x0894
227#define NPU_REG_ACTIVATION_MIN 0x0898
228#define NPU_REG_ACTIVATION_MAX 0x089C
229#define NPU_REG_WEIGHT_REGION 0x08A0
230#define NPU_REG_SCALE_REGION 0x08A4
231#define NPU_REG_AB_START 0x08B4
232#define NPU_REG_BLOCKDEP 0x08BC
233#define TSU_KERNEL_REGISTERS_SIZE 0x08C0
238#define NPU_REG_DMA0_SRC_REGION 0x08C0
239#define NPU_REG_DMA0_DST_REGION 0x08C4
240#define NPU_REG_DMA0_SIZE0 0x08C8
241#define NPU_REG_DMA0_SIZE1 0x08CC
242#define TSU_DMA_REGISTERS_SIZE 0x0900
247#define NPU_REG_IFM2_BROADCAST 0x0900
248#define NPU_REG_IFM2_SCALAR 0x0904
249#define NPU_REG_IFM2_PRECISION 0x0914
250#define NPU_REG_IFM2_ZERO_POINT 0x0924
251#define NPU_REG_IFM2_WIDTH0_M1 0x0928
252#define NPU_REG_IFM2_HEIGHT0_M1 0x092C
253#define NPU_REG_IFM2_HEIGHT1_M1 0x0930
254#define NPU_REG_IFM2_IB_START 0x0934
255#define NPU_REG_IFM2_REGION 0x093C
256#define TSU_IFM2_REGISTERS_SIZE 0x0940
261#define NPU_REG_IFM_BASE0 0x0A00
262#define NPU_REG_IFM_BASE0_HI 0x0A04
263#define NPU_REG_IFM_BASE1 0x0A08
264#define NPU_REG_IFM_BASE1_HI 0x0A0C
265#define NPU_REG_IFM_BASE2 0x0A10
266#define NPU_REG_IFM_BASE2_HI 0x0A14
267#define NPU_REG_IFM_BASE3 0x0A18
268#define NPU_REG_IFM_BASE3_HI 0x0A1C
269#define NPU_REG_IFM_STRIDE_X 0x0A20
270#define NPU_REG_IFM_STRIDE_X_HI 0x0A24
271#define NPU_REG_IFM_STRIDE_Y 0x0A28
272#define NPU_REG_IFM_STRIDE_Y_HI 0x0A2C
273#define NPU_REG_IFM_STRIDE_C 0x0A30
274#define NPU_REG_IFM_STRIDE_C_HI 0x0A34
275#define TSU_IFM_BASE_REGISTERS_SIZE 0x0A40
280#define NPU_REG_OFM_BASE0 0x0A40
281#define NPU_REG_OFM_BASE0_HI 0x0A44
282#define NPU_REG_OFM_BASE1 0x0A48
283#define NPU_REG_OFM_BASE1_HI 0x0A4C
284#define NPU_REG_OFM_BASE2 0x0A50
285#define NPU_REG_OFM_BASE2_HI 0x0A54
286#define NPU_REG_OFM_BASE3 0x0A58
287#define NPU_REG_OFM_BASE3_HI 0x0A5C
288#define NPU_REG_OFM_STRIDE_X 0x0A60
289#define NPU_REG_OFM_STRIDE_X_HI 0x0A64
290#define NPU_REG_OFM_STRIDE_Y 0x0A68
291#define NPU_REG_OFM_STRIDE_Y_HI 0x0A6C
292#define NPU_REG_OFM_STRIDE_C 0x0A70
293#define NPU_REG_OFM_STRIDE_C_HI 0x0A74
294#define TSU_OFM_BASE_REGISTERS_SIZE 0x0A80
299#define NPU_REG_WEIGHT_BASE 0x0A80
300#define NPU_REG_WEIGHT_BASE_HI 0x0A84
301#define NPU_REG_WEIGHT_LENGTH 0x0A88
302#define NPU_REG_WEIGHT_LENGTH_HI 0x0A8C
303#define NPU_REG_SCALE_BASE 0x0A90
304#define NPU_REG_SCALE_BASE_HI 0x0A94
305#define NPU_REG_SCALE_LENGTH 0x0A98
306#define NPU_REG_SCALE_LENGTH_HI 0x0A9C
307#define NPU_REG_OFM_SCALE 0x0AA0
308#define NPU_REG_OFM_SCALE_SHIFT 0x0AA4
309#define NPU_REG_OPA_SCALE 0x0AA8
310#define NPU_REG_OPA_SCALE_SHIFT 0x0AAC
311#define NPU_REG_OPB_SCALE 0x0AB0
312#define TSU_WS_BASE_REGISTERS_SIZE 0x0AC0
317#define NPU_REG_DMA0_SRC 0x0AC0
318#define NPU_REG_DMA0_SRC_HI 0x0AC4
319#define NPU_REG_DMA0_DST 0x0AC8
320#define NPU_REG_DMA0_DST_HI 0x0ACC
321#define NPU_REG_DMA0_LEN 0x0AD0
322#define NPU_REG_DMA0_LEN_HI 0x0AD4
323#define NPU_REG_DMA0_SKIP0 0x0AD8
324#define NPU_REG_DMA0_SKIP0_HI 0x0ADC
325#define NPU_REG_DMA0_SKIP1 0x0AE0
326#define NPU_REG_DMA0_SKIP1_HI 0x0AE4
327#define TSU_DMA_BASE_REGISTERS_SIZE 0x0B00
332#define NPU_REG_IFM2_BASE0 0x0B00
333#define NPU_REG_IFM2_BASE0_HI 0x0B04
334#define NPU_REG_IFM2_BASE1 0x0B08
335#define NPU_REG_IFM2_BASE1_HI 0x0B0C
336#define NPU_REG_IFM2_BASE2 0x0B10
337#define NPU_REG_IFM2_BASE2_HI 0x0B14
338#define NPU_REG_IFM2_BASE3 0x0B18
339#define NPU_REG_IFM2_BASE3_HI 0x0B1C
340#define NPU_REG_IFM2_STRIDE_X 0x0B20
341#define NPU_REG_IFM2_STRIDE_X_HI 0x0B24
342#define NPU_REG_IFM2_STRIDE_Y 0x0B28
343#define NPU_REG_IFM2_STRIDE_Y_HI 0x0B2C
344#define NPU_REG_IFM2_STRIDE_C 0x0B30
345#define NPU_REG_IFM2_STRIDE_C_HI 0x0B34
346#define TSU_IFM2_BASE_REGISTERS_SIZE 0x0B40
351#define NPU_REG_WEIGHT1_BASE 0x0B40
352#define NPU_REG_WEIGHT1_BASE_HI 0x0B44
353#define NPU_REG_WEIGHT1_LENGTH 0x0B48
354#define NPU_REG_WEIGHT1_LENGTH_HI 0x0B4C
355#define NPU_REG_SCALE1_BASE 0x0B50
356#define NPU_REG_SCALE1_BASE_HI 0x0B54
357#define NPU_REG_SCALE1_LENGTH 0x0B58
358#define NPU_REG_SCALE1_LENGTH_HI 0x0B5C
359#define TSU_WS1_BASE_REGISTERS_SIZE 0x0B80
364#define TSU_USER_BASE_REGISTERS_SIZE 0x0BC0
369#define TSU_DMA_EBASE_REGISTERS_SIZE 0x0C00
374#define NPU_REG_REVISION 0x0FC0
375#define NPU_REG_PID4 0x0FD0
376#define NPU_REG_PID5 0x0FD4
377#define NPU_REG_PID6 0x0FD8
378#define NPU_REG_PID7 0x0FDC
379#define NPU_REG_PID0 0x0FE0
380#define NPU_REG_PID1 0x0FE4
381#define NPU_REG_PID2 0x0FE8
382#define NPU_REG_PID3 0x0FEC
383#define NPU_REG_CID0 0x0FF0
384#define NPU_REG_CID1 0x0FF4
385#define NPU_REG_CID2 0x0FF8
386#define NPU_REG_CID3 0x0FFC
387#define ID_REGISTERS_SIZE 0x1000
443 DEVICE_NON_BUFFERABLE = 0,
444 DEVICE_BUFFERABLE = 1,
445 NORMAL_NON_CACHEABLE_NON_BUFFERABLE = 2,
446 NORMAL_NON_CACHEABLE_BUFFERABLE = 3,
447 WRITE_THROUGH_NO_ALLOCATE = 4,
448 WRITE_THROUGH_READ_ALLOCATE = 5,
449 WRITE_THROUGH_WRITE_ALLOCATE = 6,
450 WRITE_THROUGH_READ_AND_WRITE_ALLOCATE = 7,
451 WRITE_BACK_NO_ALLOCATE = 8,
452 WRITE_BACK_READ_ALLOCATE = 9,
453 WRITE_BACK_WRITE_ALLOCATE = 10,
454 WRITE_BACK_READ_AND_WRITE_ALLOCATE = 11,
468 NPU_OP_DEPTHWISE = 3,
470 NPU_OP_ELEMENTWISE = 6,
471 NPU_OP_DMA_START = 16,
472 NPU_OP_DMA_WAIT = 17,
473 NPU_OP_KERNEL_WAIT = 18,
474 NPU_OP_PMU_MASK = 19,
475 NPU_SET_IFM_PAD_TOP = 256,
476 NPU_SET_IFM_PAD_LEFT = 257,
477 NPU_SET_IFM_PAD_RIGHT = 258,
478 NPU_SET_IFM_PAD_BOTTOM = 259,
479 NPU_SET_IFM_DEPTH_M1 = 260,
480 NPU_SET_IFM_PRECISION = 261,
481 NPU_SET_IFM_UPSCALE = 263,
482 NPU_SET_IFM_ZERO_POINT = 265,
483 NPU_SET_IFM_WIDTH0_M1 = 266,
484 NPU_SET_IFM_HEIGHT0_M1 = 267,
485 NPU_SET_IFM_HEIGHT1_M1 = 268,
486 NPU_SET_IFM_IB_END = 269,
487 NPU_SET_IFM_REGION = 271,
488 NPU_SET_OFM_WIDTH_M1 = 273,
489 NPU_SET_OFM_HEIGHT_M1 = 274,
490 NPU_SET_OFM_DEPTH_M1 = 275,
491 NPU_SET_OFM_PRECISION = 276,
492 NPU_SET_OFM_BLK_WIDTH_M1 = 277,
493 NPU_SET_OFM_BLK_HEIGHT_M1 = 278,
494 NPU_SET_OFM_BLK_DEPTH_M1 = 279,
495 NPU_SET_OFM_ZERO_POINT = 280,
496 NPU_SET_OFM_WIDTH0_M1 = 282,
497 NPU_SET_OFM_HEIGHT0_M1 = 283,
498 NPU_SET_OFM_HEIGHT1_M1 = 284,
499 NPU_SET_OFM_REGION = 287,
500 NPU_SET_KERNEL_WIDTH_M1 = 288,
501 NPU_SET_KERNEL_HEIGHT_M1 = 289,
502 NPU_SET_KERNEL_STRIDE = 290,
503 NPU_SET_PARALLEL_MODE = 291,
504 NPU_SET_ACC_FORMAT = 292,
505 NPU_SET_ACTIVATION = 293,
506 NPU_SET_ACTIVATION_MIN = 294,
507 NPU_SET_ACTIVATION_MAX = 295,
508 NPU_SET_WEIGHT_REGION = 296,
509 NPU_SET_SCALE_REGION = 297,
510 NPU_SET_AB_START = 301,
511 NPU_SET_BLOCKDEP = 303,
512 NPU_SET_DMA0_SRC_REGION = 304,
513 NPU_SET_DMA0_DST_REGION = 305,
514 NPU_SET_DMA0_SIZE0 = 306,
515 NPU_SET_DMA0_SIZE1 = 307,
516 NPU_SET_IFM2_BROADCAST = 384,
517 NPU_SET_IFM2_SCALAR = 385,
518 NPU_SET_IFM2_PRECISION = 389,
519 NPU_SET_IFM2_ZERO_POINT = 393,
520 NPU_SET_IFM2_WIDTH0_M1 = 394,
521 NPU_SET_IFM2_HEIGHT0_M1 = 395,
522 NPU_SET_IFM2_HEIGHT1_M1 = 396,
523 NPU_SET_IFM2_IB_START = 397,
524 NPU_SET_IFM2_REGION = 399,
529 NPU_SET_IFM_BASE0 = 0,
530 NPU_SET_IFM_BASE1 = 1,
531 NPU_SET_IFM_BASE2 = 2,
532 NPU_SET_IFM_BASE3 = 3,
533 NPU_SET_IFM_STRIDE_X = 4,
534 NPU_SET_IFM_STRIDE_Y = 5,
535 NPU_SET_IFM_STRIDE_C = 6,
536 NPU_SET_OFM_BASE0 = 16,
537 NPU_SET_OFM_BASE1 = 17,
538 NPU_SET_OFM_BASE2 = 18,
539 NPU_SET_OFM_BASE3 = 19,
540 NPU_SET_OFM_STRIDE_X = 20,
541 NPU_SET_OFM_STRIDE_Y = 21,
542 NPU_SET_OFM_STRIDE_C = 22,
543 NPU_SET_WEIGHT_BASE = 32,
544 NPU_SET_WEIGHT_LENGTH = 33,
545 NPU_SET_SCALE_BASE = 34,
546 NPU_SET_SCALE_LENGTH = 35,
547 NPU_SET_OFM_SCALE = 36,
548 NPU_SET_OPA_SCALE = 37,
549 NPU_SET_OPB_SCALE = 38,
550 NPU_SET_DMA0_SRC = 48,
551 NPU_SET_DMA0_DST = 49,
552 NPU_SET_DMA0_LEN = 50,
553 NPU_SET_DMA0_SKIP0 = 51,
554 NPU_SET_DMA0_SKIP1 = 52,
555 NPU_SET_IFM2_BASE0 = 128,
556 NPU_SET_IFM2_BASE1 = 129,
557 NPU_SET_IFM2_BASE2 = 130,
558 NPU_SET_IFM2_BASE3 = 131,
559 NPU_SET_IFM2_STRIDE_X = 132,
560 NPU_SET_IFM2_STRIDE_Y = 133,
561 NPU_SET_IFM2_STRIDE_C = 134,
562 NPU_SET_WEIGHT1_BASE = 144,
563 NPU_SET_WEIGHT1_LENGTH = 145,
564 NPU_SET_SCALE1_BASE = 146,
565 NPU_SET_SCALE1_LENGTH = 147,
660 AXI0_OUTSTANDING_COUNTER0 = 0,
661 AXI0_OUTSTANDING_COUNTER1 = 1,
662 AXI1_OUTSTANDING_COUNTER2 = 2,
663 AXI1_OUTSTANDING_COUNTER3 = 3,
694 CC_STALLED_ON_BLOCKDEP = 33,
695 CC_STALLED_ON_SHRAM_RECONFIG = 34,
698 MAC_ACTIVE_8BIT = 49,
699 MAC_ACTIVE_16BIT = 50,
701 MAC_STALLED_BY_WD_ACC = 52,
702 MAC_STALLED_BY_WD = 53,
703 MAC_STALLED_BY_ACC = 54,
704 MAC_STALLED_BY_IB = 55,
705 MAC_ACTIVE_32BIT = 56,
706 MAC_STALLED_BY_INT_W = 57,
707 MAC_STALLED_BY_INT_ACC = 58,
710 AO_ACTIVE_16BIT = 66,
711 AO_STALLED_BY_OFMP_OB = 67,
712 AO_STALLED_BY_OFMP = 68,
713 AO_STALLED_BY_OB = 69,
714 AO_STALLED_BY_ACC_IB = 70,
715 AO_STALLED_BY_ACC = 71,
716 AO_STALLED_BY_IB = 72,
719 WD_STALLED_BY_WS = 82,
720 WD_STALLED_BY_WD_BUF = 83,
721 WD_PARSE_ACTIVE = 84,
722 WD_PARSE_STALLED = 85,
723 WD_PARSE_STALLED_IN = 86,
724 WD_PARSE_STALLED_OUT = 87,
729 AXI0_RD_TRANS_ACCEPTED = 128,
730 AXI0_RD_TRANS_COMPLETED = 129,
731 AXI0_RD_DATA_BEAT_RECEIVED = 130,
732 AXI0_RD_TRAN_REQ_STALLED = 131,
733 AXI0_WR_TRANS_ACCEPTED = 132,
734 AXI0_WR_TRANS_COMPLETED_M = 133,
735 AXI0_WR_TRANS_COMPLETED_S = 134,
736 AXI0_WR_DATA_BEAT_WRITTEN = 135,
737 AXI0_WR_TRAN_REQ_STALLED = 136,
738 AXI0_WR_DATA_BEAT_STALLED = 137,
739 AXI0_ENABLED_CYCLES = 140,
740 AXI0_RD_STALL_LIMIT = 142,
741 AXI0_WR_STALL_LIMIT = 143,
742 AXI_LATENCY_ANY = 160,
743 AXI_LATENCY_32 = 161,
744 AXI_LATENCY_64 = 162,
745 AXI_LATENCY_128 = 163,
746 AXI_LATENCY_256 = 164,
747 AXI_LATENCY_512 = 165,
748 AXI_LATENCY_1024 = 166,
751 AXI1_RD_TRANS_ACCEPTED = 384,
752 AXI1_RD_TRANS_COMPLETED = 385,
753 AXI1_RD_DATA_BEAT_RECEIVED = 386,
754 AXI1_RD_TRAN_REQ_STALLED = 387,
755 AXI1_WR_TRANS_ACCEPTED = 388,
756 AXI1_WR_TRANS_COMPLETED_M = 389,
757 AXI1_WR_TRANS_COMPLETED_S = 390,
758 AXI1_WR_DATA_BEAT_WRITTEN = 391,
759 AXI1_WR_TRAN_REQ_STALLED = 392,
760 AXI1_WR_DATA_BEAT_STALLED = 393,
761 AXI1_ENABLED_CYCLES = 396,
762 AXI1_RD_STALL_LIMIT = 398,
763 AXI1_WR_STALL_LIMIT = 399,
793enum class state : uint8_t
817 PART_KERNEL_FIRST = 1,
1253#ifdef NPU_DISASSEMBLE
1255static const char *acc_format_str[] = {
1261static const char *activation_clip_range_str[] = {
1262 "ACTIVATION_CLIP_RANGE_OFM_PRECISION",
1264 "ACTIVATION_CLIP_RANGE_FORCE_UINT8",
1265 "ACTIVATION_CLIP_RANGE_FORCE_INT8",
1267 "ACTIVATION_CLIP_RANGE_FORCE_INT16",
1270static const char *activation_format_str[] = {
1271 "ACTIVATION_FORMAT_NHWC",
1272 "ACTIVATION_FORMAT_NHCWB16",
1275static const char *activation_function_str[] = {
1276 "ACTIVATION_FUNCTION_RELU",
1279 "ACTIVATION_FUNCTION_TANH",
1280 "ACTIVATION_FUNCTION_SIGMOID",
1292 "ACTIVATION_FUNCTION_TABLE_0",
1293 "ACTIVATION_FUNCTION_TABLE_1",
1294 "ACTIVATION_FUNCTION_TABLE_2",
1295 "ACTIVATION_FUNCTION_TABLE_3",
1296 "ACTIVATION_FUNCTION_TABLE_4",
1297 "ACTIVATION_FUNCTION_TABLE_5",
1298 "ACTIVATION_FUNCTION_TABLE_6",
1299 "ACTIVATION_FUNCTION_TABLE_7",
1302static const char *activation_precision_str[] = {
1303 "ACTIVATION_PRECISION_B8",
1304 "ACTIVATION_PRECISION_B16",
1305 "ACTIVATION_PRECISION_B32",
1306 "ACTIVATION_PRECISION_B64",
1309static const char *activation_type_str[] = {
1310 "ACTIVATION_TYPE_UNSIGNED",
1311 "ACTIVATION_TYPE_SIGNED",
1314static const char *axi_mem_encoding_str[] = {
1315 "AXI_MEM_ENCODING_DEVICE_NON_BUFFERABLE",
1316 "AXI_MEM_ENCODING_DEVICE_BUFFERABLE",
1317 "AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_NON_BUFFERABLE",
1318 "AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_BUFFERABLE",
1319 "AXI_MEM_ENCODING_WRITE_THROUGH_NO_ALLOCATE",
1320 "AXI_MEM_ENCODING_WRITE_THROUGH_READ_ALLOCATE",
1321 "AXI_MEM_ENCODING_WRITE_THROUGH_WRITE_ALLOCATE",
1322 "AXI_MEM_ENCODING_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE",
1323 "AXI_MEM_ENCODING_WRITE_BACK_NO_ALLOCATE",
1324 "AXI_MEM_ENCODING_WRITE_BACK_READ_ALLOCATE",
1325 "AXI_MEM_ENCODING_WRITE_BACK_WRITE_ALLOCATE",
1326 "AXI_MEM_ENCODING_WRITE_BACK_READ_AND_WRITE_ALLOCATE",
1329static const char *broadcast_mode_str[] = {
1330 "BROADCAST_MODE_DISABLE",
1331 "BROADCAST_MODE_ENABLE",
1334static const char *cmd0_opcode_str[] = {
1335 "CMD0_OPCODE_NPU_OP_STOP",
1336 "CMD0_OPCODE_NPU_OP_IRQ",
1337 "CMD0_OPCODE_NPU_OP_CONV",
1338 "CMD0_OPCODE_NPU_OP_DEPTHWISE",
1340 "CMD0_OPCODE_NPU_OP_POOL",
1341 "CMD0_OPCODE_NPU_OP_ELEMENTWISE",
1351 "CMD0_OPCODE_NPU_OP_DMA_START",
1352 "CMD0_OPCODE_NPU_OP_DMA_WAIT",
1353 "CMD0_OPCODE_NPU_OP_KERNEL_WAIT",
1354 "CMD0_OPCODE_NPU_OP_PMU_MASK",
1591 "CMD0_OPCODE_NPU_SET_IFM_PAD_TOP",
1592 "CMD0_OPCODE_NPU_SET_IFM_PAD_LEFT",
1593 "CMD0_OPCODE_NPU_SET_IFM_PAD_RIGHT",
1594 "CMD0_OPCODE_NPU_SET_IFM_PAD_BOTTOM",
1595 "CMD0_OPCODE_NPU_SET_IFM_DEPTH_M1",
1596 "CMD0_OPCODE_NPU_SET_IFM_PRECISION",
1598 "CMD0_OPCODE_NPU_SET_IFM_UPSCALE",
1600 "CMD0_OPCODE_NPU_SET_IFM_ZERO_POINT",
1601 "CMD0_OPCODE_NPU_SET_IFM_WIDTH0_M1",
1602 "CMD0_OPCODE_NPU_SET_IFM_HEIGHT0_M1",
1603 "CMD0_OPCODE_NPU_SET_IFM_HEIGHT1_M1",
1604 "CMD0_OPCODE_NPU_SET_IFM_IB_END",
1606 "CMD0_OPCODE_NPU_SET_IFM_REGION",
1608 "CMD0_OPCODE_NPU_SET_OFM_WIDTH_M1",
1609 "CMD0_OPCODE_NPU_SET_OFM_HEIGHT_M1",
1610 "CMD0_OPCODE_NPU_SET_OFM_DEPTH_M1",
1611 "CMD0_OPCODE_NPU_SET_OFM_PRECISION",
1612 "CMD0_OPCODE_NPU_SET_OFM_BLK_WIDTH_M1",
1613 "CMD0_OPCODE_NPU_SET_OFM_BLK_HEIGHT_M1",
1614 "CMD0_OPCODE_NPU_SET_OFM_BLK_DEPTH_M1",
1615 "CMD0_OPCODE_NPU_SET_OFM_ZERO_POINT",
1617 "CMD0_OPCODE_NPU_SET_OFM_WIDTH0_M1",
1618 "CMD0_OPCODE_NPU_SET_OFM_HEIGHT0_M1",
1619 "CMD0_OPCODE_NPU_SET_OFM_HEIGHT1_M1",
1622 "CMD0_OPCODE_NPU_SET_OFM_REGION",
1623 "CMD0_OPCODE_NPU_SET_KERNEL_WIDTH_M1",
1624 "CMD0_OPCODE_NPU_SET_KERNEL_HEIGHT_M1",
1625 "CMD0_OPCODE_NPU_SET_KERNEL_STRIDE",
1626 "CMD0_OPCODE_NPU_SET_PARALLEL_MODE",
1627 "CMD0_OPCODE_NPU_SET_ACC_FORMAT",
1628 "CMD0_OPCODE_NPU_SET_ACTIVATION",
1629 "CMD0_OPCODE_NPU_SET_ACTIVATION_MIN",
1630 "CMD0_OPCODE_NPU_SET_ACTIVATION_MAX",
1631 "CMD0_OPCODE_NPU_SET_WEIGHT_REGION",
1632 "CMD0_OPCODE_NPU_SET_SCALE_REGION",
1636 "CMD0_OPCODE_NPU_SET_AB_START",
1638 "CMD0_OPCODE_NPU_SET_BLOCKDEP",
1639 "CMD0_OPCODE_NPU_SET_DMA0_SRC_REGION",
1640 "CMD0_OPCODE_NPU_SET_DMA0_DST_REGION",
1641 "CMD0_OPCODE_NPU_SET_DMA0_SIZE0",
1642 "CMD0_OPCODE_NPU_SET_DMA0_SIZE1",
1719 "CMD0_OPCODE_NPU_SET_IFM2_BROADCAST",
1720 "CMD0_OPCODE_NPU_SET_IFM2_SCALAR",
1724 "CMD0_OPCODE_NPU_SET_IFM2_PRECISION",
1728 "CMD0_OPCODE_NPU_SET_IFM2_ZERO_POINT",
1729 "CMD0_OPCODE_NPU_SET_IFM2_WIDTH0_M1",
1730 "CMD0_OPCODE_NPU_SET_IFM2_HEIGHT0_M1",
1731 "CMD0_OPCODE_NPU_SET_IFM2_HEIGHT1_M1",
1732 "CMD0_OPCODE_NPU_SET_IFM2_IB_START",
1734 "CMD0_OPCODE_NPU_SET_IFM2_REGION",
1737static const char *cmd1_opcode_str[] = {
1738 "CMD1_OPCODE_NPU_SET_IFM_BASE0",
1739 "CMD1_OPCODE_NPU_SET_IFM_BASE1",
1740 "CMD1_OPCODE_NPU_SET_IFM_BASE2",
1741 "CMD1_OPCODE_NPU_SET_IFM_BASE3",
1742 "CMD1_OPCODE_NPU_SET_IFM_STRIDE_X",
1743 "CMD1_OPCODE_NPU_SET_IFM_STRIDE_Y",
1744 "CMD1_OPCODE_NPU_SET_IFM_STRIDE_C",
1754 "CMD1_OPCODE_NPU_SET_OFM_BASE0",
1755 "CMD1_OPCODE_NPU_SET_OFM_BASE1",
1756 "CMD1_OPCODE_NPU_SET_OFM_BASE2",
1757 "CMD1_OPCODE_NPU_SET_OFM_BASE3",
1758 "CMD1_OPCODE_NPU_SET_OFM_STRIDE_X",
1759 "CMD1_OPCODE_NPU_SET_OFM_STRIDE_Y",
1760 "CMD1_OPCODE_NPU_SET_OFM_STRIDE_C",
1770 "CMD1_OPCODE_NPU_SET_WEIGHT_BASE",
1771 "CMD1_OPCODE_NPU_SET_WEIGHT_LENGTH",
1772 "CMD1_OPCODE_NPU_SET_SCALE_BASE",
1773 "CMD1_OPCODE_NPU_SET_SCALE_LENGTH",
1774 "CMD1_OPCODE_NPU_SET_OFM_SCALE",
1775 "CMD1_OPCODE_NPU_SET_OPA_SCALE",
1776 "CMD1_OPCODE_NPU_SET_OPB_SCALE",
1786 "CMD1_OPCODE_NPU_SET_DMA0_SRC",
1787 "CMD1_OPCODE_NPU_SET_DMA0_DST",
1788 "CMD1_OPCODE_NPU_SET_DMA0_LEN",
1789 "CMD1_OPCODE_NPU_SET_DMA0_SKIP0",
1790 "CMD1_OPCODE_NPU_SET_DMA0_SKIP1",
1866 "CMD1_OPCODE_NPU_SET_IFM2_BASE0",
1867 "CMD1_OPCODE_NPU_SET_IFM2_BASE1",
1868 "CMD1_OPCODE_NPU_SET_IFM2_BASE2",
1869 "CMD1_OPCODE_NPU_SET_IFM2_BASE3",
1870 "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_X",
1871 "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_Y",
1872 "CMD1_OPCODE_NPU_SET_IFM2_STRIDE_C",
1882 "CMD1_OPCODE_NPU_SET_WEIGHT1_BASE",
1883 "CMD1_OPCODE_NPU_SET_WEIGHT1_LENGTH",
1884 "CMD1_OPCODE_NPU_SET_SCALE1_BASE",
1885 "CMD1_OPCODE_NPU_SET_SCALE1_LENGTH",
1888static const char *cmd_ctrl_str[] = {
1889 "CMD_CTRL_CMD0_CTRL",
1890 "CMD_CTRL_CMD1_CTRL",
1893static const char *custom_dma_str[] = {
1894 "CUSTOM_DMA_NOT_IMPLEMENTED",
1895 "CUSTOM_DMA_IMPLEMENTED",
1898static const char *dma_fault_src_str[] = {
1899 "DMA_FAULT_SRC_AXI_M0",
1900 "DMA_FAULT_SRC_AXI_M1",
1903static const char *dma_region_mode_str[] = {
1904 "DMA_REGION_MODE_EXTERNAL",
1905 "DMA_REGION_MODE_INTERNAL",
1908static const char *dma_stride_mode_str[] = {
1909 "DMA_STRIDE_MODE_D1",
1910 "DMA_STRIDE_MODE_D2",
1911 "DMA_STRIDE_MODE_D3",
1914static const char *elementwise_mode_str[] = {
1915 "ELEMENTWISE_MODE_MUL",
1916 "ELEMENTWISE_MODE_ADD",
1917 "ELEMENTWISE_MODE_SUB",
1918 "ELEMENTWISE_MODE_MIN",
1919 "ELEMENTWISE_MODE_MAX",
1920 "ELEMENTWISE_MODE_LRELU",
1921 "ELEMENTWISE_MODE_ABS",
1922 "ELEMENTWISE_MODE_CLZ",
1923 "ELEMENTWISE_MODE_SHR",
1924 "ELEMENTWISE_MODE_SHL",
1927static const char *functional_safety_str[] = {
1928 "FUNCTIONAL_SAFETY_NOT_IMPLEMENTED",
1929 "FUNCTIONAL_SAFETY_IMPLEMENTED",
1932static const char *ifm2_operand_order_str[] = {
1933 "IFM2_OPERAND_ORDER_ORDER_B",
1934 "IFM2_OPERAND_ORDER_ORDER_A",
1937static const char *ifm_scale_mode_str[] = {
1938 "IFM_SCALE_MODE_OPA_OPB_16",
1939 "IFM_SCALE_MODE_OPA_32",
1940 "IFM_SCALE_MODE_OPB_32",
1943static const char *ifm_upscale_mode_str[] = {
1944 "IFM_UPSCALE_MODE_NONE",
1945 "IFM_UPSCALE_MODE_NEAREST",
1946 "IFM_UPSCALE_MODE_ZEROS",
1949static const char *kernel_decomposition_str[] = {
1950 "KERNEL_DECOMPOSITION_D8X8",
1951 "KERNEL_DECOMPOSITION_D4X4",
1954static const char *kernel_dilation_str[] = {
1955 "KERNEL_DILATION_NONE",
1956 "KERNEL_DILATION_X2",
1959static const char *max_beats_str[] = {
1965static const char *mem_attr_str[] = {
1966 "MEM_ATTR_AXI0_OUTSTANDING_COUNTER0",
1967 "MEM_ATTR_AXI0_OUTSTANDING_COUNTER1",
1968 "MEM_ATTR_AXI1_OUTSTANDING_COUNTER2",
1969 "MEM_ATTR_AXI1_OUTSTANDING_COUNTER3",
1972static const char *ofm_scale_mode_str[] = {
1973 "OFM_SCALE_MODE_PER_CHANNEL",
1974 "OFM_SCALE_MODE_GLOBAL",
1977static const char *parallel_mode_str[] = {
1978 "PARALLEL_MODE_SINGLE_CORE",
1979 "PARALLEL_MODE_DUAL_CORE_DEPTH",
1982static const char *pmu_axi_channel_str[] = {
1983 "PMU_AXI_CHANNEL_RD_CMD",
1984 "PMU_AXI_CHANNEL_RD_IFM",
1985 "PMU_AXI_CHANNEL_RD_WEIGHTS",
1986 "PMU_AXI_CHANNEL_RD_SCALE_BIAS",
1987 "PMU_AXI_CHANNEL_RD_MEM2MEM",
1991 "PMU_AXI_CHANNEL_WR_OFM",
1992 "PMU_AXI_CHANNEL_WR_MEM2MEM",
1995static const char *pmu_event_str[] = {
1996 "PMU_EVENT_NO_EVENT",
2028 "PMU_EVENT_NPU_IDLE",
2029 "PMU_EVENT_CC_STALLED_ON_BLOCKDEP",
2030 "PMU_EVENT_CC_STALLED_ON_SHRAM_RECONFIG",
2031 "PMU_EVENT_NPU_ACTIVE",
2044 "PMU_EVENT_MAC_ACTIVE",
2045 "PMU_EVENT_MAC_ACTIVE_8BIT",
2046 "PMU_EVENT_MAC_ACTIVE_16BIT",
2047 "PMU_EVENT_MAC_DPU_ACTIVE",
2048 "PMU_EVENT_MAC_STALLED_BY_WD_ACC",
2049 "PMU_EVENT_MAC_STALLED_BY_WD",
2050 "PMU_EVENT_MAC_STALLED_BY_ACC",
2051 "PMU_EVENT_MAC_STALLED_BY_IB",
2052 "PMU_EVENT_MAC_ACTIVE_32BIT",
2053 "PMU_EVENT_MAC_STALLED_BY_INT_W",
2054 "PMU_EVENT_MAC_STALLED_BY_INT_ACC",
2060 "PMU_EVENT_AO_ACTIVE",
2061 "PMU_EVENT_AO_ACTIVE_8BIT",
2062 "PMU_EVENT_AO_ACTIVE_16BIT",
2063 "PMU_EVENT_AO_STALLED_BY_OFMP_OB",
2064 "PMU_EVENT_AO_STALLED_BY_OFMP",
2065 "PMU_EVENT_AO_STALLED_BY_OB",
2066 "PMU_EVENT_AO_STALLED_BY_ACC_IB",
2067 "PMU_EVENT_AO_STALLED_BY_ACC",
2068 "PMU_EVENT_AO_STALLED_BY_IB",
2076 "PMU_EVENT_WD_ACTIVE",
2077 "PMU_EVENT_WD_STALLED",
2078 "PMU_EVENT_WD_STALLED_BY_WS",
2079 "PMU_EVENT_WD_STALLED_BY_WD_BUF",
2080 "PMU_EVENT_WD_PARSE_ACTIVE",
2081 "PMU_EVENT_WD_PARSE_STALLED",
2082 "PMU_EVENT_WD_PARSE_STALLED_IN",
2083 "PMU_EVENT_WD_PARSE_STALLED_OUT",
2084 "PMU_EVENT_WD_TRANS_WS",
2085 "PMU_EVENT_WD_TRANS_WB",
2086 "PMU_EVENT_WD_TRANS_DW0",
2087 "PMU_EVENT_WD_TRANS_DW1",
2124 "PMU_EVENT_AXI0_RD_TRANS_ACCEPTED",
2125 "PMU_EVENT_AXI0_RD_TRANS_COMPLETED",
2126 "PMU_EVENT_AXI0_RD_DATA_BEAT_RECEIVED",
2127 "PMU_EVENT_AXI0_RD_TRAN_REQ_STALLED",
2128 "PMU_EVENT_AXI0_WR_TRANS_ACCEPTED",
2129 "PMU_EVENT_AXI0_WR_TRANS_COMPLETED_M",
2130 "PMU_EVENT_AXI0_WR_TRANS_COMPLETED_S",
2131 "PMU_EVENT_AXI0_WR_DATA_BEAT_WRITTEN",
2132 "PMU_EVENT_AXI0_WR_TRAN_REQ_STALLED",
2133 "PMU_EVENT_AXI0_WR_DATA_BEAT_STALLED",
2136 "PMU_EVENT_AXI0_ENABLED_CYCLES",
2138 "PMU_EVENT_AXI0_RD_STALL_LIMIT",
2139 "PMU_EVENT_AXI0_WR_STALL_LIMIT",
2156 "PMU_EVENT_AXI_LATENCY_ANY",
2157 "PMU_EVENT_AXI_LATENCY_32",
2158 "PMU_EVENT_AXI_LATENCY_64",
2159 "PMU_EVENT_AXI_LATENCY_128",
2160 "PMU_EVENT_AXI_LATENCY_256",
2161 "PMU_EVENT_AXI_LATENCY_512",
2162 "PMU_EVENT_AXI_LATENCY_1024",
2172 "PMU_EVENT_ECC_DMA",
2173 "PMU_EVENT_ECC_SB0",
2380 "PMU_EVENT_AXI1_RD_TRANS_ACCEPTED",
2381 "PMU_EVENT_AXI1_RD_TRANS_COMPLETED",
2382 "PMU_EVENT_AXI1_RD_DATA_BEAT_RECEIVED",
2383 "PMU_EVENT_AXI1_RD_TRAN_REQ_STALLED",
2384 "PMU_EVENT_AXI1_WR_TRANS_ACCEPTED",
2385 "PMU_EVENT_AXI1_WR_TRANS_COMPLETED_M",
2386 "PMU_EVENT_AXI1_WR_TRANS_COMPLETED_S",
2387 "PMU_EVENT_AXI1_WR_DATA_BEAT_WRITTEN",
2388 "PMU_EVENT_AXI1_WR_TRAN_REQ_STALLED",
2389 "PMU_EVENT_AXI1_WR_DATA_BEAT_STALLED",
2392 "PMU_EVENT_AXI1_ENABLED_CYCLES",
2394 "PMU_EVENT_AXI1_RD_STALL_LIMIT",
2395 "PMU_EVENT_AXI1_WR_STALL_LIMIT",
2429 "PMU_EVENT_ECC_SB1",
2432static const char *pooling_mode_str[] = {
2434 "POOLING_MODE_AVERAGE",
2435 "POOLING_MODE_REDUCE_SUM",
2438static const char *privilege_level_str[] = {
2439 "PRIVILEGE_LEVEL_USER",
2440 "PRIVILEGE_LEVEL_PRIVILEGED",
2443static const char *round_mode_str[] = {
2445 "ROUND_MODE_TRUNCATE",
2446 "ROUND_MODE_NATURAL",
2449static const char *security_level_str[] = {
2450 "SECURITY_LEVEL_SECURE",
2451 "SECURITY_LEVEL_NON_SECURE",
2454static const char *state_str[] = {
2459static const char *wd_core_slice_state_str[] = {
2460 "WD_CORE_SLICE_STATE_HEADER",
2461 "WD_CORE_SLICE_STATE_PALETTE",
2462 "WD_CORE_SLICE_STATE_WEIGHTS",
2465static const char *wd_ctrl_state_str[] = {
2466 "WD_CTRL_STATE_IDLE",
2467 "WD_CTRL_STATE_DRAIN",
2468 "WD_CTRL_STATE_OFD_INIT",
2469 "WD_CTRL_STATE_OFD_RUN",
2472static const char *weight_order_str[] = {
2473 "WEIGHT_ORDER_DEPTH_FIRST",
2474 "WEIGHT_ORDER_PART_KERNEL_FIRST",
2488 uint32_t version_status : 4;
2489 uint32_t version_minor : 4;
2490 uint32_t version_major : 4;
2491 uint32_t product_major : 4;
2492 uint32_t arch_patch_rev : 4;
2511 void operator=(uint32_t
value)
volatile
2519 operator uint32_t()
volatile
2523 id_r copy()
volatile
2527 CONSTEXPR uint32_t get_version_status()
const
2529 uint32_t
value = ((1U << 4) - 1) & (word0 >> 0);
2532 uint32_t get_version_status()
const volatile
2534 uint32_t
value = ((1U << 4) - 1) & (word0 >> 0);
2539 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) &
value) << 0);
2542 volatile id_r &set_version_status(uint32_t
value)
volatile
2544 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) &
value) << 0);
2547 CONSTEXPR uint32_t get_version_minor()
const
2549 uint32_t
value = ((1U << 4) - 1) & (word0 >> 4);
2552 uint32_t get_version_minor()
const volatile
2554 uint32_t
value = ((1U << 4) - 1) & (word0 >> 4);
2559 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
value) << 4);
2562 volatile id_r &set_version_minor(uint32_t
value)
volatile
2564 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
value) << 4);
2567 CONSTEXPR uint32_t get_version_major()
const
2569 uint32_t
value = ((1U << 4) - 1) & (word0 >> 8);
2572 uint32_t get_version_major()
const volatile
2574 uint32_t
value = ((1U << 4) - 1) & (word0 >> 8);
2579 word0 = (((~((1U << 4) - 1)) << 8) & word0) | ((((1U << 4) - 1) &
value) << 8);
2582 volatile id_r &set_version_major(uint32_t
value)
volatile
2584 word0 = (((~((1U << 4) - 1)) << 8) & word0) | ((((1U << 4) - 1) &
value) << 8);
2587 CONSTEXPR uint32_t get_product_major()
const
2589 uint32_t
value = ((1U << 4) - 1) & (word0 >> 12);
2592 uint32_t get_product_major()
const volatile
2594 uint32_t
value = ((1U << 4) - 1) & (word0 >> 12);
2599 word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) &
value) << 12);
2602 volatile id_r &set_product_major(uint32_t
value)
volatile
2604 word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) &
value) << 12);
2607 CONSTEXPR uint32_t get_arch_patch_rev()
const
2609 uint32_t
value = ((1U << 4) - 1) & (word0 >> 16);
2612 uint32_t get_arch_patch_rev()
const volatile
2614 uint32_t
value = ((1U << 4) - 1) & (word0 >> 16);
2619 word0 = (((~((1U << 4) - 1)) << 16) & word0) | ((((1U << 4) - 1) &
value) << 16);
2622 volatile id_r &set_arch_patch_rev(uint32_t
value)
volatile
2624 word0 = (((~((1U << 4) - 1)) << 16) & word0) | ((((1U << 4) - 1) &
value) << 16);
2627 CONSTEXPR uint32_t get_arch_minor_rev()
const
2629 uint32_t
value = ((1U << 8) - 1) & (word0 >> 20);
2632 uint32_t get_arch_minor_rev()
const volatile
2634 uint32_t
value = ((1U << 8) - 1) & (word0 >> 20);
2639 word0 = (((~((1U << 8) - 1)) << 20) & word0) | ((((1U << 8) - 1) &
value) << 20);
2642 volatile id_r &set_arch_minor_rev(uint32_t
value)
volatile
2644 word0 = (((~((1U << 8) - 1)) << 20) & word0) | ((((1U << 8) - 1) &
value) << 20);
2647 CONSTEXPR uint32_t get_arch_major_rev()
const
2649 uint32_t
value = ((1U << 4) - 1) & (word0 >> 28);
2652 uint32_t get_arch_major_rev()
const volatile
2654 uint32_t
value = ((1U << 4) - 1) & (word0 >> 28);
2659 word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) &
value) << 28);
2662 volatile id_r &set_arch_major_rev(uint32_t
value)
volatile
2664 word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) &
value) << 28);
2679 uint32_t irq_raised : 1;
2684 uint32_t reset_status : 1;
2688 cmd_parse_error : 1;
2689 uint32_t cmd_end_reached : 1;
2691 uint32_t pmu_irq_raised : 1;
2692 uint32_t wd_fault : 1;
2694 uint32_t ecc_fault : 1;
2696 uint32_t reserved0 : 2;
2697 uint32_t faulting_interface : 1;
2698 uint32_t faulting_channel : 4;
2700 uint32_t irq_history_mask : 16;
2715 void operator=(uint32_t
value)
volatile
2723 operator uint32_t()
volatile
2731 CONSTEXPR NPU_NAMESPACE::state get_state()
const
2733 NPU_NAMESPACE::state
value =
static_cast<NPU_NAMESPACE::state
>(((1U << 1) - 1) & (word0 >> 0));
2736 NPU_NAMESPACE::state get_state()
const volatile
2738 NPU_NAMESPACE::state
value =
static_cast<NPU_NAMESPACE::state
>(((1U << 1) - 1) & (word0 >> 0));
2743 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 0);
2746 volatile status_r &set_state(NPU_NAMESPACE::state
value)
volatile
2748 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 0);
2751 CONSTEXPR uint32_t get_irq_raised()
const
2753 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
2756 uint32_t get_irq_raised()
const volatile
2758 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
2763 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
2768 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
2771 CONSTEXPR uint32_t get_bus_status()
const
2773 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
2776 uint32_t get_bus_status()
const volatile
2778 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
2783 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
2788 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
2791 CONSTEXPR uint32_t get_reset_status()
const
2793 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
2796 uint32_t get_reset_status()
const volatile
2798 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
2803 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
2806 volatile status_r &set_reset_status(uint32_t
value)
volatile
2808 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
2811 CONSTEXPR uint32_t get_cmd_parse_error()
const
2813 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
2816 uint32_t get_cmd_parse_error()
const volatile
2818 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
2823 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
2826 volatile status_r &set_cmd_parse_error(uint32_t
value)
volatile
2828 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
2831 CONSTEXPR uint32_t get_cmd_end_reached()
const
2833 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
2836 uint32_t get_cmd_end_reached()
const volatile
2838 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
2843 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
2846 volatile status_r &set_cmd_end_reached(uint32_t
value)
volatile
2848 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
2851 CONSTEXPR uint32_t get_pmu_irq_raised()
const
2853 uint32_t
value = ((1U << 1) - 1) & (word0 >> 6);
2856 uint32_t get_pmu_irq_raised()
const volatile
2858 uint32_t
value = ((1U << 1) - 1) & (word0 >> 6);
2863 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) &
value) << 6);
2866 volatile status_r &set_pmu_irq_raised(uint32_t
value)
volatile
2868 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) &
value) << 6);
2873 uint32_t
value = ((1U << 1) - 1) & (word0 >> 7);
2876 uint32_t get_wd_fault()
const volatile
2878 uint32_t
value = ((1U << 1) - 1) & (word0 >> 7);
2883 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) &
value) << 7);
2888 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) &
value) << 7);
2891 CONSTEXPR uint32_t get_ecc_fault()
const
2893 uint32_t
value = ((1U << 1) - 1) & (word0 >> 8);
2896 uint32_t get_ecc_fault()
const volatile
2898 uint32_t
value = ((1U << 1) - 1) & (word0 >> 8);
2903 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) &
value) << 8);
2908 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) &
value) << 8);
2911 CONSTEXPR NPU_NAMESPACE::dma_fault_src get_faulting_interface()
const
2913 NPU_NAMESPACE::dma_fault_src
value =
static_cast<NPU_NAMESPACE::dma_fault_src
>(((1U << 1) - 1) & (word0 >> 11));
2916 NPU_NAMESPACE::dma_fault_src get_faulting_interface()
const volatile
2918 NPU_NAMESPACE::dma_fault_src
value =
static_cast<NPU_NAMESPACE::dma_fault_src
>(((1U << 1) - 1) & (word0 >> 11));
2923 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 11);
2926 volatile status_r &set_faulting_interface(NPU_NAMESPACE::dma_fault_src
value)
volatile
2928 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 11);
2931 CONSTEXPR uint32_t get_faulting_channel()
const
2933 uint32_t
value = ((1U << 4) - 1) & (word0 >> 12);
2936 uint32_t get_faulting_channel()
const volatile
2938 uint32_t
value = ((1U << 4) - 1) & (word0 >> 12);
2943 word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) &
value) << 12);
2946 volatile status_r &set_faulting_channel(uint32_t
value)
volatile
2948 word0 = (((~((1U << 4) - 1)) << 12) & word0) | ((((1U << 4) - 1) &
value) << 12);
2951 CONSTEXPR uint32_t get_irq_history_mask()
const
2953 uint32_t
value = ((1U << 16) - 1) & (word0 >> 16);
2956 uint32_t get_irq_history_mask()
const volatile
2958 uint32_t
value = ((1U << 16) - 1) & (word0 >> 16);
2963 word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) &
value) << 16);
2966 volatile status_r &set_irq_history_mask(uint32_t
value)
volatile
2968 word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) &
value) << 16);
2982 uint32_t transition_to_running_state : 1;
2984 uint32_t clear_irq : 1;
2985 uint32_t clock_q_enable : 1;
2987 uint32_t power_q_enable : 1;
2990 uint32_t reserved0 : 11;
2991 uint32_t clear_irq_history : 16;
3006 void operator=(uint32_t
value)
volatile
3014 operator uint32_t()
volatile
3018 cmd_r copy()
volatile
3022 CONSTEXPR uint32_t get_transition_to_running_state()
const
3024 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
3027 uint32_t get_transition_to_running_state()
const volatile
3029 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
3034 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
3037 volatile cmd_r &set_transition_to_running_state(uint32_t
value)
volatile
3039 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
3042 CONSTEXPR uint32_t get_clear_irq()
const
3044 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
3047 uint32_t get_clear_irq()
const volatile
3049 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
3054 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
3057 volatile cmd_r &set_clear_irq(uint32_t
value)
volatile
3059 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
3062 CONSTEXPR uint32_t get_clock_q_enable()
const
3064 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
3067 uint32_t get_clock_q_enable()
const volatile
3069 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
3074 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
3077 volatile cmd_r &set_clock_q_enable(uint32_t
value)
volatile
3079 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
3082 CONSTEXPR uint32_t get_power_q_enable()
const
3084 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
3087 uint32_t get_power_q_enable()
const volatile
3089 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
3094 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
3097 volatile cmd_r &set_power_q_enable(uint32_t
value)
volatile
3099 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
3102 CONSTEXPR uint32_t get_stop_request()
const
3104 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
3107 uint32_t get_stop_request()
const volatile
3109 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
3114 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
3117 volatile cmd_r &set_stop_request(uint32_t
value)
volatile
3119 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
3122 CONSTEXPR uint32_t get_clear_irq_history()
const
3124 uint32_t
value = ((1U << 16) - 1) & (word0 >> 16);
3127 uint32_t get_clear_irq_history()
const volatile
3129 uint32_t
value = ((1U << 16) - 1) & (word0 >> 16);
3134 word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) &
value) << 16);
3137 volatile cmd_r &set_clear_irq_history(uint32_t
value)
volatile
3139 word0 = (((~((1U << 16) - 1)) << 16) & word0) | ((((1U << 16) - 1) &
value) << 16);
3153 uint32_t pending_CPL : 1;
3154 uint32_t pending_CSL : 1;
3155 uint32_t reserved0 : 30;
3170 void operator=(uint32_t
value)
volatile
3178 operator uint32_t()
volatile
3186 CONSTEXPR NPU_NAMESPACE::privilege_level get_pending_CPL()
const
3188 NPU_NAMESPACE::privilege_level
value =
3189 static_cast<NPU_NAMESPACE::privilege_level
>(((1U << 1) - 1) & (word0 >> 0));
3192 NPU_NAMESPACE::privilege_level get_pending_CPL()
const volatile
3194 NPU_NAMESPACE::privilege_level
value =
3195 static_cast<NPU_NAMESPACE::privilege_level
>(((1U << 1) - 1) & (word0 >> 0));
3200 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 0);
3203 volatile reset_r &set_pending_CPL(NPU_NAMESPACE::privilege_level
value)
volatile
3205 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 0);
3208 CONSTEXPR NPU_NAMESPACE::security_level get_pending_CSL()
const
3210 NPU_NAMESPACE::security_level
value =
3211 static_cast<NPU_NAMESPACE::security_level
>(((1U << 1) - 1) & (word0 >> 1));
3214 NPU_NAMESPACE::security_level get_pending_CSL()
const volatile
3216 NPU_NAMESPACE::security_level
value =
3217 static_cast<NPU_NAMESPACE::security_level
>(((1U << 1) - 1) & (word0 >> 1));
3222 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 1);
3225 volatile reset_r &set_pending_CSL(NPU_NAMESPACE::security_level
value)
volatile
3227 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 1);
3243 uint32_t reserved0 : 24;
3255 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
3256 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
3261 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
3262 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
3264 void operator=(uint64_t
value)
volatile
3266 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
3267 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
3271 return (
static_cast<uint64_t
>(word1) << 32) | word0;
3273 operator uint64_t()
volatile
3275 return (
static_cast<uint64_t
>(word1) << 32) | word0;
3292 uint32_t QREAD : 32;
3307 void operator=(uint32_t
value)
volatile
3315 operator uint32_t()
volatile
3325 uint32_t
value = word0;
3328 uint32_t get_QREAD()
const volatile
3330 uint32_t
value = word0;
3354 uint32_t cmd_region0 : 2;
3355 uint32_t reserved0 : 30;
3370 void operator=(uint32_t
value)
volatile
3378 operator uint32_t()
volatile
3386 CONSTEXPR NPU_NAMESPACE::mem_attr get_cmd_region0()
const
3388 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 0));
3391 NPU_NAMESPACE::mem_attr get_cmd_region0()
const volatile
3393 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 0));
3398 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
3401 volatile qconfig_r &set_cmd_region0(NPU_NAMESPACE::mem_attr
value)
volatile
3403 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
3417 uint32_t QSIZE : 32;
3432 void operator=(uint32_t
value)
volatile
3440 operator uint32_t()
volatile
3450 uint32_t
value = word0;
3453 uint32_t get_QSIZE()
const volatile
3455 uint32_t
value = word0;
3479 uint32_t active_CPL : 1;
3480 uint32_t active_CSL : 1;
3481 uint32_t reserved0 : 30;
3496 void operator=(uint32_t
value)
volatile
3504 operator uint32_t()
volatile
3512 CONSTEXPR NPU_NAMESPACE::privilege_level get_active_CPL()
const
3514 NPU_NAMESPACE::privilege_level
value =
3515 static_cast<NPU_NAMESPACE::privilege_level
>(((1U << 1) - 1) & (word0 >> 0));
3518 NPU_NAMESPACE::privilege_level get_active_CPL()
const volatile
3520 NPU_NAMESPACE::privilege_level
value =
3521 static_cast<NPU_NAMESPACE::privilege_level
>(((1U << 1) - 1) & (word0 >> 0));
3526 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 0);
3529 volatile prot_r &set_active_CPL(NPU_NAMESPACE::privilege_level
value)
volatile
3531 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 0);
3534 CONSTEXPR NPU_NAMESPACE::security_level get_active_CSL()
const
3536 NPU_NAMESPACE::security_level
value =
3537 static_cast<NPU_NAMESPACE::security_level
>(((1U << 1) - 1) & (word0 >> 1));
3540 NPU_NAMESPACE::security_level get_active_CSL()
const volatile
3542 NPU_NAMESPACE::security_level
value =
3543 static_cast<NPU_NAMESPACE::security_level
>(((1U << 1) - 1) & (word0 >> 1));
3548 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 1);
3551 volatile prot_r &set_active_CSL(NPU_NAMESPACE::security_level
value)
volatile
3553 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 1);
3567 uint32_t macs_per_cc : 4;
3568 uint32_t cmd_stream_version : 4;
3569 uint32_t shram_size : 8;
3570 uint32_t reserved0 : 10;
3573 uint32_t product : 4;
3588 void operator=(uint32_t
value)
volatile
3596 operator uint32_t()
volatile
3604 CONSTEXPR uint32_t get_macs_per_cc()
const
3606 uint32_t
value = ((1U << 4) - 1) & (word0 >> 0);
3609 uint32_t get_macs_per_cc()
const volatile
3611 uint32_t
value = ((1U << 4) - 1) & (word0 >> 0);
3616 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) &
value) << 0);
3621 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) &
value) << 0);
3624 CONSTEXPR uint32_t get_cmd_stream_version()
const
3626 uint32_t
value = ((1U << 4) - 1) & (word0 >> 4);
3629 uint32_t get_cmd_stream_version()
const volatile
3631 uint32_t
value = ((1U << 4) - 1) & (word0 >> 4);
3636 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
value) << 4);
3639 volatile config_r &set_cmd_stream_version(uint32_t
value)
volatile
3641 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
value) << 4);
3644 CONSTEXPR uint32_t get_shram_size()
const
3646 uint32_t
value = ((1U << 8) - 1) & (word0 >> 8);
3649 uint32_t get_shram_size()
const volatile
3651 uint32_t
value = ((1U << 8) - 1) & (word0 >> 8);
3656 word0 = (((~((1U << 8) - 1)) << 8) & word0) | ((((1U << 8) - 1) &
value) << 8);
3661 word0 = (((~((1U << 8) - 1)) << 8) & word0) | ((((1U << 8) - 1) &
value) << 8);
3664 CONSTEXPR NPU_NAMESPACE::functional_safety get_functional_safety()
const
3666 NPU_NAMESPACE::functional_safety
value =
3667 static_cast<NPU_NAMESPACE::functional_safety
>(((1U << 1) - 1) & (word0 >> 26));
3670 NPU_NAMESPACE::functional_safety get_functional_safety()
const volatile
3672 NPU_NAMESPACE::functional_safety
value =
3673 static_cast<NPU_NAMESPACE::functional_safety
>(((1U << 1) - 1) & (word0 >> 26));
3678 word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 26);
3681 volatile config_r &set_functional_safety(NPU_NAMESPACE::functional_safety
value)
volatile
3683 word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 26);
3686 CONSTEXPR NPU_NAMESPACE::custom_dma get_custom_dma()
const
3688 NPU_NAMESPACE::custom_dma
value =
static_cast<NPU_NAMESPACE::custom_dma
>(((1U << 1) - 1) & (word0 >> 27));
3691 NPU_NAMESPACE::custom_dma get_custom_dma()
const volatile
3693 NPU_NAMESPACE::custom_dma
value =
static_cast<NPU_NAMESPACE::custom_dma
>(((1U << 1) - 1) & (word0 >> 27));
3698 word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 27);
3701 volatile config_r &set_custom_dma(NPU_NAMESPACE::custom_dma
value)
volatile
3703 word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) &
static_cast<uint32_t
>(
value)) << 27);
3708 uint32_t
value = ((1U << 4) - 1) & (word0 >> 28);
3711 uint32_t get_product()
const volatile
3713 uint32_t
value = ((1U << 4) - 1) & (word0 >> 28);
3718 word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) &
value) << 28);
3723 word0 = (((~((1U << 4) - 1)) << 28) & word0) | ((((1U << 4) - 1) &
value) << 28);
3752 void operator=(uint32_t
value)
volatile
3760 operator uint32_t()
volatile
3770 uint32_t
value = word0;
3773 uint32_t get_LOCK()
const volatile
3775 uint32_t
value = word0;
3783 volatile lock_r &set_LOCK(uint32_t
value)
volatile
3799 uint32_t region0 : 2;
3800 uint32_t region1 : 2;
3801 uint32_t region2 : 2;
3802 uint32_t region3 : 2;
3803 uint32_t region4 : 2;
3804 uint32_t region5 : 2;
3805 uint32_t region6 : 2;
3806 uint32_t region7 : 2;
3807 uint32_t reserved0 : 16;
3822 void operator=(uint32_t
value)
volatile
3830 operator uint32_t()
volatile
3838 CONSTEXPR NPU_NAMESPACE::mem_attr get_region0()
const
3840 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 0));
3843 NPU_NAMESPACE::mem_attr get_region0()
const volatile
3845 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 0));
3850 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
3855 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
3858 CONSTEXPR NPU_NAMESPACE::mem_attr get_region1()
const
3860 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 2));
3863 NPU_NAMESPACE::mem_attr get_region1()
const volatile
3865 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 2));
3870 word0 = (((~((1U << 2) - 1)) << 2) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 2);
3875 word0 = (((~((1U << 2) - 1)) << 2) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 2);
3878 CONSTEXPR NPU_NAMESPACE::mem_attr get_region2()
const
3880 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 4));
3883 NPU_NAMESPACE::mem_attr get_region2()
const volatile
3885 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 4));
3890 word0 = (((~((1U << 2) - 1)) << 4) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 4);
3895 word0 = (((~((1U << 2) - 1)) << 4) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 4);
3898 CONSTEXPR NPU_NAMESPACE::mem_attr get_region3()
const
3900 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 6));
3903 NPU_NAMESPACE::mem_attr get_region3()
const volatile
3905 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 6));
3910 word0 = (((~((1U << 2) - 1)) << 6) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 6);
3915 word0 = (((~((1U << 2) - 1)) << 6) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 6);
3918 CONSTEXPR NPU_NAMESPACE::mem_attr get_region4()
const
3920 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 8));
3923 NPU_NAMESPACE::mem_attr get_region4()
const volatile
3925 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 8));
3930 word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 8);
3935 word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 8);
3938 CONSTEXPR NPU_NAMESPACE::mem_attr get_region5()
const
3940 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 10));
3943 NPU_NAMESPACE::mem_attr get_region5()
const volatile
3945 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 10));
3950 word0 = (((~((1U << 2) - 1)) << 10) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 10);
3955 word0 = (((~((1U << 2) - 1)) << 10) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 10);
3958 CONSTEXPR NPU_NAMESPACE::mem_attr get_region6()
const
3960 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 12));
3963 NPU_NAMESPACE::mem_attr get_region6()
const volatile
3965 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 12));
3970 word0 = (((~((1U << 2) - 1)) << 12) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 12);
3975 word0 = (((~((1U << 2) - 1)) << 12) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 12);
3978 CONSTEXPR NPU_NAMESPACE::mem_attr get_region7()
const
3980 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 14));
3983 NPU_NAMESPACE::mem_attr get_region7()
const volatile
3985 NPU_NAMESPACE::mem_attr
value =
static_cast<NPU_NAMESPACE::mem_attr
>(((1U << 2) - 1) & (word0 >> 14));
3990 word0 = (((~((1U << 2) - 1)) << 14) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 14);
3995 word0 = (((~((1U << 2) - 1)) << 14) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 14);
4010 uint32_t reserved0 : 2;
4011 uint32_t memtype : 4;
4012 uint32_t reserved1 : 8;
4014 max_outstanding_read_m1 : 6;
4015 uint32_t reserved2 : 2;
4016 uint32_t max_outstanding_write_m1 : 5;
4018 uint32_t reserved3 : 3;
4033 void operator=(uint32_t
value)
volatile
4041 operator uint32_t()
volatile
4049 CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats()
const
4051 NPU_NAMESPACE::max_beats
value =
static_cast<NPU_NAMESPACE::max_beats
>(((1U << 2) - 1) & (word0 >> 0));
4054 NPU_NAMESPACE::max_beats get_max_beats()
const volatile
4056 NPU_NAMESPACE::max_beats
value =
static_cast<NPU_NAMESPACE::max_beats
>(((1U << 2) - 1) & (word0 >> 0));
4061 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
4066 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
4069 CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype()
const
4071 NPU_NAMESPACE::axi_mem_encoding
value =
4072 static_cast<NPU_NAMESPACE::axi_mem_encoding
>(((1U << 4) - 1) & (word0 >> 4));
4075 NPU_NAMESPACE::axi_mem_encoding get_memtype()
const volatile
4077 NPU_NAMESPACE::axi_mem_encoding
value =
4078 static_cast<NPU_NAMESPACE::axi_mem_encoding
>(((1U << 4) - 1) & (word0 >> 4));
4083 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
static_cast<uint32_t
>(
value)) << 4);
4086 volatile axi_limit0_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding
value)
volatile
4088 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
static_cast<uint32_t
>(
value)) << 4);
4091 CONSTEXPR uint32_t get_max_outstanding_read_m1()
const
4093 uint32_t
value = ((1U << 6) - 1) & (word0 >> 16);
4096 uint32_t get_max_outstanding_read_m1()
const volatile
4098 uint32_t
value = ((1U << 6) - 1) & (word0 >> 16);
4103 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) &
value) << 16);
4108 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) &
value) << 16);
4111 CONSTEXPR uint32_t get_max_outstanding_write_m1()
const
4113 uint32_t
value = ((1U << 5) - 1) & (word0 >> 24);
4116 uint32_t get_max_outstanding_write_m1()
const volatile
4118 uint32_t
value = ((1U << 5) - 1) & (word0 >> 24);
4123 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) &
value) << 24);
4128 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) &
value) << 24);
4143 uint32_t reserved0 : 2;
4144 uint32_t memtype : 4;
4145 uint32_t reserved1 : 8;
4147 max_outstanding_read_m1 : 6;
4148 uint32_t reserved2 : 2;
4149 uint32_t max_outstanding_write_m1 : 5;
4151 uint32_t reserved3 : 3;
4166 void operator=(uint32_t
value)
volatile
4174 operator uint32_t()
volatile
4182 CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats()
const
4184 NPU_NAMESPACE::max_beats
value =
static_cast<NPU_NAMESPACE::max_beats
>(((1U << 2) - 1) & (word0 >> 0));
4187 NPU_NAMESPACE::max_beats get_max_beats()
const volatile
4189 NPU_NAMESPACE::max_beats
value =
static_cast<NPU_NAMESPACE::max_beats
>(((1U << 2) - 1) & (word0 >> 0));
4194 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
4199 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
4202 CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype()
const
4204 NPU_NAMESPACE::axi_mem_encoding
value =
4205 static_cast<NPU_NAMESPACE::axi_mem_encoding
>(((1U << 4) - 1) & (word0 >> 4));
4208 NPU_NAMESPACE::axi_mem_encoding get_memtype()
const volatile
4210 NPU_NAMESPACE::axi_mem_encoding
value =
4211 static_cast<NPU_NAMESPACE::axi_mem_encoding
>(((1U << 4) - 1) & (word0 >> 4));
4216 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
static_cast<uint32_t
>(
value)) << 4);
4219 volatile axi_limit1_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding
value)
volatile
4221 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
static_cast<uint32_t
>(
value)) << 4);
4224 CONSTEXPR uint32_t get_max_outstanding_read_m1()
const
4226 uint32_t
value = ((1U << 6) - 1) & (word0 >> 16);
4229 uint32_t get_max_outstanding_read_m1()
const volatile
4231 uint32_t
value = ((1U << 6) - 1) & (word0 >> 16);
4236 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) &
value) << 16);
4241 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) &
value) << 16);
4244 CONSTEXPR uint32_t get_max_outstanding_write_m1()
const
4246 uint32_t
value = ((1U << 5) - 1) & (word0 >> 24);
4249 uint32_t get_max_outstanding_write_m1()
const volatile
4251 uint32_t
value = ((1U << 5) - 1) & (word0 >> 24);
4256 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) &
value) << 24);
4261 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) &
value) << 24);
4276 uint32_t reserved0 : 2;
4277 uint32_t memtype : 4;
4278 uint32_t reserved1 : 8;
4280 max_outstanding_read_m1 : 6;
4281 uint32_t reserved2 : 2;
4282 uint32_t max_outstanding_write_m1 : 5;
4284 uint32_t reserved3 : 3;
4299 void operator=(uint32_t
value)
volatile
4307 operator uint32_t()
volatile
4315 CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats()
const
4317 NPU_NAMESPACE::max_beats
value =
static_cast<NPU_NAMESPACE::max_beats
>(((1U << 2) - 1) & (word0 >> 0));
4320 NPU_NAMESPACE::max_beats get_max_beats()
const volatile
4322 NPU_NAMESPACE::max_beats
value =
static_cast<NPU_NAMESPACE::max_beats
>(((1U << 2) - 1) & (word0 >> 0));
4327 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
4332 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
4335 CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype()
const
4337 NPU_NAMESPACE::axi_mem_encoding
value =
4338 static_cast<NPU_NAMESPACE::axi_mem_encoding
>(((1U << 4) - 1) & (word0 >> 4));
4341 NPU_NAMESPACE::axi_mem_encoding get_memtype()
const volatile
4343 NPU_NAMESPACE::axi_mem_encoding
value =
4344 static_cast<NPU_NAMESPACE::axi_mem_encoding
>(((1U << 4) - 1) & (word0 >> 4));
4349 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
static_cast<uint32_t
>(
value)) << 4);
4352 volatile axi_limit2_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding
value)
volatile
4354 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
static_cast<uint32_t
>(
value)) << 4);
4357 CONSTEXPR uint32_t get_max_outstanding_read_m1()
const
4359 uint32_t
value = ((1U << 6) - 1) & (word0 >> 16);
4362 uint32_t get_max_outstanding_read_m1()
const volatile
4364 uint32_t
value = ((1U << 6) - 1) & (word0 >> 16);
4369 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) &
value) << 16);
4374 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) &
value) << 16);
4377 CONSTEXPR uint32_t get_max_outstanding_write_m1()
const
4379 uint32_t
value = ((1U << 5) - 1) & (word0 >> 24);
4382 uint32_t get_max_outstanding_write_m1()
const volatile
4384 uint32_t
value = ((1U << 5) - 1) & (word0 >> 24);
4389 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) &
value) << 24);
4394 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) &
value) << 24);
4409 uint32_t reserved0 : 2;
4410 uint32_t memtype : 4;
4411 uint32_t reserved1 : 8;
4413 max_outstanding_read_m1 : 6;
4414 uint32_t reserved2 : 2;
4415 uint32_t max_outstanding_write_m1 : 5;
4417 uint32_t reserved3 : 3;
4432 void operator=(uint32_t
value)
volatile
4440 operator uint32_t()
volatile
4448 CONSTEXPR NPU_NAMESPACE::max_beats get_max_beats()
const
4450 NPU_NAMESPACE::max_beats
value =
static_cast<NPU_NAMESPACE::max_beats
>(((1U << 2) - 1) & (word0 >> 0));
4453 NPU_NAMESPACE::max_beats get_max_beats()
const volatile
4455 NPU_NAMESPACE::max_beats
value =
static_cast<NPU_NAMESPACE::max_beats
>(((1U << 2) - 1) & (word0 >> 0));
4460 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
4465 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
4468 CONSTEXPR NPU_NAMESPACE::axi_mem_encoding get_memtype()
const
4470 NPU_NAMESPACE::axi_mem_encoding
value =
4471 static_cast<NPU_NAMESPACE::axi_mem_encoding
>(((1U << 4) - 1) & (word0 >> 4));
4474 NPU_NAMESPACE::axi_mem_encoding get_memtype()
const volatile
4476 NPU_NAMESPACE::axi_mem_encoding
value =
4477 static_cast<NPU_NAMESPACE::axi_mem_encoding
>(((1U << 4) - 1) & (word0 >> 4));
4482 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
static_cast<uint32_t
>(
value)) << 4);
4485 volatile axi_limit3_r &set_memtype(NPU_NAMESPACE::axi_mem_encoding
value)
volatile
4487 word0 = (((~((1U << 4) - 1)) << 4) & word0) | ((((1U << 4) - 1) &
static_cast<uint32_t
>(
value)) << 4);
4490 CONSTEXPR uint32_t get_max_outstanding_read_m1()
const
4492 uint32_t
value = ((1U << 6) - 1) & (word0 >> 16);
4495 uint32_t get_max_outstanding_read_m1()
const volatile
4497 uint32_t
value = ((1U << 6) - 1) & (word0 >> 16);
4502 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) &
value) << 16);
4507 word0 = (((~((1U << 6) - 1)) << 16) & word0) | ((((1U << 6) - 1) &
value) << 16);
4510 CONSTEXPR uint32_t get_max_outstanding_write_m1()
const
4512 uint32_t
value = ((1U << 5) - 1) & (word0 >> 24);
4515 uint32_t get_max_outstanding_write_m1()
const volatile
4517 uint32_t
value = ((1U << 5) - 1) & (word0 >> 24);
4522 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) &
value) << 24);
4527 word0 = (((~((1U << 5) - 1)) << 24) & word0) | ((((1U << 5) - 1) &
value) << 24);
4544 uint32_t reserved0 : 24;
4556 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
4557 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
4562 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
4563 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
4565 void operator=(uint64_t
value)
volatile
4567 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
4568 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
4572 return (
static_cast<uint64_t
>(word1) << 32) | word0;
4574 operator uint64_t()
volatile
4576 return (
static_cast<uint64_t
>(word1) << 32) | word0;
4593 uint32_t core_slice_state : 2;
4594 uint32_t core_idle : 1;
4595 uint32_t ctrl_state : 2;
4596 uint32_t ctrl_idle : 1;
4597 uint32_t write_buf_index0 : 3;
4598 uint32_t write_buf_valid0 : 1;
4599 uint32_t write_buf_idle0 : 1;
4600 uint32_t write_buf_index1 : 3;
4601 uint32_t write_buf_valid1 : 1;
4602 uint32_t write_buf_idle1 : 1;
4603 uint32_t events : 12;
4604 uint32_t reserved0 : 4;
4619 void operator=(uint32_t
value)
volatile
4627 operator uint32_t()
volatile
4635 CONSTEXPR NPU_NAMESPACE::wd_core_slice_state get_core_slice_state()
const
4637 NPU_NAMESPACE::wd_core_slice_state
value =
4638 static_cast<NPU_NAMESPACE::wd_core_slice_state
>(((1U << 2) - 1) & (word0 >> 0));
4641 NPU_NAMESPACE::wd_core_slice_state get_core_slice_state()
const volatile
4643 NPU_NAMESPACE::wd_core_slice_state
value =
4644 static_cast<NPU_NAMESPACE::wd_core_slice_state
>(((1U << 2) - 1) & (word0 >> 0));
4649 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
4652 volatile wd_status_r &set_core_slice_state(NPU_NAMESPACE::wd_core_slice_state
value)
volatile
4654 word0 = (((~((1U << 2) - 1)) << 0) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 0);
4657 CONSTEXPR uint32_t get_core_idle()
const
4659 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
4662 uint32_t get_core_idle()
const volatile
4664 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
4669 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
4674 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
4677 CONSTEXPR NPU_NAMESPACE::wd_ctrl_state get_ctrl_state()
const
4679 NPU_NAMESPACE::wd_ctrl_state
value =
static_cast<NPU_NAMESPACE::wd_ctrl_state
>(((1U << 2) - 1) & (word0 >> 3));
4682 NPU_NAMESPACE::wd_ctrl_state get_ctrl_state()
const volatile
4684 NPU_NAMESPACE::wd_ctrl_state
value =
static_cast<NPU_NAMESPACE::wd_ctrl_state
>(((1U << 2) - 1) & (word0 >> 3));
4689 word0 = (((~((1U << 2) - 1)) << 3) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 3);
4692 volatile wd_status_r &set_ctrl_state(NPU_NAMESPACE::wd_ctrl_state
value)
volatile
4694 word0 = (((~((1U << 2) - 1)) << 3) & word0) | ((((1U << 2) - 1) &
static_cast<uint32_t
>(
value)) << 3);
4697 CONSTEXPR uint32_t get_ctrl_idle()
const
4699 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
4702 uint32_t get_ctrl_idle()
const volatile
4704 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
4709 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
4714 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
4717 CONSTEXPR uint32_t get_write_buf_index0()
const
4719 uint32_t
value = ((1U << 3) - 1) & (word0 >> 6);
4722 uint32_t get_write_buf_index0()
const volatile
4724 uint32_t
value = ((1U << 3) - 1) & (word0 >> 6);
4729 word0 = (((~((1U << 3) - 1)) << 6) & word0) | ((((1U << 3) - 1) &
value) << 6);
4734 word0 = (((~((1U << 3) - 1)) << 6) & word0) | ((((1U << 3) - 1) &
value) << 6);
4737 CONSTEXPR uint32_t get_write_buf_valid0()
const
4739 uint32_t
value = ((1U << 1) - 1) & (word0 >> 9);
4742 uint32_t get_write_buf_valid0()
const volatile
4744 uint32_t
value = ((1U << 1) - 1) & (word0 >> 9);
4749 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) &
value) << 9);
4754 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) &
value) << 9);
4757 CONSTEXPR uint32_t get_write_buf_idle0()
const
4759 uint32_t
value = ((1U << 1) - 1) & (word0 >> 10);
4762 uint32_t get_write_buf_idle0()
const volatile
4764 uint32_t
value = ((1U << 1) - 1) & (word0 >> 10);
4769 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) &
value) << 10);
4774 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) &
value) << 10);
4777 CONSTEXPR uint32_t get_write_buf_index1()
const
4779 uint32_t
value = ((1U << 3) - 1) & (word0 >> 11);
4782 uint32_t get_write_buf_index1()
const volatile
4784 uint32_t
value = ((1U << 3) - 1) & (word0 >> 11);
4789 word0 = (((~((1U << 3) - 1)) << 11) & word0) | ((((1U << 3) - 1) &
value) << 11);
4794 word0 = (((~((1U << 3) - 1)) << 11) & word0) | ((((1U << 3) - 1) &
value) << 11);
4797 CONSTEXPR uint32_t get_write_buf_valid1()
const
4799 uint32_t
value = ((1U << 1) - 1) & (word0 >> 14);
4802 uint32_t get_write_buf_valid1()
const volatile
4804 uint32_t
value = ((1U << 1) - 1) & (word0 >> 14);
4809 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) &
value) << 14);
4814 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) &
value) << 14);
4817 CONSTEXPR uint32_t get_write_buf_idle1()
const
4819 uint32_t
value = ((1U << 1) - 1) & (word0 >> 15);
4822 uint32_t get_write_buf_idle1()
const volatile
4824 uint32_t
value = ((1U << 1) - 1) & (word0 >> 15);
4829 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) &
value) << 15);
4834 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) &
value) << 15);
4839 uint32_t
value = ((1U << 12) - 1) & (word0 >> 16);
4842 uint32_t get_events()
const volatile
4844 uint32_t
value = ((1U << 12) - 1) & (word0 >> 16);
4849 word0 = (((~((1U << 12) - 1)) << 16) & word0) | ((((1U << 12) - 1) &
value) << 16);
4854 word0 = (((~((1U << 12) - 1)) << 16) & word0) | ((((1U << 12) - 1) &
value) << 16);
4868 uint32_t block_cfg_valid : 1;
4869 uint32_t trav_en : 1;
4870 uint32_t wait_for_ib : 1;
4871 uint32_t wait_for_acc_buf : 1;
4872 uint32_t wait_for_weights : 1;
4873 uint32_t stall_stripe : 1;
4874 uint32_t dw_sel : 1;
4875 uint32_t wait_for_dw0_ready : 1;
4876 uint32_t wait_for_dw1_ready : 1;
4877 uint32_t acc_buf_sel_ai : 1;
4878 uint32_t wait_for_acc0_ready : 1;
4879 uint32_t wait_for_acc1_ready : 1;
4880 uint32_t acc_buf_sel_aa : 1;
4881 uint32_t acc0_valid : 1;
4882 uint32_t acc1_valid : 1;
4883 uint32_t reserved0 : 1;
4884 uint32_t events : 11;
4885 uint32_t reserved1 : 5;
4900 void operator=(uint32_t
value)
volatile
4908 operator uint32_t()
volatile
4916 CONSTEXPR uint32_t get_block_cfg_valid()
const
4918 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
4921 uint32_t get_block_cfg_valid()
const volatile
4923 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
4928 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
4933 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
4938 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
4941 uint32_t get_trav_en()
const volatile
4943 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
4948 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
4953 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
4956 CONSTEXPR uint32_t get_wait_for_ib()
const
4958 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
4961 uint32_t get_wait_for_ib()
const volatile
4963 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
4968 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
4973 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
4976 CONSTEXPR uint32_t get_wait_for_acc_buf()
const
4978 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
4981 uint32_t get_wait_for_acc_buf()
const volatile
4983 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
4988 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
4993 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
4996 CONSTEXPR uint32_t get_wait_for_weights()
const
4998 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
5001 uint32_t get_wait_for_weights()
const volatile
5003 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
5008 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
5013 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
5016 CONSTEXPR uint32_t get_stall_stripe()
const
5018 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
5021 uint32_t get_stall_stripe()
const volatile
5023 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
5028 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
5033 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
5038 uint32_t
value = ((1U << 1) - 1) & (word0 >> 6);
5041 uint32_t get_dw_sel()
const volatile
5043 uint32_t
value = ((1U << 1) - 1) & (word0 >> 6);
5048 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) &
value) << 6);
5053 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) &
value) << 6);
5056 CONSTEXPR uint32_t get_wait_for_dw0_ready()
const
5058 uint32_t
value = ((1U << 1) - 1) & (word0 >> 7);
5061 uint32_t get_wait_for_dw0_ready()
const volatile
5063 uint32_t
value = ((1U << 1) - 1) & (word0 >> 7);
5068 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) &
value) << 7);
5073 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) &
value) << 7);
5076 CONSTEXPR uint32_t get_wait_for_dw1_ready()
const
5078 uint32_t
value = ((1U << 1) - 1) & (word0 >> 8);
5081 uint32_t get_wait_for_dw1_ready()
const volatile
5083 uint32_t
value = ((1U << 1) - 1) & (word0 >> 8);
5088 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) &
value) << 8);
5093 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) &
value) << 8);
5096 CONSTEXPR uint32_t get_acc_buf_sel_ai()
const
5098 uint32_t
value = ((1U << 1) - 1) & (word0 >> 9);
5101 uint32_t get_acc_buf_sel_ai()
const volatile
5103 uint32_t
value = ((1U << 1) - 1) & (word0 >> 9);
5108 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) &
value) << 9);
5113 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) &
value) << 9);
5116 CONSTEXPR uint32_t get_wait_for_acc0_ready()
const
5118 uint32_t
value = ((1U << 1) - 1) & (word0 >> 10);
5121 uint32_t get_wait_for_acc0_ready()
const volatile
5123 uint32_t
value = ((1U << 1) - 1) & (word0 >> 10);
5128 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) &
value) << 10);
5133 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) &
value) << 10);
5136 CONSTEXPR uint32_t get_wait_for_acc1_ready()
const
5138 uint32_t
value = ((1U << 1) - 1) & (word0 >> 11);
5141 uint32_t get_wait_for_acc1_ready()
const volatile
5143 uint32_t
value = ((1U << 1) - 1) & (word0 >> 11);
5148 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) &
value) << 11);
5153 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) &
value) << 11);
5156 CONSTEXPR uint32_t get_acc_buf_sel_aa()
const
5158 uint32_t
value = ((1U << 1) - 1) & (word0 >> 12);
5161 uint32_t get_acc_buf_sel_aa()
const volatile
5163 uint32_t
value = ((1U << 1) - 1) & (word0 >> 12);
5168 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) &
value) << 12);
5173 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) &
value) << 12);
5176 CONSTEXPR uint32_t get_acc0_valid()
const
5178 uint32_t
value = ((1U << 1) - 1) & (word0 >> 13);
5181 uint32_t get_acc0_valid()
const volatile
5183 uint32_t
value = ((1U << 1) - 1) & (word0 >> 13);
5188 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) &
value) << 13);
5193 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) &
value) << 13);
5196 CONSTEXPR uint32_t get_acc1_valid()
const
5198 uint32_t
value = ((1U << 1) - 1) & (word0 >> 14);
5201 uint32_t get_acc1_valid()
const volatile
5203 uint32_t
value = ((1U << 1) - 1) & (word0 >> 14);
5208 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) &
value) << 14);
5213 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) &
value) << 14);
5218 uint32_t
value = ((1U << 11) - 1) & (word0 >> 16);
5221 uint32_t get_events()
const volatile
5223 uint32_t
value = ((1U << 11) - 1) & (word0 >> 16);
5228 word0 = (((~((1U << 11) - 1)) << 16) & word0) | ((((1U << 11) - 1) &
value) << 16);
5233 word0 = (((~((1U << 11) - 1)) << 16) & word0) | ((((1U << 11) - 1) &
value) << 16);
5247 uint32_t cmd_sbw_valid : 1;
5248 uint32_t cmd_act_valid : 1;
5249 uint32_t cmd_ctl_valid : 1;
5250 uint32_t cmd_scl_valid : 1;
5251 uint32_t cmd_sbr_valid : 1;
5252 uint32_t cmd_ofm_valid : 1;
5253 uint32_t blk_cmd_ready : 1;
5254 uint32_t blk_cmd_valid : 1;
5255 uint32_t reserved0 : 8;
5256 uint32_t events : 8;
5257 uint32_t reserved1 : 8;
5272 void operator=(uint32_t
value)
volatile
5280 operator uint32_t()
volatile
5288 CONSTEXPR uint32_t get_cmd_sbw_valid()
const
5290 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
5293 uint32_t get_cmd_sbw_valid()
const volatile
5295 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
5300 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
5305 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
5308 CONSTEXPR uint32_t get_cmd_act_valid()
const
5310 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
5313 uint32_t get_cmd_act_valid()
const volatile
5315 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
5320 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
5325 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
5328 CONSTEXPR uint32_t get_cmd_ctl_valid()
const
5330 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
5333 uint32_t get_cmd_ctl_valid()
const volatile
5335 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
5340 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
5345 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
5348 CONSTEXPR uint32_t get_cmd_scl_valid()
const
5350 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
5353 uint32_t get_cmd_scl_valid()
const volatile
5355 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
5360 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
5365 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
5368 CONSTEXPR uint32_t get_cmd_sbr_valid()
const
5370 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
5373 uint32_t get_cmd_sbr_valid()
const volatile
5375 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
5380 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
5385 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
5388 CONSTEXPR uint32_t get_cmd_ofm_valid()
const
5390 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
5393 uint32_t get_cmd_ofm_valid()
const volatile
5395 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
5400 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
5405 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
5408 CONSTEXPR uint32_t get_blk_cmd_ready()
const
5410 uint32_t
value = ((1U << 1) - 1) & (word0 >> 6);
5413 uint32_t get_blk_cmd_ready()
const volatile
5415 uint32_t
value = ((1U << 1) - 1) & (word0 >> 6);
5420 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) &
value) << 6);
5425 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) &
value) << 6);
5428 CONSTEXPR uint32_t get_blk_cmd_valid()
const
5430 uint32_t
value = ((1U << 1) - 1) & (word0 >> 7);
5433 uint32_t get_blk_cmd_valid()
const volatile
5435 uint32_t
value = ((1U << 1) - 1) & (word0 >> 7);
5440 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) &
value) << 7);
5445 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) &
value) << 7);
5450 uint32_t
value = ((1U << 8) - 1) & (word0 >> 16);
5453 uint32_t get_events()
const volatile
5455 uint32_t
value = ((1U << 8) - 1) & (word0 >> 16);
5460 word0 = (((~((1U << 8) - 1)) << 16) & word0) | ((((1U << 8) - 1) &
value) << 16);
5465 word0 = (((~((1U << 8) - 1)) << 16) & word0) | ((((1U << 8) - 1) &
value) << 16);
5479 uint32_t cmd_idle : 1;
5481 uint32_t ifm_idle : 1;
5482 uint32_t wgt_idle_c0 : 1;
5484 uint32_t bas_idle_c0 : 1;
5486 uint32_t m2m_idle : 1;
5487 uint32_t ofm_idle : 1;
5488 uint32_t halt_req : 1;
5489 uint32_t halt_ack : 1;
5490 uint32_t pause_req : 1;
5491 uint32_t pause_ack : 1;
5492 uint32_t ib0_ai_valid_c0 : 1;
5493 uint32_t ib0_ai_ready_c0 : 1;
5494 uint32_t ib1_ai_valid_c0 : 1;
5495 uint32_t ib1_ai_ready_c0 : 1;
5496 uint32_t ib0_ao_valid_c0 : 1;
5497 uint32_t ib0_ao_ready_c0 : 1;
5498 uint32_t ib1_ao_valid_c0 : 1;
5499 uint32_t ib1_ao_ready_c0 : 1;
5500 uint32_t ob0_valid_c0 : 1;
5501 uint32_t ob0_ready_c0 : 1;
5502 uint32_t ob1_valid_c0 : 1;
5503 uint32_t ob1_ready_c0 : 1;
5504 uint32_t cmd_valid : 1;
5505 uint32_t cmd_ready : 1;
5506 uint32_t wd_bitstream_valid_c0 : 1;
5507 uint32_t wd_bitstream_ready_c0 : 1;
5508 uint32_t bs_bitstream_valid_c0 : 1;
5509 uint32_t bs_bitstream_ready_c0 : 1;
5510 uint32_t axi0_ar_stalled : 1;
5511 uint32_t axi0_rd_limit_stall : 1;
5512 uint32_t axi0_aw_stalled : 1;
5513 uint32_t axi0_w_stalled : 1;
5528 void operator=(uint32_t
value)
volatile
5536 operator uint32_t()
volatile
5546 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
5549 uint32_t get_cmd_idle()
const volatile
5551 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
5556 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
5561 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
5566 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
5569 uint32_t get_ifm_idle()
const volatile
5571 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
5576 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
5581 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
5584 CONSTEXPR uint32_t get_wgt_idle_c0()
const
5586 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
5589 uint32_t get_wgt_idle_c0()
const volatile
5591 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
5596 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
5601 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
5604 CONSTEXPR uint32_t get_bas_idle_c0()
const
5606 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
5609 uint32_t get_bas_idle_c0()
const volatile
5611 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
5616 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
5621 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
5626 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
5629 uint32_t get_m2m_idle()
const volatile
5631 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
5636 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
5641 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
5646 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
5649 uint32_t get_ofm_idle()
const volatile
5651 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
5656 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
5661 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
5666 uint32_t
value = ((1U << 1) - 1) & (word0 >> 6);
5669 uint32_t get_halt_req()
const volatile
5671 uint32_t
value = ((1U << 1) - 1) & (word0 >> 6);
5676 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) &
value) << 6);
5681 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) &
value) << 6);
5686 uint32_t
value = ((1U << 1) - 1) & (word0 >> 7);
5689 uint32_t get_halt_ack()
const volatile
5691 uint32_t
value = ((1U << 1) - 1) & (word0 >> 7);
5696 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) &
value) << 7);
5701 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) &
value) << 7);
5704 CONSTEXPR uint32_t get_pause_req()
const
5706 uint32_t
value = ((1U << 1) - 1) & (word0 >> 8);
5709 uint32_t get_pause_req()
const volatile
5711 uint32_t
value = ((1U << 1) - 1) & (word0 >> 8);
5716 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) &
value) << 8);
5721 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) &
value) << 8);
5724 CONSTEXPR uint32_t get_pause_ack()
const
5726 uint32_t
value = ((1U << 1) - 1) & (word0 >> 9);
5729 uint32_t get_pause_ack()
const volatile
5731 uint32_t
value = ((1U << 1) - 1) & (word0 >> 9);
5736 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) &
value) << 9);
5741 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) &
value) << 9);
5744 CONSTEXPR uint32_t get_ib0_ai_valid_c0()
const
5746 uint32_t
value = ((1U << 1) - 1) & (word0 >> 10);
5749 uint32_t get_ib0_ai_valid_c0()
const volatile
5751 uint32_t
value = ((1U << 1) - 1) & (word0 >> 10);
5756 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) &
value) << 10);
5761 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) &
value) << 10);
5764 CONSTEXPR uint32_t get_ib0_ai_ready_c0()
const
5766 uint32_t
value = ((1U << 1) - 1) & (word0 >> 11);
5769 uint32_t get_ib0_ai_ready_c0()
const volatile
5771 uint32_t
value = ((1U << 1) - 1) & (word0 >> 11);
5776 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) &
value) << 11);
5781 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) &
value) << 11);
5784 CONSTEXPR uint32_t get_ib1_ai_valid_c0()
const
5786 uint32_t
value = ((1U << 1) - 1) & (word0 >> 12);
5789 uint32_t get_ib1_ai_valid_c0()
const volatile
5791 uint32_t
value = ((1U << 1) - 1) & (word0 >> 12);
5796 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) &
value) << 12);
5801 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) &
value) << 12);
5804 CONSTEXPR uint32_t get_ib1_ai_ready_c0()
const
5806 uint32_t
value = ((1U << 1) - 1) & (word0 >> 13);
5809 uint32_t get_ib1_ai_ready_c0()
const volatile
5811 uint32_t
value = ((1U << 1) - 1) & (word0 >> 13);
5816 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) &
value) << 13);
5821 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) &
value) << 13);
5824 CONSTEXPR uint32_t get_ib0_ao_valid_c0()
const
5826 uint32_t
value = ((1U << 1) - 1) & (word0 >> 14);
5829 uint32_t get_ib0_ao_valid_c0()
const volatile
5831 uint32_t
value = ((1U << 1) - 1) & (word0 >> 14);
5836 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) &
value) << 14);
5841 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) &
value) << 14);
5844 CONSTEXPR uint32_t get_ib0_ao_ready_c0()
const
5846 uint32_t
value = ((1U << 1) - 1) & (word0 >> 15);
5849 uint32_t get_ib0_ao_ready_c0()
const volatile
5851 uint32_t
value = ((1U << 1) - 1) & (word0 >> 15);
5856 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) &
value) << 15);
5861 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) &
value) << 15);
5864 CONSTEXPR uint32_t get_ib1_ao_valid_c0()
const
5866 uint32_t
value = ((1U << 1) - 1) & (word0 >> 16);
5869 uint32_t get_ib1_ao_valid_c0()
const volatile
5871 uint32_t
value = ((1U << 1) - 1) & (word0 >> 16);
5876 word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) &
value) << 16);
5881 word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) &
value) << 16);
5884 CONSTEXPR uint32_t get_ib1_ao_ready_c0()
const
5886 uint32_t
value = ((1U << 1) - 1) & (word0 >> 17);
5889 uint32_t get_ib1_ao_ready_c0()
const volatile
5891 uint32_t
value = ((1U << 1) - 1) & (word0 >> 17);
5896 word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) &
value) << 17);
5901 word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) &
value) << 17);
5904 CONSTEXPR uint32_t get_ob0_valid_c0()
const
5906 uint32_t
value = ((1U << 1) - 1) & (word0 >> 18);
5909 uint32_t get_ob0_valid_c0()
const volatile
5911 uint32_t
value = ((1U << 1) - 1) & (word0 >> 18);
5916 word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) &
value) << 18);
5921 word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) &
value) << 18);
5924 CONSTEXPR uint32_t get_ob0_ready_c0()
const
5926 uint32_t
value = ((1U << 1) - 1) & (word0 >> 19);
5929 uint32_t get_ob0_ready_c0()
const volatile
5931 uint32_t
value = ((1U << 1) - 1) & (word0 >> 19);
5936 word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) &
value) << 19);
5941 word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) &
value) << 19);
5944 CONSTEXPR uint32_t get_ob1_valid_c0()
const
5946 uint32_t
value = ((1U << 1) - 1) & (word0 >> 20);
5949 uint32_t get_ob1_valid_c0()
const volatile
5951 uint32_t
value = ((1U << 1) - 1) & (word0 >> 20);
5956 word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) &
value) << 20);
5961 word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) &
value) << 20);
5964 CONSTEXPR uint32_t get_ob1_ready_c0()
const
5966 uint32_t
value = ((1U << 1) - 1) & (word0 >> 21);
5969 uint32_t get_ob1_ready_c0()
const volatile
5971 uint32_t
value = ((1U << 1) - 1) & (word0 >> 21);
5976 word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) &
value) << 21);
5981 word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) &
value) << 21);
5984 CONSTEXPR uint32_t get_cmd_valid()
const
5986 uint32_t
value = ((1U << 1) - 1) & (word0 >> 22);
5989 uint32_t get_cmd_valid()
const volatile
5991 uint32_t
value = ((1U << 1) - 1) & (word0 >> 22);
5996 word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) &
value) << 22);
6001 word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) &
value) << 22);
6004 CONSTEXPR uint32_t get_cmd_ready()
const
6006 uint32_t
value = ((1U << 1) - 1) & (word0 >> 23);
6009 uint32_t get_cmd_ready()
const volatile
6011 uint32_t
value = ((1U << 1) - 1) & (word0 >> 23);
6016 word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) &
value) << 23);
6021 word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) &
value) << 23);
6024 CONSTEXPR uint32_t get_wd_bitstream_valid_c0()
const
6026 uint32_t
value = ((1U << 1) - 1) & (word0 >> 24);
6029 uint32_t get_wd_bitstream_valid_c0()
const volatile
6031 uint32_t
value = ((1U << 1) - 1) & (word0 >> 24);
6036 word0 = (((~((1U << 1) - 1)) << 24) & word0) | ((((1U << 1) - 1) &
value) << 24);
6041 word0 = (((~((1U << 1) - 1)) << 24) & word0) | ((((1U << 1) - 1) &
value) << 24);
6044 CONSTEXPR uint32_t get_wd_bitstream_ready_c0()
const
6046 uint32_t
value = ((1U << 1) - 1) & (word0 >> 25);
6049 uint32_t get_wd_bitstream_ready_c0()
const volatile
6051 uint32_t
value = ((1U << 1) - 1) & (word0 >> 25);
6056 word0 = (((~((1U << 1) - 1)) << 25) & word0) | ((((1U << 1) - 1) &
value) << 25);
6061 word0 = (((~((1U << 1) - 1)) << 25) & word0) | ((((1U << 1) - 1) &
value) << 25);
6064 CONSTEXPR uint32_t get_bs_bitstream_valid_c0()
const
6066 uint32_t
value = ((1U << 1) - 1) & (word0 >> 26);
6069 uint32_t get_bs_bitstream_valid_c0()
const volatile
6071 uint32_t
value = ((1U << 1) - 1) & (word0 >> 26);
6076 word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) &
value) << 26);
6081 word0 = (((~((1U << 1) - 1)) << 26) & word0) | ((((1U << 1) - 1) &
value) << 26);
6084 CONSTEXPR uint32_t get_bs_bitstream_ready_c0()
const
6086 uint32_t
value = ((1U << 1) - 1) & (word0 >> 27);
6089 uint32_t get_bs_bitstream_ready_c0()
const volatile
6091 uint32_t
value = ((1U << 1) - 1) & (word0 >> 27);
6096 word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) &
value) << 27);
6101 word0 = (((~((1U << 1) - 1)) << 27) & word0) | ((((1U << 1) - 1) &
value) << 27);
6104 CONSTEXPR uint32_t get_axi0_ar_stalled()
const
6106 uint32_t
value = ((1U << 1) - 1) & (word0 >> 28);
6109 uint32_t get_axi0_ar_stalled()
const volatile
6111 uint32_t
value = ((1U << 1) - 1) & (word0 >> 28);
6116 word0 = (((~((1U << 1) - 1)) << 28) & word0) | ((((1U << 1) - 1) &
value) << 28);
6121 word0 = (((~((1U << 1) - 1)) << 28) & word0) | ((((1U << 1) - 1) &
value) << 28);
6124 CONSTEXPR uint32_t get_axi0_rd_limit_stall()
const
6126 uint32_t
value = ((1U << 1) - 1) & (word0 >> 29);
6129 uint32_t get_axi0_rd_limit_stall()
const volatile
6131 uint32_t
value = ((1U << 1) - 1) & (word0 >> 29);
6136 word0 = (((~((1U << 1) - 1)) << 29) & word0) | ((((1U << 1) - 1) &
value) << 29);
6141 word0 = (((~((1U << 1) - 1)) << 29) & word0) | ((((1U << 1) - 1) &
value) << 29);
6144 CONSTEXPR uint32_t get_axi0_aw_stalled()
const
6146 uint32_t
value = ((1U << 1) - 1) & (word0 >> 30);
6149 uint32_t get_axi0_aw_stalled()
const volatile
6151 uint32_t
value = ((1U << 1) - 1) & (word0 >> 30);
6156 word0 = (((~((1U << 1) - 1)) << 30) & word0) | ((((1U << 1) - 1) &
value) << 30);
6161 word0 = (((~((1U << 1) - 1)) << 30) & word0) | ((((1U << 1) - 1) &
value) << 30);
6164 CONSTEXPR uint32_t get_axi0_w_stalled()
const
6166 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
6169 uint32_t get_axi0_w_stalled()
const volatile
6171 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
6176 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
6181 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
6195 uint32_t axi0_wr_limit_stall : 1;
6196 uint32_t axi1_ar_stalled : 1;
6197 uint32_t axi1_rd_limit_stall : 1;
6198 uint32_t axi1_wr_stalled : 1;
6199 uint32_t axi1_w_stalled : 1;
6200 uint32_t axi1_wr_limit_stall : 1;
6201 uint32_t wgt_idle_c1 : 1;
6203 uint32_t bas_idle_c1 : 1;
6205 uint32_t ib0_ai_valid_c1 : 1;
6206 uint32_t ib0_ai_ready_c1 : 1;
6207 uint32_t ib1_ai_valid_c1 : 1;
6208 uint32_t ib1_ai_ready_c1 : 1;
6209 uint32_t ib0_ao_valid_c1 : 1;
6210 uint32_t ib0_ao_ready_c1 : 1;
6211 uint32_t ib1_ao_valid_c1 : 1;
6212 uint32_t ib1_ao_ready_c1 : 1;
6213 uint32_t ob0_valid_c1 : 1;
6214 uint32_t ob0_ready_c1 : 1;
6215 uint32_t ob1_valid_c1 : 1;
6216 uint32_t ob1_ready_c1 : 1;
6217 uint32_t wd_bitstream_valid_c1 : 1;
6218 uint32_t wd_bitstream_ready_c1 : 1;
6219 uint32_t bs_bitstream_valid_c1 : 1;
6220 uint32_t bs_bitstream_ready_c1 : 1;
6221 uint32_t reserved0 : 8;
6236 void operator=(uint32_t
value)
volatile
6244 operator uint32_t()
volatile
6252 CONSTEXPR uint32_t get_axi0_wr_limit_stall()
const
6254 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
6257 uint32_t get_axi0_wr_limit_stall()
const volatile
6259 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
6264 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
6269 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
6272 CONSTEXPR uint32_t get_axi1_ar_stalled()
const
6274 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
6277 uint32_t get_axi1_ar_stalled()
const volatile
6279 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
6284 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
6289 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
6292 CONSTEXPR uint32_t get_axi1_rd_limit_stall()
const
6294 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
6297 uint32_t get_axi1_rd_limit_stall()
const volatile
6299 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
6304 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
6309 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
6312 CONSTEXPR uint32_t get_axi1_wr_stalled()
const
6314 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
6317 uint32_t get_axi1_wr_stalled()
const volatile
6319 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
6324 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
6329 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
6332 CONSTEXPR uint32_t get_axi1_w_stalled()
const
6334 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
6337 uint32_t get_axi1_w_stalled()
const volatile
6339 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
6344 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
6349 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
6352 CONSTEXPR uint32_t get_axi1_wr_limit_stall()
const
6354 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
6357 uint32_t get_axi1_wr_limit_stall()
const volatile
6359 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
6364 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
6369 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
6372 CONSTEXPR uint32_t get_wgt_idle_c1()
const
6374 uint32_t
value = ((1U << 1) - 1) & (word0 >> 6);
6377 uint32_t get_wgt_idle_c1()
const volatile
6379 uint32_t
value = ((1U << 1) - 1) & (word0 >> 6);
6384 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) &
value) << 6);
6389 word0 = (((~((1U << 1) - 1)) << 6) & word0) | ((((1U << 1) - 1) &
value) << 6);
6392 CONSTEXPR uint32_t get_bas_idle_c1()
const
6394 uint32_t
value = ((1U << 1) - 1) & (word0 >> 7);
6397 uint32_t get_bas_idle_c1()
const volatile
6399 uint32_t
value = ((1U << 1) - 1) & (word0 >> 7);
6404 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) &
value) << 7);
6409 word0 = (((~((1U << 1) - 1)) << 7) & word0) | ((((1U << 1) - 1) &
value) << 7);
6412 CONSTEXPR uint32_t get_ib0_ai_valid_c1()
const
6414 uint32_t
value = ((1U << 1) - 1) & (word0 >> 8);
6417 uint32_t get_ib0_ai_valid_c1()
const volatile
6419 uint32_t
value = ((1U << 1) - 1) & (word0 >> 8);
6424 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) &
value) << 8);
6429 word0 = (((~((1U << 1) - 1)) << 8) & word0) | ((((1U << 1) - 1) &
value) << 8);
6432 CONSTEXPR uint32_t get_ib0_ai_ready_c1()
const
6434 uint32_t
value = ((1U << 1) - 1) & (word0 >> 9);
6437 uint32_t get_ib0_ai_ready_c1()
const volatile
6439 uint32_t
value = ((1U << 1) - 1) & (word0 >> 9);
6444 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) &
value) << 9);
6449 word0 = (((~((1U << 1) - 1)) << 9) & word0) | ((((1U << 1) - 1) &
value) << 9);
6452 CONSTEXPR uint32_t get_ib1_ai_valid_c1()
const
6454 uint32_t
value = ((1U << 1) - 1) & (word0 >> 10);
6457 uint32_t get_ib1_ai_valid_c1()
const volatile
6459 uint32_t
value = ((1U << 1) - 1) & (word0 >> 10);
6464 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) &
value) << 10);
6469 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) &
value) << 10);
6472 CONSTEXPR uint32_t get_ib1_ai_ready_c1()
const
6474 uint32_t
value = ((1U << 1) - 1) & (word0 >> 11);
6477 uint32_t get_ib1_ai_ready_c1()
const volatile
6479 uint32_t
value = ((1U << 1) - 1) & (word0 >> 11);
6484 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) &
value) << 11);
6489 word0 = (((~((1U << 1) - 1)) << 11) & word0) | ((((1U << 1) - 1) &
value) << 11);
6492 CONSTEXPR uint32_t get_ib0_ao_valid_c1()
const
6494 uint32_t
value = ((1U << 1) - 1) & (word0 >> 12);
6497 uint32_t get_ib0_ao_valid_c1()
const volatile
6499 uint32_t
value = ((1U << 1) - 1) & (word0 >> 12);
6504 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) &
value) << 12);
6509 word0 = (((~((1U << 1) - 1)) << 12) & word0) | ((((1U << 1) - 1) &
value) << 12);
6512 CONSTEXPR uint32_t get_ib0_ao_ready_c1()
const
6514 uint32_t
value = ((1U << 1) - 1) & (word0 >> 13);
6517 uint32_t get_ib0_ao_ready_c1()
const volatile
6519 uint32_t
value = ((1U << 1) - 1) & (word0 >> 13);
6524 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) &
value) << 13);
6529 word0 = (((~((1U << 1) - 1)) << 13) & word0) | ((((1U << 1) - 1) &
value) << 13);
6532 CONSTEXPR uint32_t get_ib1_ao_valid_c1()
const
6534 uint32_t
value = ((1U << 1) - 1) & (word0 >> 14);
6537 uint32_t get_ib1_ao_valid_c1()
const volatile
6539 uint32_t
value = ((1U << 1) - 1) & (word0 >> 14);
6544 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) &
value) << 14);
6549 word0 = (((~((1U << 1) - 1)) << 14) & word0) | ((((1U << 1) - 1) &
value) << 14);
6552 CONSTEXPR uint32_t get_ib1_ao_ready_c1()
const
6554 uint32_t
value = ((1U << 1) - 1) & (word0 >> 15);
6557 uint32_t get_ib1_ao_ready_c1()
const volatile
6559 uint32_t
value = ((1U << 1) - 1) & (word0 >> 15);
6564 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) &
value) << 15);
6569 word0 = (((~((1U << 1) - 1)) << 15) & word0) | ((((1U << 1) - 1) &
value) << 15);
6572 CONSTEXPR uint32_t get_ob0_valid_c1()
const
6574 uint32_t
value = ((1U << 1) - 1) & (word0 >> 16);
6577 uint32_t get_ob0_valid_c1()
const volatile
6579 uint32_t
value = ((1U << 1) - 1) & (word0 >> 16);
6584 word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) &
value) << 16);
6589 word0 = (((~((1U << 1) - 1)) << 16) & word0) | ((((1U << 1) - 1) &
value) << 16);
6592 CONSTEXPR uint32_t get_ob0_ready_c1()
const
6594 uint32_t
value = ((1U << 1) - 1) & (word0 >> 17);
6597 uint32_t get_ob0_ready_c1()
const volatile
6599 uint32_t
value = ((1U << 1) - 1) & (word0 >> 17);
6604 word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) &
value) << 17);
6609 word0 = (((~((1U << 1) - 1)) << 17) & word0) | ((((1U << 1) - 1) &
value) << 17);
6612 CONSTEXPR uint32_t get_ob1_valid_c1()
const
6614 uint32_t
value = ((1U << 1) - 1) & (word0 >> 18);
6617 uint32_t get_ob1_valid_c1()
const volatile
6619 uint32_t
value = ((1U << 1) - 1) & (word0 >> 18);
6624 word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) &
value) << 18);
6629 word0 = (((~((1U << 1) - 1)) << 18) & word0) | ((((1U << 1) - 1) &
value) << 18);
6632 CONSTEXPR uint32_t get_ob1_ready_c1()
const
6634 uint32_t
value = ((1U << 1) - 1) & (word0 >> 19);
6637 uint32_t get_ob1_ready_c1()
const volatile
6639 uint32_t
value = ((1U << 1) - 1) & (word0 >> 19);
6644 word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) &
value) << 19);
6649 word0 = (((~((1U << 1) - 1)) << 19) & word0) | ((((1U << 1) - 1) &
value) << 19);
6652 CONSTEXPR uint32_t get_wd_bitstream_valid_c1()
const
6654 uint32_t
value = ((1U << 1) - 1) & (word0 >> 20);
6657 uint32_t get_wd_bitstream_valid_c1()
const volatile
6659 uint32_t
value = ((1U << 1) - 1) & (word0 >> 20);
6664 word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) &
value) << 20);
6669 word0 = (((~((1U << 1) - 1)) << 20) & word0) | ((((1U << 1) - 1) &
value) << 20);
6672 CONSTEXPR uint32_t get_wd_bitstream_ready_c1()
const
6674 uint32_t
value = ((1U << 1) - 1) & (word0 >> 21);
6677 uint32_t get_wd_bitstream_ready_c1()
const volatile
6679 uint32_t
value = ((1U << 1) - 1) & (word0 >> 21);
6684 word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) &
value) << 21);
6689 word0 = (((~((1U << 1) - 1)) << 21) & word0) | ((((1U << 1) - 1) &
value) << 21);
6692 CONSTEXPR uint32_t get_bs_bitstream_valid_c1()
const
6694 uint32_t
value = ((1U << 1) - 1) & (word0 >> 22);
6697 uint32_t get_bs_bitstream_valid_c1()
const volatile
6699 uint32_t
value = ((1U << 1) - 1) & (word0 >> 22);
6704 word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) &
value) << 22);
6709 word0 = (((~((1U << 1) - 1)) << 22) & word0) | ((((1U << 1) - 1) &
value) << 22);
6712 CONSTEXPR uint32_t get_bs_bitstream_ready_c1()
const
6714 uint32_t
value = ((1U << 1) - 1) & (word0 >> 23);
6717 uint32_t get_bs_bitstream_ready_c1()
const volatile
6719 uint32_t
value = ((1U << 1) - 1) & (word0 >> 23);
6724 word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) &
value) << 23);
6729 word0 = (((~((1U << 1) - 1)) << 23) & word0) | ((((1U << 1) - 1) &
value) << 23);
6743 uint32_t top_level_clk : 1;
6744 uint32_t cc_clk : 1;
6745 uint32_t dma_clk : 1;
6746 uint32_t mac_clk : 1;
6747 uint32_t ao_clk : 1;
6748 uint32_t wd_clk : 1;
6749 uint32_t reserved0 : 26;
6764 void operator=(uint32_t
value)
volatile
6772 operator uint32_t()
volatile
6780 CONSTEXPR uint32_t get_top_level_clk()
const
6782 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
6785 uint32_t get_top_level_clk()
const volatile
6787 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
6792 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
6797 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
6802 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
6805 uint32_t get_cc_clk()
const volatile
6807 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
6812 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
6817 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
6822 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
6825 uint32_t get_dma_clk()
const volatile
6827 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
6832 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
6837 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
6842 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
6845 uint32_t get_mac_clk()
const volatile
6847 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
6852 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
6857 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
6862 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
6865 uint32_t get_ao_clk()
const volatile
6867 uint32_t
value = ((1U << 1) - 1) & (word0 >> 4);
6872 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
6877 word0 = (((~((1U << 1) - 1)) << 4) & word0) | ((((1U << 1) - 1) &
value) << 4);
6882 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
6885 uint32_t get_wd_clk()
const volatile
6887 uint32_t
value = ((1U << 1) - 1) & (word0 >> 5);
6892 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
6897 word0 = (((~((1U << 1) - 1)) << 5) & word0) | ((((1U << 1) - 1) &
value) << 5);
6926 void operator=(uint32_t
value)
volatile
6934 operator uint32_t()
volatile
6944 uint32_t
value = word0;
6947 uint32_t get_addr()
const volatile
6949 uint32_t
value = word0;
6988 void operator=(uint32_t
value)
volatile
6996 operator uint32_t()
volatile
7006 uint32_t
value = word0;
7009 uint32_t get_misc()
const volatile
7011 uint32_t
value = word0;
7050 void operator=(uint32_t
value)
volatile
7058 operator uint32_t()
volatile
7068 uint32_t
value = word0;
7071 uint32_t get_core()
const volatile
7073 uint32_t
value = word0;
7098 uint32_t block : 32;
7113 void operator=(uint32_t
value)
volatile
7121 operator uint32_t()
volatile
7131 uint32_t
value = word0;
7134 uint32_t get_block()
const volatile
7136 uint32_t
value = word0;
7160 uint32_t cnt_en : 1;
7161 uint32_t event_cnt_rst : 1;
7162 uint32_t cycle_cnt_rst : 1;
7163 uint32_t mask_en : 1;
7164 uint32_t reserved0 : 7;
7165 uint32_t num_event_cnt : 5;
7166 uint32_t reserved1 : 16;
7181 void operator=(uint32_t
value)
volatile
7189 operator uint32_t()
volatile
7199 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7202 uint32_t get_cnt_en()
const volatile
7204 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7209 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7212 volatile pmcr_r &set_cnt_en(uint32_t
value)
volatile
7214 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7217 CONSTEXPR uint32_t get_event_cnt_rst()
const
7219 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7222 uint32_t get_event_cnt_rst()
const volatile
7224 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7229 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7232 volatile pmcr_r &set_event_cnt_rst(uint32_t
value)
volatile
7234 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7237 CONSTEXPR uint32_t get_cycle_cnt_rst()
const
7239 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7242 uint32_t get_cycle_cnt_rst()
const volatile
7244 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7249 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7252 volatile pmcr_r &set_cycle_cnt_rst(uint32_t
value)
volatile
7254 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7259 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7262 uint32_t get_mask_en()
const volatile
7264 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7269 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
7272 volatile pmcr_r &set_mask_en(uint32_t
value)
volatile
7274 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
7277 CONSTEXPR uint32_t get_num_event_cnt()
const
7279 uint32_t
value = ((1U << 5) - 1) & (word0 >> 11);
7282 uint32_t get_num_event_cnt()
const volatile
7284 uint32_t
value = ((1U << 5) - 1) & (word0 >> 11);
7289 word0 = (((~((1U << 5) - 1)) << 11) & word0) | ((((1U << 5) - 1) &
value) << 11);
7292 volatile pmcr_r &set_num_event_cnt(uint32_t
value)
volatile
7294 word0 = (((~((1U << 5) - 1)) << 11) & word0) | ((((1U << 5) - 1) &
value) << 11);
7308 uint32_t EVENT_CNT_0 : 1;
7309 uint32_t EVENT_CNT_1 : 1;
7310 uint32_t EVENT_CNT_2 : 1;
7311 uint32_t EVENT_CNT_3 : 1;
7312 uint32_t reserved0 : 27;
7313 uint32_t CYCLE_CNT : 1;
7328 void operator=(uint32_t
value)
volatile
7336 operator uint32_t()
volatile
7344 CONSTEXPR uint32_t get_EVENT_CNT_0()
const
7346 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7349 uint32_t get_EVENT_CNT_0()
const volatile
7351 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7356 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7361 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7364 CONSTEXPR uint32_t get_EVENT_CNT_1()
const
7366 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7369 uint32_t get_EVENT_CNT_1()
const volatile
7371 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7376 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7381 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7384 CONSTEXPR uint32_t get_EVENT_CNT_2()
const
7386 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7389 uint32_t get_EVENT_CNT_2()
const volatile
7391 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7396 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7401 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7404 CONSTEXPR uint32_t get_EVENT_CNT_3()
const
7406 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7409 uint32_t get_EVENT_CNT_3()
const volatile
7411 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7416 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
7421 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
7424 CONSTEXPR uint32_t get_CYCLE_CNT()
const
7426 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
7429 uint32_t get_CYCLE_CNT()
const volatile
7431 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
7436 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
7441 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
7455 uint32_t EVENT_CNT_0 : 1;
7456 uint32_t EVENT_CNT_1 : 1;
7457 uint32_t EVENT_CNT_2 : 1;
7458 uint32_t EVENT_CNT_3 : 1;
7459 uint32_t reserved0 : 27;
7460 uint32_t CYCLE_CNT : 1;
7475 void operator=(uint32_t
value)
volatile
7483 operator uint32_t()
volatile
7491 CONSTEXPR uint32_t get_EVENT_CNT_0()
const
7493 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7496 uint32_t get_EVENT_CNT_0()
const volatile
7498 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7503 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7508 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7511 CONSTEXPR uint32_t get_EVENT_CNT_1()
const
7513 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7516 uint32_t get_EVENT_CNT_1()
const volatile
7518 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7523 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7528 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7531 CONSTEXPR uint32_t get_EVENT_CNT_2()
const
7533 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7536 uint32_t get_EVENT_CNT_2()
const volatile
7538 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7543 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7548 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7551 CONSTEXPR uint32_t get_EVENT_CNT_3()
const
7553 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7556 uint32_t get_EVENT_CNT_3()
const volatile
7558 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7563 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
7568 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
7571 CONSTEXPR uint32_t get_CYCLE_CNT()
const
7573 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
7576 uint32_t get_CYCLE_CNT()
const volatile
7578 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
7583 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
7588 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
7602 uint32_t EVENT_CNT_0_OVF : 1;
7603 uint32_t EVENT_CNT_1_OVF : 1;
7604 uint32_t EVENT_CNT_2_OVF : 1;
7605 uint32_t EVENT_CNT_3_OVF : 1;
7606 uint32_t reserved0 : 27;
7607 uint32_t CYCLE_CNT_OVF : 1;
7622 void operator=(uint32_t
value)
volatile
7630 operator uint32_t()
volatile
7638 CONSTEXPR uint32_t get_EVENT_CNT_0_OVF()
const
7640 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7643 uint32_t get_EVENT_CNT_0_OVF()
const volatile
7645 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7650 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7655 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7658 CONSTEXPR uint32_t get_EVENT_CNT_1_OVF()
const
7660 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7663 uint32_t get_EVENT_CNT_1_OVF()
const volatile
7665 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7670 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7675 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7678 CONSTEXPR uint32_t get_EVENT_CNT_2_OVF()
const
7680 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7683 uint32_t get_EVENT_CNT_2_OVF()
const volatile
7685 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7690 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7695 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7698 CONSTEXPR uint32_t get_EVENT_CNT_3_OVF()
const
7700 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7703 uint32_t get_EVENT_CNT_3_OVF()
const volatile
7705 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7710 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
7715 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
7718 CONSTEXPR uint32_t get_CYCLE_CNT_OVF()
const
7720 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
7723 uint32_t get_CYCLE_CNT_OVF()
const volatile
7725 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
7730 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
7735 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
7749 uint32_t EVENT_CNT_0_OVF : 1;
7750 uint32_t EVENT_CNT_1_OVF : 1;
7751 uint32_t EVENT_CNT_2_OVF : 1;
7752 uint32_t EVENT_CNT_3_OVF : 1;
7753 uint32_t reserved0 : 27;
7754 uint32_t CYCLE_CNT_OVF : 1;
7769 void operator=(uint32_t
value)
volatile
7777 operator uint32_t()
volatile
7785 CONSTEXPR uint32_t get_EVENT_CNT_0_OVF()
const
7787 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7790 uint32_t get_EVENT_CNT_0_OVF()
const volatile
7792 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7797 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7802 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7805 CONSTEXPR uint32_t get_EVENT_CNT_1_OVF()
const
7807 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7810 uint32_t get_EVENT_CNT_1_OVF()
const volatile
7812 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7817 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7822 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7825 CONSTEXPR uint32_t get_EVENT_CNT_2_OVF()
const
7827 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7830 uint32_t get_EVENT_CNT_2_OVF()
const volatile
7832 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7837 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7842 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7845 CONSTEXPR uint32_t get_EVENT_CNT_3_OVF()
const
7847 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7850 uint32_t get_EVENT_CNT_3_OVF()
const volatile
7852 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7857 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
7862 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
7865 CONSTEXPR uint32_t get_CYCLE_CNT_OVF()
const
7867 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
7870 uint32_t get_CYCLE_CNT_OVF()
const volatile
7872 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
7877 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
7882 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
7896 uint32_t EVENT_CNT_0_INT : 1;
7897 uint32_t EVENT_CNT_1_INT : 1;
7898 uint32_t EVENT_CNT_2_INT : 1;
7899 uint32_t EVENT_CNT_3_INT : 1;
7900 uint32_t reserved0 : 27;
7901 uint32_t CYCLE_CNT_INT : 1;
7916 void operator=(uint32_t
value)
volatile
7924 operator uint32_t()
volatile
7932 CONSTEXPR uint32_t get_EVENT_CNT_0_INT()
const
7934 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7937 uint32_t get_EVENT_CNT_0_INT()
const volatile
7939 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
7944 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7949 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
7952 CONSTEXPR uint32_t get_EVENT_CNT_1_INT()
const
7954 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7957 uint32_t get_EVENT_CNT_1_INT()
const volatile
7959 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
7964 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7969 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
7972 CONSTEXPR uint32_t get_EVENT_CNT_2_INT()
const
7974 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7977 uint32_t get_EVENT_CNT_2_INT()
const volatile
7979 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
7984 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7989 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
7992 CONSTEXPR uint32_t get_EVENT_CNT_3_INT()
const
7994 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
7997 uint32_t get_EVENT_CNT_3_INT()
const volatile
7999 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
8004 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
8009 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
8012 CONSTEXPR uint32_t get_CYCLE_CNT_INT()
const
8014 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
8017 uint32_t get_CYCLE_CNT_INT()
const volatile
8019 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
8024 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
8029 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
8043 uint32_t EVENT_CNT_0_INT : 1;
8044 uint32_t EVENT_CNT_1_INT : 1;
8045 uint32_t EVENT_CNT_2_INT : 1;
8046 uint32_t EVENT_CNT_3_INT : 1;
8047 uint32_t reserved0 : 27;
8048 uint32_t CYCLE_CNT_INT : 1;
8063 void operator=(uint32_t
value)
volatile
8071 operator uint32_t()
volatile
8079 CONSTEXPR uint32_t get_EVENT_CNT_0_INT()
const
8081 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
8084 uint32_t get_EVENT_CNT_0_INT()
const volatile
8086 uint32_t
value = ((1U << 1) - 1) & (word0 >> 0);
8091 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
8096 word0 = (((~((1U << 1) - 1)) << 0) & word0) | ((((1U << 1) - 1) &
value) << 0);
8099 CONSTEXPR uint32_t get_EVENT_CNT_1_INT()
const
8101 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
8104 uint32_t get_EVENT_CNT_1_INT()
const volatile
8106 uint32_t
value = ((1U << 1) - 1) & (word0 >> 1);
8111 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
8116 word0 = (((~((1U << 1) - 1)) << 1) & word0) | ((((1U << 1) - 1) &
value) << 1);
8119 CONSTEXPR uint32_t get_EVENT_CNT_2_INT()
const
8121 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
8124 uint32_t get_EVENT_CNT_2_INT()
const volatile
8126 uint32_t
value = ((1U << 1) - 1) & (word0 >> 2);
8131 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
8136 word0 = (((~((1U << 1) - 1)) << 2) & word0) | ((((1U << 1) - 1) &
value) << 2);
8139 CONSTEXPR uint32_t get_EVENT_CNT_3_INT()
const
8141 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
8144 uint32_t get_EVENT_CNT_3_INT()
const volatile
8146 uint32_t
value = ((1U << 1) - 1) & (word0 >> 3);
8151 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
8156 word0 = (((~((1U << 1) - 1)) << 3) & word0) | ((((1U << 1) - 1) &
value) << 3);
8159 CONSTEXPR uint32_t get_CYCLE_CNT_INT()
const
8161 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
8164 uint32_t get_CYCLE_CNT_INT()
const volatile
8166 uint32_t
value = ((1U << 1) - 1) & (word0 >> 31);
8171 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
8176 word0 = (((~((1U << 1) - 1)) << 31) & word0) | ((((1U << 1) - 1) &
value) << 31);
8190 uint32_t CYCLE_CNT_LO : 32;
8191 uint32_t CYCLE_CNT_HI : 16;
8192 uint32_t reserved0 : 16;
8204 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
8205 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
8210 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
8211 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
8213 void operator=(uint64_t
value)
volatile
8215 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
8216 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
8220 return (
static_cast<uint64_t
>(word1) << 32) | word0;
8222 operator uint64_t()
volatile
8224 return (
static_cast<uint64_t
>(word1) << 32) | word0;
8241 uint32_t CYCLE_CNT_CFG_START : 10;
8242 uint32_t reserved0 : 6;
8243 uint32_t CYCLE_CNT_CFG_STOP : 10;
8244 uint32_t reserved1 : 6;
8259 void operator=(uint32_t
value)
volatile
8267 operator uint32_t()
volatile
8275 CONSTEXPR NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_START()
const
8277 NPU_NAMESPACE::pmu_event
value =
static_cast<NPU_NAMESPACE::pmu_event
>(((1U << 10) - 1) & (word0 >> 0));
8280 NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_START()
const volatile
8282 NPU_NAMESPACE::pmu_event
value =
static_cast<NPU_NAMESPACE::pmu_event
>(((1U << 10) - 1) & (word0 >> 0));
8287 word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) &
static_cast<uint32_t
>(
value)) << 0);
8290 volatile pmccntr_cfg_r &set_CYCLE_CNT_CFG_START(NPU_NAMESPACE::pmu_event
value)
volatile
8292 word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) &
static_cast<uint32_t
>(
value)) << 0);
8295 CONSTEXPR NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_STOP()
const
8297 NPU_NAMESPACE::pmu_event
value =
static_cast<NPU_NAMESPACE::pmu_event
>(((1U << 10) - 1) & (word0 >> 16));
8300 NPU_NAMESPACE::pmu_event get_CYCLE_CNT_CFG_STOP()
const volatile
8302 NPU_NAMESPACE::pmu_event
value =
static_cast<NPU_NAMESPACE::pmu_event
>(((1U << 10) - 1) & (word0 >> 16));
8307 word0 = (((~((1U << 10) - 1)) << 16) & word0) | ((((1U << 10) - 1) &
static_cast<uint32_t
>(
value)) << 16);
8310 volatile pmccntr_cfg_r &set_CYCLE_CNT_CFG_STOP(NPU_NAMESPACE::pmu_event
value)
volatile
8312 word0 = (((~((1U << 10) - 1)) << 16) & word0) | ((((1U << 10) - 1) &
static_cast<uint32_t
>(
value)) << 16);
8326 uint32_t CH_SEL : 4;
8327 uint32_t reserved0 : 4;
8328 uint32_t AXI_CNT_SEL : 2;
8329 uint32_t BW_CH_SEL_EN : 1;
8330 uint32_t reserved1 : 21;
8345 void operator=(uint32_t
value)
volatile
8353 operator uint32_t()
volatile
8361 CONSTEXPR NPU_NAMESPACE::pmu_axi_channel get_CH_SEL()
const
8363 NPU_NAMESPACE::pmu_axi_channel
value =
8364 static_cast<NPU_NAMESPACE::pmu_axi_channel
>(((1U << 4) - 1) & (word0 >> 0));
8367 NPU_NAMESPACE::pmu_axi_channel get_CH_SEL()
const volatile
8369 NPU_NAMESPACE::pmu_axi_channel
value =
8370 static_cast<NPU_NAMESPACE::pmu_axi_channel
>(((1U << 4) - 1) & (word0 >> 0));
8375 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) &
static_cast<uint32_t
>(
value)) << 0);
8380 word0 = (((~((1U << 4) - 1)) << 0) & word0) | ((((1U << 4) - 1) &
static_cast<uint32_t
>(
value)) << 0);
8383 CONSTEXPR uint32_t get_AXI_CNT_SEL()
const
8385 uint32_t
value = ((1U << 2) - 1) & (word0 >> 8);
8388 uint32_t get_AXI_CNT_SEL()
const volatile
8390 uint32_t
value = ((1U << 2) - 1) & (word0 >> 8);
8395 word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) &
value) << 8);
8400 word0 = (((~((1U << 2) - 1)) << 8) & word0) | ((((1U << 2) - 1) &
value) << 8);
8403 CONSTEXPR uint32_t get_BW_CH_SEL_EN()
const
8405 uint32_t
value = ((1U << 1) - 1) & (word0 >> 10);
8408 uint32_t get_BW_CH_SEL_EN()
const volatile
8410 uint32_t
value = ((1U << 1) - 1) & (word0 >> 10);
8415 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) &
value) << 10);
8420 word0 = (((~((1U << 1) - 1)) << 10) & word0) | ((((1U << 1) - 1) &
value) << 10);
8434 uint32_t
value : 32;
8449 void operator=(uint32_t
value)
volatile
8457 operator uint32_t()
volatile
8467 uint32_t
value = word0;
8470 uint32_t get_value()
const volatile
8472 uint32_t
value = word0;
8496 uint32_t
value : 32;
8511 void operator=(uint32_t
value)
volatile
8519 operator uint32_t()
volatile
8529 uint32_t
value = word0;
8532 uint32_t get_value()
const volatile
8534 uint32_t
value = word0;
8558 uint32_t
value : 32;
8573 void operator=(uint32_t
value)
volatile
8581 operator uint32_t()
volatile
8591 uint32_t
value = word0;
8594 uint32_t get_value()
const volatile
8596 uint32_t
value = word0;
8620 uint32_t
value : 32;
8635 void operator=(uint32_t
value)
volatile
8643 operator uint32_t()
volatile
8653 uint32_t
value = word0;
8656 uint32_t get_value()
const volatile
8658 uint32_t
value = word0;
8682 uint32_t
value : 32;
8697 void operator=(uint32_t
value)
volatile
8705 operator uint32_t()
volatile
8715 uint32_t
value = word0;
8718 uint32_t get_value()
const volatile
8720 uint32_t
value = word0;
8744 uint32_t
value : 32;
8759 void operator=(uint32_t
value)
volatile
8767 operator uint32_t()
volatile
8777 uint32_t
value = word0;
8780 uint32_t get_value()
const volatile
8782 uint32_t
value = word0;
8806 uint32_t
value : 32;
8821 void operator=(uint32_t
value)
volatile
8829 operator uint32_t()
volatile
8839 uint32_t
value = word0;
8842 uint32_t get_value()
const volatile
8844 uint32_t
value = word0;
8868 uint32_t
value : 32;
8883 void operator=(uint32_t
value)
volatile
8891 operator uint32_t()
volatile
8901 uint32_t
value = word0;
8904 uint32_t get_value()
const volatile
8906 uint32_t
value = word0;
8930 uint32_t
value : 32;
8945 void operator=(uint32_t
value)
volatile
8953 operator uint32_t()
volatile
8963 uint32_t
value = word0;
8966 uint32_t get_value()
const volatile
8968 uint32_t
value = word0;
8992 uint32_t
value : 32;
9007 void operator=(uint32_t
value)
volatile
9015 operator uint32_t()
volatile
9025 uint32_t
value = word0;
9028 uint32_t get_value()
const volatile
9030 uint32_t
value = word0;
9054 uint32_t
value : 32;
9069 void operator=(uint32_t
value)
volatile
9077 operator uint32_t()
volatile
9087 uint32_t
value = word0;
9090 uint32_t get_value()
const volatile
9092 uint32_t
value = word0;
9116 uint32_t
value : 32;
9131 void operator=(uint32_t
value)
volatile
9139 operator uint32_t()
volatile
9149 uint32_t
value = word0;
9152 uint32_t get_value()
const volatile
9154 uint32_t
value = word0;
9178 uint32_t
value : 32;
9193 void operator=(uint32_t
value)
volatile
9201 operator uint32_t()
volatile
9211 uint32_t
value = word0;
9214 uint32_t get_value()
const volatile
9216 uint32_t
value = word0;
9240 uint32_t
value : 32;
9255 void operator=(uint32_t
value)
volatile
9263 operator uint32_t()
volatile
9273 uint32_t
value = word0;
9276 uint32_t get_value()
const volatile
9278 uint32_t
value = word0;
9302 uint32_t
value : 32;
9317 void operator=(uint32_t
value)
volatile
9325 operator uint32_t()
volatile
9335 uint32_t
value = word0;
9338 uint32_t get_value()
const volatile
9340 uint32_t
value = word0;
9364 uint32_t
value : 32;
9379 void operator=(uint32_t
value)
volatile
9387 operator uint32_t()
volatile
9397 uint32_t
value = word0;
9400 uint32_t get_value()
const volatile
9402 uint32_t
value = word0;
9428 uint32_t reserved0 : 24;
9440 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
9441 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
9446 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9447 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9449 void operator=(uint64_t
value)
volatile
9451 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9452 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9456 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9458 operator uint64_t()
volatile
9460 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9477 uint32_t
value : 32;
9492 void operator=(uint32_t
value)
volatile
9500 operator uint32_t()
volatile
9510 uint32_t
value = word0;
9513 uint32_t get_value()
const volatile
9515 uint32_t
value = word0;
9539 uint32_t
value : 32;
9554 void operator=(uint32_t
value)
volatile
9562 operator uint32_t()
volatile
9572 uint32_t
value = word0;
9575 uint32_t get_value()
const volatile
9577 uint32_t
value = word0;
9603 uint32_t reserved0 : 24;
9615 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
9616 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
9621 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9622 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9624 void operator=(uint64_t
value)
volatile
9626 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9627 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9631 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9633 operator uint64_t()
volatile
9635 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9654 uint32_t reserved0 : 24;
9666 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
9667 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
9672 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9673 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9675 void operator=(uint64_t
value)
volatile
9677 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9678 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9682 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9684 operator uint64_t()
volatile
9686 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9705 uint32_t reserved0 : 24;
9717 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
9718 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
9723 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9724 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9726 void operator=(uint64_t
value)
volatile
9728 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9729 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9733 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9735 operator uint64_t()
volatile
9737 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9754 uint32_t
value : 32;
9769 void operator=(uint32_t
value)
volatile
9777 operator uint32_t()
volatile
9787 uint32_t
value = word0;
9790 uint32_t get_value()
const volatile
9792 uint32_t
value = word0;
9818 uint32_t reserved0 : 24;
9830 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
9831 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
9836 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9837 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9839 void operator=(uint64_t
value)
volatile
9841 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9842 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9846 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9848 operator uint64_t()
volatile
9850 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9869 uint32_t reserved0 : 24;
9881 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
9882 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
9887 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9888 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9890 void operator=(uint64_t
value)
volatile
9892 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
9893 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
9897 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9899 operator uint64_t()
volatile
9901 return (
static_cast<uint64_t
>(word1) << 32) | word0;
9918 uint32_t
value : 32;
9933 void operator=(uint32_t
value)
volatile
9941 operator uint32_t()
volatile
9951 uint32_t
value = word0;
9954 uint32_t get_value()
const volatile
9956 uint32_t
value = word0;
9982 uint32_t reserved0 : 24;
9994 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
9995 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
10000 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
10001 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
10003 void operator=(uint64_t
value)
volatile
10005 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
10006 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
10010 return (
static_cast<uint64_t
>(word1) << 32) | word0;
10012 operator uint64_t()
volatile
10014 return (
static_cast<uint64_t
>(word1) << 32) | word0;
10031 uint32_t
value : 32;
10046 void operator=(uint32_t
value)
volatile
10054 operator uint32_t()
volatile
10064 uint32_t
value = word0;
10067 uint32_t get_value()
const volatile
10069 uint32_t
value = word0;
10093 uint32_t
value : 32;
10108 void operator=(uint32_t
value)
volatile
10116 operator uint32_t()
volatile
10126 uint32_t
value = word0;
10129 uint32_t get_value()
const volatile
10131 uint32_t
value = word0;
10155 uint32_t
value : 32;
10170 void operator=(uint32_t
value)
volatile
10178 operator uint32_t()
volatile
10188 uint32_t
value = word0;
10191 uint32_t get_value()
const volatile
10193 uint32_t
value = word0;
10217 uint32_t count : 32;
10232 void operator=(uint32_t
value)
volatile
10240 operator uint32_t()
volatile
10250 uint32_t
value = word0;
10253 uint32_t get_count()
const volatile
10255 uint32_t
value = word0;
10279 uint32_t EV_TYPE : 10;
10280 uint32_t reserved0 : 22;
10295 void operator=(uint32_t
value)
volatile
10303 operator uint32_t()
volatile
10311 CONSTEXPR NPU_NAMESPACE::pmu_event get_EV_TYPE()
const
10313 NPU_NAMESPACE::pmu_event
value =
static_cast<NPU_NAMESPACE::pmu_event
>(((1U << 10) - 1) & (word0 >> 0));
10316 NPU_NAMESPACE::pmu_event get_EV_TYPE()
const volatile
10318 NPU_NAMESPACE::pmu_event
value =
static_cast<NPU_NAMESPACE::pmu_event
>(((1U << 10) - 1) & (word0 >> 0));
10323 word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) &
static_cast<uint32_t
>(
value)) << 0);
10326 volatile pmevtyper_r &set_EV_TYPE(NPU_NAMESPACE::pmu_event
value)
volatile
10328 word0 = (((~((1U << 10) - 1)) << 0) & word0) | ((((1U << 10) - 1) &
static_cast<uint32_t
>(
value)) << 0);
10342 uint32_t mem_word : 32;
10357 void operator=(uint32_t
value)
volatile
10365 operator uint32_t()
volatile
10373 CONSTEXPR uint32_t get_mem_word()
const
10375 uint32_t
value = word0;
10378 uint32_t get_mem_word()
const volatile
10380 uint32_t
value = word0;
10404 uint32_t
value : 32;
10419 void operator=(uint32_t
value)
volatile
10427 operator uint32_t()
volatile
10437 uint32_t
value = word0;
10440 uint32_t get_value()
const volatile
10442 uint32_t
value = word0;
10466 uint32_t
value : 32;
10481 void operator=(uint32_t
value)
volatile
10489 operator uint32_t()
volatile
10499 uint32_t
value = word0;
10502 uint32_t get_value()
const volatile
10504 uint32_t
value = word0;
10528 uint32_t
value : 32;
10543 void operator=(uint32_t
value)
volatile
10551 operator uint32_t()
volatile
10561 uint32_t
value = word0;
10564 uint32_t get_value()
const volatile
10566 uint32_t
value = word0;
10590 uint32_t
value : 32;
10605 void operator=(uint32_t
value)
volatile
10613 operator uint32_t()
volatile
10623 uint32_t
value = word0;
10626 uint32_t get_value()
const volatile
10628 uint32_t
value = word0;
10652 uint32_t
value : 32;
10667 void operator=(uint32_t
value)
volatile
10675 operator uint32_t()
volatile
10685 uint32_t
value = word0;
10688 uint32_t get_value()
const volatile
10690 uint32_t
value = word0;
10714 uint32_t
value : 32;
10729 void operator=(uint32_t
value)
volatile
10737 operator uint32_t()
volatile
10747 uint32_t
value = word0;
10750 uint32_t get_value()
const volatile
10752 uint32_t
value = word0;
10776 uint32_t
value : 32;
10791 void operator=(uint32_t
value)
volatile
10799 operator uint32_t()
volatile
10809 uint32_t
value = word0;
10812 uint32_t get_value()
const volatile
10814 uint32_t
value = word0;
10838 uint32_t
value : 32;
10853 void operator=(uint32_t
value)
volatile
10861 operator uint32_t()
volatile
10871 uint32_t
value = word0;
10874 uint32_t get_value()
const volatile
10876 uint32_t
value = word0;
10900 uint32_t
value : 32;
10915 void operator=(uint32_t
value)
volatile
10923 operator uint32_t()
volatile
10933 uint32_t
value = word0;
10936 uint32_t get_value()
const volatile
10938 uint32_t
value = word0;
10962 uint32_t
value : 32;
10977 void operator=(uint32_t
value)
volatile
10985 operator uint32_t()
volatile
10995 uint32_t
value = word0;
10998 uint32_t get_value()
const volatile
11000 uint32_t
value = word0;
11024 uint32_t
value : 32;
11039 void operator=(uint32_t
value)
volatile
11047 operator uint32_t()
volatile
11057 uint32_t
value = word0;
11060 uint32_t get_value()
const volatile
11062 uint32_t
value = word0;
11086 uint32_t
value : 32;
11101 void operator=(uint32_t
value)
volatile
11109 operator uint32_t()
volatile
11119 uint32_t
value = word0;
11122 uint32_t get_value()
const volatile
11124 uint32_t
value = word0;
11148 uint32_t
value : 32;
11163 void operator=(uint32_t
value)
volatile
11171 operator uint32_t()
volatile
11181 uint32_t
value = word0;
11184 uint32_t get_value()
const volatile
11186 uint32_t
value = word0;
11210 uint32_t
value : 32;
11225 void operator=(uint32_t
value)
volatile
11233 operator uint32_t()
volatile
11243 uint32_t
value = word0;
11246 uint32_t get_value()
const volatile
11248 uint32_t
value = word0;
11272 uint32_t
value : 32;
11287 void operator=(uint32_t
value)
volatile
11295 operator uint32_t()
volatile
11305 uint32_t
value = word0;
11308 uint32_t get_value()
const volatile
11310 uint32_t
value = word0;
11334 uint32_t
value : 32;
11349 void operator=(uint32_t
value)
volatile
11357 operator uint32_t()
volatile
11367 uint32_t
value = word0;
11370 uint32_t get_value()
const volatile
11372 uint32_t
value = word0;
11396 uint32_t
value : 32;
11411 void operator=(uint32_t
value)
volatile
11419 operator uint32_t()
volatile
11429 uint32_t
value = word0;
11432 uint32_t get_value()
const volatile
11434 uint32_t
value = word0;
11458 uint32_t
value : 32;
11473 void operator=(uint32_t
value)
volatile
11481 operator uint32_t()
volatile
11491 uint32_t
value = word0;
11494 uint32_t get_value()
const volatile
11496 uint32_t
value = word0;
11520 uint32_t
value : 32;
11535 void operator=(uint32_t
value)
volatile
11543 operator uint32_t()
volatile
11553 uint32_t
value = word0;
11556 uint32_t get_value()
const volatile
11558 uint32_t
value = word0;
11582 uint32_t
value : 32;
11597 void operator=(uint32_t
value)
volatile
11605 operator uint32_t()
volatile
11615 uint32_t
value = word0;
11618 uint32_t get_value()
const volatile
11620 uint32_t
value = word0;
11644 uint32_t
value : 32;
11659 void operator=(uint32_t
value)
volatile
11667 operator uint32_t()
volatile
11677 uint32_t
value = word0;
11680 uint32_t get_value()
const volatile
11682 uint32_t
value = word0;
11706 uint32_t
value : 32;
11721 void operator=(uint32_t
value)
volatile
11729 operator uint32_t()
volatile
11739 uint32_t
value = word0;
11742 uint32_t get_value()
const volatile
11744 uint32_t
value = word0;
11768 uint32_t
value : 32;
11783 void operator=(uint32_t
value)
volatile
11791 operator uint32_t()
volatile
11801 uint32_t
value = word0;
11804 uint32_t get_value()
const volatile
11806 uint32_t
value = word0;
11830 uint32_t
value : 32;
11845 void operator=(uint32_t
value)
volatile
11853 operator uint32_t()
volatile
11863 uint32_t
value = word0;
11866 uint32_t get_value()
const volatile
11868 uint32_t
value = word0;
11892 uint32_t
value : 32;
11907 void operator=(uint32_t
value)
volatile
11915 operator uint32_t()
volatile
11925 uint32_t
value = word0;
11928 uint32_t get_value()
const volatile
11930 uint32_t
value = word0;
11954 uint32_t
value : 32;
11969 void operator=(uint32_t
value)
volatile
11977 operator uint32_t()
volatile
11987 uint32_t
value = word0;
11990 uint32_t get_value()
const volatile
11992 uint32_t
value = word0;
12016 uint32_t
value : 32;
12031 void operator=(uint32_t
value)
volatile
12039 operator uint32_t()
volatile
12049 uint32_t
value = word0;
12052 uint32_t get_value()
const volatile
12054 uint32_t
value = word0;
12078 uint32_t
value : 32;
12093 void operator=(uint32_t
value)
volatile
12101 operator uint32_t()
volatile
12111 uint32_t
value = word0;
12114 uint32_t get_value()
const volatile
12116 uint32_t
value = word0;
12155 void operator=(uint32_t
value)
volatile
12163 operator uint32_t()
volatile
12173 uint32_t
value = word0;
12176 uint32_t get_value()
const volatile
12178 uint32_t
value = word0;
12202 uint32_t
value : 32;
12217 void operator=(uint32_t
value)
volatile
12225 operator uint32_t()
volatile
12235 uint32_t
value = word0;
12238 uint32_t get_value()
const volatile
12240 uint32_t
value = word0;
12264 uint32_t
value : 32;
12279 void operator=(uint32_t
value)
volatile
12287 operator uint32_t()
volatile
12297 uint32_t
value = word0;
12300 uint32_t get_value()
const volatile
12302 uint32_t
value = word0;
12326 uint32_t
value : 32;
12341 void operator=(uint32_t
value)
volatile
12349 operator uint32_t()
volatile
12359 uint32_t
value = word0;
12362 uint32_t get_value()
const volatile
12364 uint32_t
value = word0;
12388 uint32_t
value : 32;
12403 void operator=(uint32_t
value)
volatile
12411 operator uint32_t()
volatile
12421 uint32_t
value = word0;
12424 uint32_t get_value()
const volatile
12426 uint32_t
value = word0;
12450 uint32_t
value : 32;
12465 void operator=(uint32_t
value)
volatile
12473 operator uint32_t()
volatile
12483 uint32_t
value = word0;
12486 uint32_t get_value()
const volatile
12488 uint32_t
value = word0;
12512 uint32_t
value : 32;
12527 void operator=(uint32_t
value)
volatile
12535 operator uint32_t()
volatile
12545 uint32_t
value = word0;
12548 uint32_t get_value()
const volatile
12550 uint32_t
value = word0;
12574 uint32_t
value : 32;
12589 void operator=(uint32_t
value)
volatile
12597 operator uint32_t()
volatile
12607 uint32_t
value = word0;
12610 uint32_t get_value()
const volatile
12612 uint32_t
value = word0;
12636 uint32_t
value : 32;
12651 void operator=(uint32_t
value)
volatile
12659 operator uint32_t()
volatile
12669 uint32_t
value = word0;
12672 uint32_t get_value()
const volatile
12674 uint32_t
value = word0;
12698 uint32_t
value : 32;
12713 void operator=(uint32_t
value)
volatile
12721 operator uint32_t()
volatile
12731 uint32_t
value = word0;
12734 uint32_t get_value()
const volatile
12736 uint32_t
value = word0;
12760 uint32_t
value : 32;
12775 void operator=(uint32_t
value)
volatile
12783 operator uint32_t()
volatile
12793 uint32_t
value = word0;
12796 uint32_t get_value()
const volatile
12798 uint32_t
value = word0;
12822 uint32_t
value : 32;
12837 void operator=(uint32_t
value)
volatile
12845 operator uint32_t()
volatile
12855 uint32_t
value = word0;
12858 uint32_t get_value()
const volatile
12860 uint32_t
value = word0;
12884 uint32_t
value : 32;
12899 void operator=(uint32_t
value)
volatile
12907 operator uint32_t()
volatile
12917 uint32_t
value = word0;
12920 uint32_t get_value()
const volatile
12922 uint32_t
value = word0;
12946 uint32_t
value : 32;
12961 void operator=(uint32_t
value)
volatile
12969 operator uint32_t()
volatile
12979 uint32_t
value = word0;
12982 uint32_t get_value()
const volatile
12984 uint32_t
value = word0;
13008 uint32_t
value : 32;
13023 void operator=(uint32_t
value)
volatile
13031 operator uint32_t()
volatile
13041 uint32_t
value = word0;
13044 uint32_t get_value()
const volatile
13046 uint32_t
value = word0;
13070 uint32_t
value : 32;
13085 void operator=(uint32_t
value)
volatile
13093 operator uint32_t()
volatile
13103 uint32_t
value = word0;
13106 uint32_t get_value()
const volatile
13108 uint32_t
value = word0;
13132 uint32_t
value : 32;
13147 void operator=(uint32_t
value)
volatile
13155 operator uint32_t()
volatile
13165 uint32_t
value = word0;
13168 uint32_t get_value()
const volatile
13170 uint32_t
value = word0;
13194 uint32_t
value : 32;
13209 void operator=(uint32_t
value)
volatile
13217 operator uint32_t()
volatile
13227 uint32_t
value = word0;
13230 uint32_t get_value()
const volatile
13232 uint32_t
value = word0;
13256 uint32_t
value : 32;
13271 void operator=(uint32_t
value)
volatile
13279 operator uint32_t()
volatile
13289 uint32_t
value = word0;
13292 uint32_t get_value()
const volatile
13294 uint32_t
value = word0;
13318 uint32_t
value : 32;
13333 void operator=(uint32_t
value)
volatile
13341 operator uint32_t()
volatile
13351 uint32_t
value = word0;
13354 uint32_t get_value()
const volatile
13356 uint32_t
value = word0;
13380 uint32_t
value : 32;
13395 void operator=(uint32_t
value)
volatile
13403 operator uint32_t()
volatile
13413 uint32_t
value = word0;
13416 uint32_t get_value()
const volatile
13418 uint32_t
value = word0;
13442 uint32_t
value : 32;
13457 void operator=(uint32_t
value)
volatile
13465 operator uint32_t()
volatile
13475 uint32_t
value = word0;
13478 uint32_t get_value()
const volatile
13480 uint32_t
value = word0;
13504 uint32_t value_LO : 32;
13505 uint32_t value_HI : 32;
13517 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
13518 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
13523 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13524 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13526 void operator=(uint64_t
value)
volatile
13528 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13529 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13533 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13535 operator uint64_t()
volatile
13537 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13554 uint32_t value_LO : 32;
13555 uint32_t value_HI : 32;
13567 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
13568 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
13573 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13574 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13576 void operator=(uint64_t
value)
volatile
13578 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13579 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13583 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13585 operator uint64_t()
volatile
13587 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13604 uint32_t value_LO : 32;
13605 uint32_t value_HI : 32;
13617 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
13618 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
13623 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13624 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13626 void operator=(uint64_t
value)
volatile
13628 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13629 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13633 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13635 operator uint64_t()
volatile
13637 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13654 uint32_t value_LO : 32;
13655 uint32_t value_HI : 32;
13667 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
13668 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
13673 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13674 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13676 void operator=(uint64_t
value)
volatile
13678 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13679 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13683 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13685 operator uint64_t()
volatile
13687 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13704 uint32_t value_LO : 32;
13705 uint32_t value_HI : 32;
13717 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
13718 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
13723 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13724 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13726 void operator=(uint64_t
value)
volatile
13728 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13729 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13733 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13735 operator uint64_t()
volatile
13737 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13754 uint32_t value_LO : 32;
13755 uint32_t value_HI : 32;
13767 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
13768 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
13773 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13774 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13776 void operator=(uint64_t
value)
volatile
13778 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13779 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13783 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13785 operator uint64_t()
volatile
13787 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13804 uint32_t value_LO : 32;
13805 uint32_t value_HI : 32;
13817 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
13818 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
13823 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13824 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13826 void operator=(uint64_t
value)
volatile
13828 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13829 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13833 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13835 operator uint64_t()
volatile
13837 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13854 uint32_t value_LO : 32;
13855 uint32_t value_HI : 32;
13867 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
13868 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
13873 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13874 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13876 void operator=(uint64_t
value)
volatile
13878 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13879 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13883 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13885 operator uint64_t()
volatile
13887 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13904 uint32_t value_LO : 32;
13905 uint32_t value_HI : 32;
13917 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
13918 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
13923 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13924 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13926 void operator=(uint64_t
value)
volatile
13928 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13929 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13933 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13935 operator uint64_t()
volatile
13937 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13954 uint32_t value_LO : 32;
13955 uint32_t value_HI : 32;
13967 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
13968 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
13973 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13974 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13976 void operator=(uint64_t
value)
volatile
13978 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
13979 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
13983 return (
static_cast<uint64_t
>(word1) << 32) | word0;
13985 operator uint64_t()
volatile
13987 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14004 uint32_t value_LO : 32;
14005 uint32_t value_HI : 32;
14017 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14018 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14023 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14024 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14026 void operator=(uint64_t
value)
volatile
14028 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14029 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14033 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14035 operator uint64_t()
volatile
14037 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14054 uint32_t value_LO : 32;
14055 uint32_t value_HI : 32;
14067 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14068 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14073 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14074 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14076 void operator=(uint64_t
value)
volatile
14078 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14079 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14083 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14085 operator uint64_t()
volatile
14087 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14104 uint32_t value_LO : 32;
14105 uint32_t value_HI : 32;
14117 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14118 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14123 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14124 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14126 void operator=(uint64_t
value)
volatile
14128 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14129 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14133 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14135 operator uint64_t()
volatile
14137 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14154 uint32_t value_LO : 32;
14155 uint32_t value_HI : 32;
14167 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14168 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14173 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14174 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14176 void operator=(uint64_t
value)
volatile
14178 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14179 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14183 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14185 operator uint64_t()
volatile
14187 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14204 uint32_t value_LO : 32;
14205 uint32_t value_HI : 32;
14217 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14218 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14223 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14224 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14226 void operator=(uint64_t
value)
volatile
14228 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14229 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14233 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14235 operator uint64_t()
volatile
14237 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14254 uint32_t value_LO : 32;
14255 uint32_t value_HI : 32;
14267 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14268 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14273 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14274 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14276 void operator=(uint64_t
value)
volatile
14278 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14279 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14283 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14285 operator uint64_t()
volatile
14287 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14304 uint32_t value_LO : 32;
14305 uint32_t value_HI : 32;
14317 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14318 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14323 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14324 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14326 void operator=(uint64_t
value)
volatile
14328 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14329 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14333 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14335 operator uint64_t()
volatile
14337 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14354 uint32_t value_LO : 32;
14355 uint32_t value_HI : 32;
14367 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14368 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14373 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14374 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14376 void operator=(uint64_t
value)
volatile
14378 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14379 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14383 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14385 operator uint64_t()
volatile
14387 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14404 uint32_t
value : 32;
14419 void operator=(uint32_t
value)
volatile
14427 operator uint32_t()
volatile
14437 uint32_t
value = word0;
14440 uint32_t get_value()
const volatile
14442 uint32_t
value = word0;
14466 uint32_t
value : 32;
14481 void operator=(uint32_t
value)
volatile
14489 operator uint32_t()
volatile
14499 uint32_t
value = word0;
14502 uint32_t get_value()
const volatile
14504 uint32_t
value = word0;
14528 uint32_t
value : 32;
14543 void operator=(uint32_t
value)
volatile
14551 operator uint32_t()
volatile
14561 uint32_t
value = word0;
14564 uint32_t get_value()
const volatile
14566 uint32_t
value = word0;
14590 uint32_t
value : 32;
14605 void operator=(uint32_t
value)
volatile
14613 operator uint32_t()
volatile
14623 uint32_t
value = word0;
14626 uint32_t get_value()
const volatile
14628 uint32_t
value = word0;
14652 uint32_t
value : 32;
14667 void operator=(uint32_t
value)
volatile
14675 operator uint32_t()
volatile
14685 uint32_t
value = word0;
14688 uint32_t get_value()
const volatile
14690 uint32_t
value = word0;
14714 uint32_t value_LO : 32;
14715 uint32_t value_HI : 32;
14727 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14728 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14733 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14734 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14736 void operator=(uint64_t
value)
volatile
14738 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14739 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14743 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14745 operator uint64_t()
volatile
14747 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14764 uint32_t value_LO : 32;
14765 uint32_t value_HI : 32;
14777 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14778 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14783 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14784 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14786 void operator=(uint64_t
value)
volatile
14788 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14789 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14793 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14795 operator uint64_t()
volatile
14797 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14814 uint32_t value_LO : 32;
14815 uint32_t value_HI : 32;
14827 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14828 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14833 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14834 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14836 void operator=(uint64_t
value)
volatile
14838 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14839 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14843 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14845 operator uint64_t()
volatile
14847 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14877 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14878 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14883 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14884 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14886 void operator=(uint64_t
value)
volatile
14888 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14889 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14893 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14895 operator uint64_t()
volatile
14897 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14927 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14928 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14933 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14934 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14936 void operator=(uint64_t
value)
volatile
14938 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14939 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14943 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14945 operator uint64_t()
volatile
14947 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14964 uint32_t value_LO : 32;
14965 uint32_t value_HI : 32;
14977 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
14978 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
14983 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14984 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14986 void operator=(uint64_t
value)
volatile
14988 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
14989 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
14993 return (
static_cast<uint64_t
>(word1) << 32) | word0;
14995 operator uint64_t()
volatile
14997 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15014 uint32_t value_LO : 32;
15015 uint32_t value_HI : 32;
15027 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
15028 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
15033 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15034 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15036 void operator=(uint64_t
value)
volatile
15038 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15039 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15043 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15045 operator uint64_t()
volatile
15047 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15064 uint32_t value_LO : 32;
15065 uint32_t value_HI : 32;
15077 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
15078 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
15083 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15084 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15086 void operator=(uint64_t
value)
volatile
15088 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15089 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15093 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15095 operator uint64_t()
volatile
15097 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15114 uint32_t value_LO : 32;
15115 uint32_t value_HI : 32;
15127 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
15128 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
15133 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15134 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15136 void operator=(uint64_t
value)
volatile
15138 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15139 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15143 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15145 operator uint64_t()
volatile
15147 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15164 uint32_t value_LO : 32;
15165 uint32_t value_HI : 32;
15177 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
15178 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
15183 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15184 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15186 void operator=(uint64_t
value)
volatile
15188 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15189 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15193 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15195 operator uint64_t()
volatile
15197 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15214 uint32_t value_LO : 32;
15215 uint32_t value_HI : 32;
15227 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
15228 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
15233 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15234 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15236 void operator=(uint64_t
value)
volatile
15238 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15239 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15243 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15245 operator uint64_t()
volatile
15247 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15264 uint32_t value_LO : 32;
15265 uint32_t value_HI : 32;
15277 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
15278 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
15283 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15284 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15286 void operator=(uint64_t
value)
volatile
15288 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15289 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15293 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15295 operator uint64_t()
volatile
15297 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15327 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
15328 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
15333 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15334 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15336 void operator=(uint64_t
value)
volatile
15338 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15339 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15343 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15345 operator uint64_t()
volatile
15347 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15377 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
15378 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
15383 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15384 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15386 void operator=(uint64_t
value)
volatile
15388 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15389 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15393 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15395 operator uint64_t()
volatile
15397 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15427 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
15428 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
15433 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15434 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15436 void operator=(uint64_t
value)
volatile
15438 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15439 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15443 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15445 operator uint64_t()
volatile
15447 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15477 word0(static_cast<uint32_t>((init)&std::numeric_limits<uint64_t>::
max())),
15478 word1(static_cast<uint32_t>((init >> 32) & std::numeric_limits<uint64_t>::
max()))
15483 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15484 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15486 void operator=(uint64_t
value)
volatile
15488 word0 =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
15489 word1 =
static_cast<uint32_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
15493 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15495 operator uint64_t()
volatile
15497 return (
static_cast<uint64_t
>(word1) << 32) | word0;
15514 uint32_t
value : 32;
15529 void operator=(uint32_t
value)
volatile
15537 operator uint32_t()
volatile
15547 uint32_t
value = word0;
15550 uint32_t get_value()
const volatile
15552 uint32_t
value = word0;
15576 uint32_t PID4 : 32;
15591 void operator=(uint32_t
value)
volatile
15599 operator uint32_t()
volatile
15609 uint32_t
value = word0;
15612 uint32_t get_PID4()
const volatile
15614 uint32_t
value = word0;
15622 volatile pid4_r &set_PID4(uint32_t
value)
volatile
15638 uint32_t PID5 : 32;
15653 void operator=(uint32_t
value)
volatile
15661 operator uint32_t()
volatile
15671 uint32_t
value = word0;
15674 uint32_t get_PID5()
const volatile
15676 uint32_t
value = word0;
15684 volatile pid5_r &set_PID5(uint32_t
value)
volatile
15700 uint32_t PID6 : 32;
15715 void operator=(uint32_t
value)
volatile
15723 operator uint32_t()
volatile
15733 uint32_t
value = word0;
15736 uint32_t get_PID6()
const volatile
15738 uint32_t
value = word0;
15746 volatile pid6_r &set_PID6(uint32_t
value)
volatile
15762 uint32_t PID7 : 32;
15777 void operator=(uint32_t
value)
volatile
15785 operator uint32_t()
volatile
15795 uint32_t
value = word0;
15798 uint32_t get_PID7()
const volatile
15800 uint32_t
value = word0;
15808 volatile pid7_r &set_PID7(uint32_t
value)
volatile
15824 uint32_t PID0 : 32;
15839 void operator=(uint32_t
value)
volatile
15847 operator uint32_t()
volatile
15857 uint32_t
value = word0;
15860 uint32_t get_PID0()
const volatile
15862 uint32_t
value = word0;
15870 volatile pid0_r &set_PID0(uint32_t
value)
volatile
15887 uint32_t PID1 : 32;
15902 void operator=(uint32_t
value)
volatile
15910 operator uint32_t()
volatile
15920 uint32_t
value = word0;
15923 uint32_t get_PID1()
const volatile
15925 uint32_t
value = word0;
15933 volatile pid1_r &set_PID1(uint32_t
value)
volatile
15949 uint32_t PID2 : 32;
15964 void operator=(uint32_t
value)
volatile
15972 operator uint32_t()
volatile
15982 uint32_t
value = word0;
15985 uint32_t get_PID2()
const volatile
15987 uint32_t
value = word0;
15995 volatile pid2_r &set_PID2(uint32_t
value)
volatile
16011 uint32_t PID3 : 32;
16026 void operator=(uint32_t
value)
volatile
16034 operator uint32_t()
volatile
16044 uint32_t
value = word0;
16047 uint32_t get_PID3()
const volatile
16049 uint32_t
value = word0;
16057 volatile pid3_r &set_PID3(uint32_t
value)
volatile
16073 uint32_t CID0 : 32;
16088 void operator=(uint32_t
value)
volatile
16096 operator uint32_t()
volatile
16106 uint32_t
value = word0;
16109 uint32_t get_CID0()
const volatile
16111 uint32_t
value = word0;
16119 volatile cid0_r &set_CID0(uint32_t
value)
volatile
16135 uint32_t CID1 : 32;
16150 void operator=(uint32_t
value)
volatile
16158 operator uint32_t()
volatile
16168 uint32_t
value = word0;
16171 uint32_t get_CID1()
const volatile
16173 uint32_t
value = word0;
16181 volatile cid1_r &set_CID1(uint32_t
value)
volatile
16197 uint32_t CID2 : 32;
16212 void operator=(uint32_t
value)
volatile
16220 operator uint32_t()
volatile
16230 uint32_t
value = word0;
16233 uint32_t get_CID2()
const volatile
16235 uint32_t
value = word0;
16243 volatile cid2_r &set_CID2(uint32_t
value)
volatile
16259 uint32_t CID3 : 32;
16274 void operator=(uint32_t
value)
volatile
16282 operator uint32_t()
volatile
16292 uint32_t
value = word0;
16295 uint32_t get_CID3()
const volatile
16297 uint32_t
value = word0;
16305 volatile cid3_r &set_CID3(uint32_t
value)
volatile
16326 uint32_t unused0[3];
16332 uint32_t unused1[12];
16334 uint32_t unused2[16];
16338 uint32_t unused3[1];
16341 uint32_t unused4[10];
16347 uint32_t unused5[11];
16355 uint32_t unused6[1];
16359 uint32_t unused7[20];
16387 uint32_t unused8[11];
16391 uint32_t unused9[16];
16393 uint32_t unused10[28];
16395 uint32_t unused11[28];
16403 uint32_t unused12[1];
16405 uint32_t unused13[1];
16411 uint32_t unused14[1];
16413 uint32_t unused15[1];
16422 uint32_t unused16[1];
16426 uint32_t unused17[2];
16438 uint32_t unused18[3];
16440 uint32_t unused19[1];
16446 uint32_t unused20[12];
16449 uint32_t unused21[3];
16451 uint32_t unused22[3];
16457 uint32_t unused23[1];
16459 uint32_t unused24[48];
16467 uint32_t unused25[2];
16475 uint32_t unused26[2];
16485 uint32_t unused27[3];
16491 uint32_t unused28[6];
16499 uint32_t unused29[2];
16504 uint32_t unused30[280];
16506 uint32_t unused31[3];
16521 enum class access_type_t : uint8_t
16542 CONFIG = 268435456;
16549 for (
size_t i = 0; i < (
sizeof(BASEP) /
sizeof(BASEP[0])); ++i)
16575 OFM_CBLK_WIDTH_M1 = 0;
16576 OFM_CBLK_HEIGHT_M1 = 0;
16577 OFM_CBLK_DEPTH_M1 = 0;
16578 IFM_CBLK_DEPTH_M1 = 0;
16585 IFM_CBLK_WIDTH = 0;
16586 IFM_CBLK_HEIGHT = 0;
16591 DMA_WEIGHT_SRC = 0;
16601 for (
size_t i = 0; i < (
sizeof(PMEVCNTR) /
sizeof(PMEVCNTR[0])); ++i)
16603 for (
size_t i = 0; i < (
sizeof(PMEVTYPER) /
sizeof(PMEVTYPER[0])); ++i)
16605 for (
size_t i = 0; i < (
sizeof(SHARED_BUFFER) /
sizeof(SHARED_BUFFER[0])); ++i)
16606 SHARED_BUFFER[i] = 0;
16610 IFM_PAD_BOTTOM = 0;
16614 IFM_ZERO_POINT = 0;
16616 IFM_HEIGHT0_M1 = 0;
16617 IFM_HEIGHT1_M1 = 0;
16624 OFM_BLK_WIDTH_M1 = 0;
16625 OFM_BLK_HEIGHT_M1 = 0;
16626 OFM_BLK_DEPTH_M1 = 0;
16627 OFM_ZERO_POINT = 0;
16629 OFM_HEIGHT0_M1 = 0;
16630 OFM_HEIGHT1_M1 = 0;
16632 KERNEL_WIDTH_M1 = 0;
16633 KERNEL_HEIGHT_M1 = 0;
16638 ACTIVATION_MIN = 0;
16639 ACTIVATION_MAX = 0;
16644 DMA0_SRC_REGION = 0;
16645 DMA0_DST_REGION = 0;
16648 IFM2_BROADCAST = 0;
16650 IFM2_PRECISION = 0;
16651 IFM2_ZERO_POINT = 0;
16652 IFM2_WIDTH0_M1 = 0;
16653 IFM2_HEIGHT0_M1 = 0;
16654 IFM2_HEIGHT1_M1 = 0;
16676 OFM_SCALE_SHIFT = 0;
16678 OPA_SCALE_SHIFT = 0;
16693 WEIGHT1_LENGTH = 0;
16710 uint32_t &operator[](
const int addr_offset)
16712 return reinterpret_cast<uint32_t *
>(
this)[addr_offset / 4];
16714 access_type_t get_access_type(uint32_t
offset)
16719 return access_type_t::RO;
16721 return access_type_t::RO;
16723 return access_type_t::RW;
16725 return access_type_t::RW;
16727 return access_type_t::RW;
16729 return access_type_t::RO;
16731 return access_type_t::RW;
16733 return access_type_t::RW;
16735 return access_type_t::RO;
16737 return access_type_t::RO;
16739 return access_type_t::RW;
16741 return access_type_t::RW;
16743 return access_type_t::RW;
16745 return access_type_t::RW;
16747 return access_type_t::RW;
16749 return access_type_t::RW;
16751 return access_type_t::RW;
16753 return access_type_t::RW;
16755 return access_type_t::RW;
16757 return access_type_t::RW;
16759 return access_type_t::RW;
16761 return access_type_t::RW;
16763 return access_type_t::RW;
16765 return access_type_t::RW;
16767 return access_type_t::RO;
16769 return access_type_t::RO;
16771 return access_type_t::RO;
16773 return access_type_t::RO;
16775 return access_type_t::RO;
16777 return access_type_t::RW;
16779 return access_type_t::RW;
16781 return access_type_t::RW;
16783 return access_type_t::RW;
16785 return access_type_t::RW;
16787 return access_type_t::RW;
16789 return access_type_t::RW;
16791 return access_type_t::RW;
16793 return access_type_t::RW;
16795 return access_type_t::RW;
16797 return access_type_t::RW;
16799 return access_type_t::RW;
16801 return access_type_t::RW;
16803 return access_type_t::RW;
16805 return access_type_t::RW;
16807 return access_type_t::RO;
16809 return access_type_t::RO;
16811 return access_type_t::RO;
16813 return access_type_t::RO;
16815 return access_type_t::RO;
16817 return access_type_t::RO;
16819 return access_type_t::RO;
16821 return access_type_t::RO;
16823 return access_type_t::RO;
16825 return access_type_t::RO;
16827 return access_type_t::RO;
16829 return access_type_t::RO;
16831 return access_type_t::RO;
16833 return access_type_t::RO;
16835 return access_type_t::RO;
16837 return access_type_t::RO;
16839 return access_type_t::RO;
16841 return access_type_t::RO;
16843 return access_type_t::RO;
16845 return access_type_t::RO;
16847 return access_type_t::RO;
16849 return access_type_t::RO;
16851 return access_type_t::RO;
16853 return access_type_t::RO;
16855 return access_type_t::RO;
16857 return access_type_t::RO;
16859 return access_type_t::RO;
16861 return access_type_t::RO;
16863 return access_type_t::RO;
16865 return access_type_t::RO;
16867 return access_type_t::RW;
16869 return access_type_t::RW;
16871 return access_type_t::RW;
16873 return access_type_t::RW;
16875 return access_type_t::RW;
16877 return access_type_t::RW;
16879 return access_type_t::RW;
16881 return access_type_t::RW;
16883 return access_type_t::RW;
16885 return access_type_t::RW;
16887 return access_type_t::RW;
16889 return access_type_t::RW;
16891 return access_type_t::RW;
16893 return access_type_t::RW;
16895 return access_type_t::RW;
16897 return access_type_t::RW;
16899 return access_type_t::RW;
16901 return access_type_t::RW;
16903 return access_type_t::RW;
16905 return access_type_t::RW;
16907 return access_type_t::RW;
16909 return access_type_t::RW;
16911 return access_type_t::RW;
16913 return access_type_t::RW;
16915 return access_type_t::RW;
16917 return access_type_t::RW;
16919 return access_type_t::RW;
16921 return access_type_t::RW;
16923 return access_type_t::RW;
16925 return access_type_t::RW;
16927 return access_type_t::RW;
16929 return access_type_t::RW;
16931 return access_type_t::RW;
16933 return access_type_t::RW;
16935 return access_type_t::RW;
16937 return access_type_t::RW;
16939 return access_type_t::RW;
16941 return access_type_t::RW;
16943 return access_type_t::RW;
16945 return access_type_t::RW;
16947 return access_type_t::RW;
16949 return access_type_t::RW;
16951 return access_type_t::RW;
16953 return access_type_t::RW;
16955 return access_type_t::RW;
16957 return access_type_t::RW;
16959 return access_type_t::RW;
16961 return access_type_t::RW;
16963 return access_type_t::RW;
16965 return access_type_t::RW;
16967 return access_type_t::RW;
16969 return access_type_t::RW;
16971 return access_type_t::RW;
16973 return access_type_t::RW;
16975 return access_type_t::RW;
16977 return access_type_t::RW;
16979 return access_type_t::RW;
16981 return access_type_t::RW;
16983 return access_type_t::RW;
16985 return access_type_t::RW;
16987 return access_type_t::RW;
16989 return access_type_t::RW;
16991 return access_type_t::RW;
16993 return access_type_t::RW;
16995 return access_type_t::RW;
16997 return access_type_t::RW;
16999 return access_type_t::RW;
17001 return access_type_t::RW;
17003 return access_type_t::RW;
17005 return access_type_t::RW;
17007 return access_type_t::RW;
17009 return access_type_t::RW;
17011 return access_type_t::RW;
17013 return access_type_t::RW;
17015 return access_type_t::RW;
17017 return access_type_t::RW;
17019 return access_type_t::RW;
17021 return access_type_t::RW;
17023 return access_type_t::RW;
17025 return access_type_t::RW;
17027 return access_type_t::RW;
17029 return access_type_t::RW;
17031 return access_type_t::RW;
17033 return access_type_t::RW;
17035 return access_type_t::RW;
17037 return access_type_t::RW;
17039 return access_type_t::RW;
17041 return access_type_t::RW;
17043 return access_type_t::RW;
17045 return access_type_t::RW;
17047 return access_type_t::RW;
17049 return access_type_t::RW;
17051 return access_type_t::RW;
17053 return access_type_t::RW;
17055 return access_type_t::RW;
17057 return access_type_t::RW;
17059 return access_type_t::RW;
17061 return access_type_t::RW;
17063 return access_type_t::RW;
17065 return access_type_t::RW;
17067 return access_type_t::RW;
17069 return access_type_t::RW;
17071 return access_type_t::RW;
17073 return access_type_t::RW;
17075 return access_type_t::RW;
17077 return access_type_t::RW;
17079 return access_type_t::RW;
17081 return access_type_t::RW;
17083 return access_type_t::RW;
17085 return access_type_t::RW;
17087 return access_type_t::RW;
17089 return access_type_t::RW;
17091 return access_type_t::RW;
17093 return access_type_t::RW;
17095 return access_type_t::RW;
17097 return access_type_t::RW;
17099 return access_type_t::RW;
17101 return access_type_t::RW;
17103 return access_type_t::RW;
17105 return access_type_t::RW;
17107 return access_type_t::RW;
17109 return access_type_t::RW;
17111 return access_type_t::RW;
17113 return access_type_t::RW;
17115 return access_type_t::RW;
17117 return access_type_t::RW;
17119 return access_type_t::RW;
17121 return access_type_t::RW;
17123 return access_type_t::RW;
17125 return access_type_t::RW;
17127 return access_type_t::RW;
17129 return access_type_t::RW;
17131 return access_type_t::RW;
17133 return access_type_t::RW;
17135 return access_type_t::RW;
17137 return access_type_t::RW;
17139 return access_type_t::RW;
17141 return access_type_t::RW;
17143 return access_type_t::RW;
17145 return access_type_t::RW;
17147 return access_type_t::RW;
17149 return access_type_t::RW;
17151 return access_type_t::RW;
17153 return access_type_t::RW;
17155 return access_type_t::RW;
17157 return access_type_t::RW;
17159 return access_type_t::RW;
17161 return access_type_t::RW;
17163 return access_type_t::RW;
17165 return access_type_t::RW;
17167 return access_type_t::RW;
17169 return access_type_t::RW;
17171 return access_type_t::RW;
17173 return access_type_t::RW;
17175 return access_type_t::RW;
17177 return access_type_t::RW;
17179 return access_type_t::RW;
17181 return access_type_t::RW;
17183 return access_type_t::RW;
17185 return access_type_t::RW;
17187 return access_type_t::RW;
17189 return access_type_t::RW;
17191 return access_type_t::RW;
17193 return access_type_t::RW;
17195 return access_type_t::RW;
17197 return access_type_t::RW;
17199 return access_type_t::RW;
17201 return access_type_t::RW;
17203 return access_type_t::RW;
17205 return access_type_t::RW;
17207 return access_type_t::RW;
17209 return access_type_t::RW;
17211 return access_type_t::RW;
17213 return access_type_t::RW;
17215 return access_type_t::RW;
17217 return access_type_t::RW;
17219 return access_type_t::RW;
17221 return access_type_t::RW;
17223 return access_type_t::RW;
17225 return access_type_t::RW;
17227 return access_type_t::RW;
17229 return access_type_t::RW;
17231 return access_type_t::RW;
17233 return access_type_t::RW;
17235 return access_type_t::RW;
17237 return access_type_t::RW;
17239 return access_type_t::RW;
17241 return access_type_t::RW;
17243 return access_type_t::RW;
17245 return access_type_t::RW;
17247 return access_type_t::RW;
17249 return access_type_t::RW;
17251 return access_type_t::RW;
17253 return access_type_t::RW;
17255 return access_type_t::RW;
17257 return access_type_t::RW;
17259 return access_type_t::RW;
17261 return access_type_t::RW;
17263 return access_type_t::RW;
17265 return access_type_t::RW;
17267 return access_type_t::RW;
17269 return access_type_t::RW;
17271 return access_type_t::RW;
17273 return access_type_t::RW;
17275 return access_type_t::RW;
17277 return access_type_t::RW;
17279 return access_type_t::RW;
17281 return access_type_t::RW;
17283 return access_type_t::RW;
17285 return access_type_t::RW;
17287 return access_type_t::RW;
17289 return access_type_t::RW;
17291 return access_type_t::RW;
17293 return access_type_t::RW;
17295 return access_type_t::RW;
17297 return access_type_t::RW;
17299 return access_type_t::RW;
17301 return access_type_t::RW;
17303 return access_type_t::RW;
17305 return access_type_t::RW;
17307 return access_type_t::RW;
17309 return access_type_t::RW;
17311 return access_type_t::RW;
17313 return access_type_t::RW;
17315 return access_type_t::RW;
17317 return access_type_t::RW;
17319 return access_type_t::RW;
17321 return access_type_t::RW;
17323 return access_type_t::RW;
17325 return access_type_t::RW;
17327 return access_type_t::RW;
17329 return access_type_t::RW;
17331 return access_type_t::RW;
17333 return access_type_t::RW;
17335 return access_type_t::RW;
17337 return access_type_t::RW;
17339 return access_type_t::RW;
17341 return access_type_t::RW;
17343 return access_type_t::RW;
17345 return access_type_t::RW;
17347 return access_type_t::RW;
17349 return access_type_t::RW;
17351 return access_type_t::RW;
17353 return access_type_t::RW;
17355 return access_type_t::RW;
17357 return access_type_t::RW;
17359 return access_type_t::RW;
17361 return access_type_t::RW;
17363 return access_type_t::RW;
17365 return access_type_t::RW;
17367 return access_type_t::RW;
17369 return access_type_t::RW;
17371 return access_type_t::RW;
17373 return access_type_t::RW;
17375 return access_type_t::RW;
17377 return access_type_t::RW;
17379 return access_type_t::RW;
17381 return access_type_t::RW;
17383 return access_type_t::RW;
17385 return access_type_t::RW;
17387 return access_type_t::RW;
17389 return access_type_t::RW;
17391 return access_type_t::RW;
17393 return access_type_t::RW;
17395 return access_type_t::RW;
17397 return access_type_t::RW;
17399 return access_type_t::RW;
17401 return access_type_t::RW;
17403 return access_type_t::RW;
17405 return access_type_t::RW;
17407 return access_type_t::RW;
17409 return access_type_t::RW;
17411 return access_type_t::RW;
17413 return access_type_t::RW;
17415 return access_type_t::RW;
17417 return access_type_t::RW;
17419 return access_type_t::RW;
17421 return access_type_t::RW;
17423 return access_type_t::RW;
17425 return access_type_t::RW;
17427 return access_type_t::RW;
17429 return access_type_t::RW;
17431 return access_type_t::RW;
17433 return access_type_t::RW;
17435 return access_type_t::RW;
17437 return access_type_t::RW;
17439 return access_type_t::RW;
17441 return access_type_t::RW;
17443 return access_type_t::RW;
17445 return access_type_t::RW;
17447 return access_type_t::RW;
17449 return access_type_t::RW;
17451 return access_type_t::RW;
17453 return access_type_t::RW;
17455 return access_type_t::RW;
17457 return access_type_t::RW;
17459 return access_type_t::RW;
17461 return access_type_t::RW;
17463 return access_type_t::RW;
17465 return access_type_t::RW;
17467 return access_type_t::RW;
17469 return access_type_t::RW;
17471 return access_type_t::RW;
17473 return access_type_t::RW;
17475 return access_type_t::RW;
17477 return access_type_t::RW;
17479 return access_type_t::RW;
17481 return access_type_t::RW;
17483 return access_type_t::RW;
17485 return access_type_t::RW;
17487 return access_type_t::RW;
17489 return access_type_t::RW;
17491 return access_type_t::RW;
17493 return access_type_t::RW;
17495 return access_type_t::RW;
17497 return access_type_t::RW;
17499 return access_type_t::RW;
17501 return access_type_t::RW;
17503 return access_type_t::RW;
17505 return access_type_t::RW;
17507 return access_type_t::RW;
17509 return access_type_t::RW;
17511 return access_type_t::RW;
17513 return access_type_t::RW;
17515 return access_type_t::RW;
17517 return access_type_t::RW;
17519 return access_type_t::RW;
17521 return access_type_t::RW;
17523 return access_type_t::RW;
17525 return access_type_t::RW;
17527 return access_type_t::RW;
17529 return access_type_t::RW;
17531 return access_type_t::RW;
17533 return access_type_t::RW;
17535 return access_type_t::RW;
17537 return access_type_t::RW;
17539 return access_type_t::RW;
17541 return access_type_t::RW;
17543 return access_type_t::RW;
17545 return access_type_t::RW;
17547 return access_type_t::RW;
17549 return access_type_t::RW;
17551 return access_type_t::RW;
17553 return access_type_t::RW;
17555 return access_type_t::RW;
17557 return access_type_t::RW;
17559 return access_type_t::RW;
17561 return access_type_t::RW;
17563 return access_type_t::RW;
17565 return access_type_t::RW;
17567 return access_type_t::RW;
17569 return access_type_t::RW;
17571 return access_type_t::RW;
17573 return access_type_t::RO;
17575 return access_type_t::RO;
17577 return access_type_t::RO;
17579 return access_type_t::RO;
17581 return access_type_t::RO;
17583 return access_type_t::RO;
17585 return access_type_t::RO;
17587 return access_type_t::RO;
17589 return access_type_t::RO;
17591 return access_type_t::RO;
17593 return access_type_t::RO;
17595 return access_type_t::RO;
17597 return access_type_t::RO;
17599 return access_type_t::RO;
17608#ifdef NPU_DISASSEMBLE
17609 static int disassemble(
const uint32_t *in,
17611 std::vector<std::pair<std::string, std::string>> &fields)
17613 switch (*in & 0xffff)
17615 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17616 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP):
17619 op =
"NPU_OP_STOP";
17620 v.disassemble(fields);
17623 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17624 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ):
17628 v.disassemble(fields);
17631 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17632 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV):
17635 op =
"NPU_OP_CONV";
17636 v.disassemble(fields);
17639 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17640 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE):
17643 op =
"NPU_OP_DEPTHWISE";
17644 v.disassemble(fields);
17647 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17648 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL):
17651 op =
"NPU_OP_POOL";
17652 v.disassemble(fields);
17655 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17656 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE):
17659 op =
"NPU_OP_ELEMENTWISE";
17660 v.disassemble(fields);
17663 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17664 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START):
17667 op =
"NPU_OP_DMA_START";
17668 v.disassemble(fields);
17671 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17672 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT):
17675 op =
"NPU_OP_DMA_WAIT";
17676 v.disassemble(fields);
17679 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17680 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT):
17683 op =
"NPU_OP_KERNEL_WAIT";
17684 v.disassemble(fields);
17687 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17688 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK):
17691 op =
"NPU_OP_PMU_MASK";
17692 v.disassemble(fields);
17695 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17696 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP):
17699 op =
"NPU_SET_IFM_PAD_TOP";
17700 v.disassemble(fields);
17703 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17704 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT):
17707 op =
"NPU_SET_IFM_PAD_LEFT";
17708 v.disassemble(fields);
17711 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17712 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT):
17715 op =
"NPU_SET_IFM_PAD_RIGHT";
17716 v.disassemble(fields);
17719 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17720 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM):
17723 op =
"NPU_SET_IFM_PAD_BOTTOM";
17724 v.disassemble(fields);
17727 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17728 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1):
17731 op =
"NPU_SET_IFM_DEPTH_M1";
17732 v.disassemble(fields);
17735 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17736 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION):
17739 op =
"NPU_SET_IFM_PRECISION";
17740 v.disassemble(fields);
17743 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17744 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE):
17747 op =
"NPU_SET_IFM_UPSCALE";
17748 v.disassemble(fields);
17751 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17752 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT):
17755 op =
"NPU_SET_IFM_ZERO_POINT";
17756 v.disassemble(fields);
17759 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17760 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1):
17763 op =
"NPU_SET_IFM_WIDTH0_M1";
17764 v.disassemble(fields);
17767 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17768 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1):
17771 op =
"NPU_SET_IFM_HEIGHT0_M1";
17772 v.disassemble(fields);
17775 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17776 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1):
17779 op =
"NPU_SET_IFM_HEIGHT1_M1";
17780 v.disassemble(fields);
17783 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17784 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END):
17787 op =
"NPU_SET_IFM_IB_END";
17788 v.disassemble(fields);
17791 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17792 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION):
17795 op =
"NPU_SET_IFM_REGION";
17796 v.disassemble(fields);
17799 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17800 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1):
17803 op =
"NPU_SET_OFM_WIDTH_M1";
17804 v.disassemble(fields);
17807 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17808 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1):
17811 op =
"NPU_SET_OFM_HEIGHT_M1";
17812 v.disassemble(fields);
17815 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17816 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1):
17819 op =
"NPU_SET_OFM_DEPTH_M1";
17820 v.disassemble(fields);
17823 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17824 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION):
17827 op =
"NPU_SET_OFM_PRECISION";
17828 v.disassemble(fields);
17831 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17832 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1):
17835 op =
"NPU_SET_OFM_BLK_WIDTH_M1";
17836 v.disassemble(fields);
17839 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17840 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1):
17843 op =
"NPU_SET_OFM_BLK_HEIGHT_M1";
17844 v.disassemble(fields);
17847 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17848 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1):
17851 op =
"NPU_SET_OFM_BLK_DEPTH_M1";
17852 v.disassemble(fields);
17855 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17856 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT):
17859 op =
"NPU_SET_OFM_ZERO_POINT";
17860 v.disassemble(fields);
17863 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17864 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1):
17867 op =
"NPU_SET_OFM_WIDTH0_M1";
17868 v.disassemble(fields);
17871 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17872 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1):
17875 op =
"NPU_SET_OFM_HEIGHT0_M1";
17876 v.disassemble(fields);
17879 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17880 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1):
17883 op =
"NPU_SET_OFM_HEIGHT1_M1";
17884 v.disassemble(fields);
17887 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17888 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION):
17891 op =
"NPU_SET_OFM_REGION";
17892 v.disassemble(fields);
17895 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17896 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1):
17899 op =
"NPU_SET_KERNEL_WIDTH_M1";
17900 v.disassemble(fields);
17903 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17904 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1):
17907 op =
"NPU_SET_KERNEL_HEIGHT_M1";
17908 v.disassemble(fields);
17911 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17912 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE):
17915 op =
"NPU_SET_KERNEL_STRIDE";
17916 v.disassemble(fields);
17919 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17920 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE):
17923 op =
"NPU_SET_PARALLEL_MODE";
17924 v.disassemble(fields);
17927 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17928 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT):
17931 op =
"NPU_SET_ACC_FORMAT";
17932 v.disassemble(fields);
17935 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17936 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION):
17939 op =
"NPU_SET_ACTIVATION";
17940 v.disassemble(fields);
17943 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17944 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN):
17947 op =
"NPU_SET_ACTIVATION_MIN";
17948 v.disassemble(fields);
17951 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17952 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX):
17955 op =
"NPU_SET_ACTIVATION_MAX";
17956 v.disassemble(fields);
17959 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17960 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION):
17963 op =
"NPU_SET_WEIGHT_REGION";
17964 v.disassemble(fields);
17967 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17968 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION):
17971 op =
"NPU_SET_SCALE_REGION";
17972 v.disassemble(fields);
17975 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17976 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START):
17979 op =
"NPU_SET_AB_START";
17980 v.disassemble(fields);
17983 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17984 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP):
17987 op =
"NPU_SET_BLOCKDEP";
17988 v.disassemble(fields);
17991 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
17992 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION):
17995 op =
"NPU_SET_DMA0_SRC_REGION";
17996 v.disassemble(fields);
17999 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18000 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION):
18003 op =
"NPU_SET_DMA0_DST_REGION";
18004 v.disassemble(fields);
18007 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18008 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0):
18011 op =
"NPU_SET_DMA0_SIZE0";
18012 v.disassemble(fields);
18015 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18016 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1):
18019 op =
"NPU_SET_DMA0_SIZE1";
18020 v.disassemble(fields);
18023 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18024 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST):
18027 op =
"NPU_SET_IFM2_BROADCAST";
18028 v.disassemble(fields);
18031 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18032 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR):
18035 op =
"NPU_SET_IFM2_SCALAR";
18036 v.disassemble(fields);
18039 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18040 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION):
18043 op =
"NPU_SET_IFM2_PRECISION";
18044 v.disassemble(fields);
18047 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18048 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT):
18051 op =
"NPU_SET_IFM2_ZERO_POINT";
18052 v.disassemble(fields);
18055 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18056 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1):
18059 op =
"NPU_SET_IFM2_WIDTH0_M1";
18060 v.disassemble(fields);
18063 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18064 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1):
18067 op =
"NPU_SET_IFM2_HEIGHT0_M1";
18068 v.disassemble(fields);
18071 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18072 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1):
18075 op =
"NPU_SET_IFM2_HEIGHT1_M1";
18076 v.disassemble(fields);
18079 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18080 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START):
18083 op =
"NPU_SET_IFM2_IB_START";
18084 v.disassemble(fields);
18087 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL) << 14) |
18088 static_cast<uint32_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION):
18091 op =
"NPU_SET_IFM2_REGION";
18092 v.disassemble(fields);
18095 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18096 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0):
18099 op =
"NPU_SET_IFM_BASE0";
18100 v.disassemble(fields);
18103 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18104 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1):
18107 op =
"NPU_SET_IFM_BASE1";
18108 v.disassemble(fields);
18111 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18112 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2):
18115 op =
"NPU_SET_IFM_BASE2";
18116 v.disassemble(fields);
18119 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18120 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3):
18123 op =
"NPU_SET_IFM_BASE3";
18124 v.disassemble(fields);
18127 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18128 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X):
18131 op =
"NPU_SET_IFM_STRIDE_X";
18132 v.disassemble(fields);
18135 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18136 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y):
18139 op =
"NPU_SET_IFM_STRIDE_Y";
18140 v.disassemble(fields);
18143 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18144 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C):
18147 op =
"NPU_SET_IFM_STRIDE_C";
18148 v.disassemble(fields);
18151 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18152 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0):
18155 op =
"NPU_SET_OFM_BASE0";
18156 v.disassemble(fields);
18159 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18160 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1):
18163 op =
"NPU_SET_OFM_BASE1";
18164 v.disassemble(fields);
18167 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18168 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2):
18171 op =
"NPU_SET_OFM_BASE2";
18172 v.disassemble(fields);
18175 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18176 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3):
18179 op =
"NPU_SET_OFM_BASE3";
18180 v.disassemble(fields);
18183 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18184 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X):
18187 op =
"NPU_SET_OFM_STRIDE_X";
18188 v.disassemble(fields);
18191 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18192 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y):
18195 op =
"NPU_SET_OFM_STRIDE_Y";
18196 v.disassemble(fields);
18199 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18200 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C):
18203 op =
"NPU_SET_OFM_STRIDE_C";
18204 v.disassemble(fields);
18207 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18208 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE):
18211 op =
"NPU_SET_WEIGHT_BASE";
18212 v.disassemble(fields);
18215 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18216 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH):
18219 op =
"NPU_SET_WEIGHT_LENGTH";
18220 v.disassemble(fields);
18223 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18224 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE):
18227 op =
"NPU_SET_SCALE_BASE";
18228 v.disassemble(fields);
18231 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18232 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH):
18235 op =
"NPU_SET_SCALE_LENGTH";
18236 v.disassemble(fields);
18239 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18240 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE):
18243 op =
"NPU_SET_OFM_SCALE";
18244 v.disassemble(fields);
18247 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18248 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE):
18251 op =
"NPU_SET_OPA_SCALE";
18252 v.disassemble(fields);
18255 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18256 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE):
18259 op =
"NPU_SET_OPB_SCALE";
18260 v.disassemble(fields);
18263 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18264 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC):
18267 op =
"NPU_SET_DMA0_SRC";
18268 v.disassemble(fields);
18271 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18272 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST):
18275 op =
"NPU_SET_DMA0_DST";
18276 v.disassemble(fields);
18279 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18280 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN):
18283 op =
"NPU_SET_DMA0_LEN";
18284 v.disassemble(fields);
18287 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18288 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0):
18291 op =
"NPU_SET_DMA0_SKIP0";
18292 v.disassemble(fields);
18295 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18296 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1):
18299 op =
"NPU_SET_DMA0_SKIP1";
18300 v.disassemble(fields);
18303 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18304 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0):
18307 op =
"NPU_SET_IFM2_BASE0";
18308 v.disassemble(fields);
18311 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18312 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1):
18315 op =
"NPU_SET_IFM2_BASE1";
18316 v.disassemble(fields);
18319 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18320 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2):
18323 op =
"NPU_SET_IFM2_BASE2";
18324 v.disassemble(fields);
18327 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18328 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3):
18331 op =
"NPU_SET_IFM2_BASE3";
18332 v.disassemble(fields);
18335 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18336 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X):
18339 op =
"NPU_SET_IFM2_STRIDE_X";
18340 v.disassemble(fields);
18343 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18344 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y):
18347 op =
"NPU_SET_IFM2_STRIDE_Y";
18348 v.disassemble(fields);
18351 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18352 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C):
18355 op =
"NPU_SET_IFM2_STRIDE_C";
18356 v.disassemble(fields);
18359 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18360 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE):
18363 op =
"NPU_SET_WEIGHT1_BASE";
18364 v.disassemble(fields);
18367 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18368 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH):
18371 op =
"NPU_SET_WEIGHT1_LENGTH";
18372 v.disassemble(fields);
18375 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18376 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE):
18379 op =
"NPU_SET_SCALE1_BASE";
18380 v.disassemble(fields);
18383 case (
static_cast<uint32_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL) << 14) |
18384 static_cast<uint32_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH):
18387 op =
"NPU_SET_SCALE1_LENGTH";
18388 v.disassemble(fields);
18392 return (*in & (3 << 14)) != 0 ? 2 : 1;
18402 uint32_t opcode : 10;
18403 uint32_t reserved0 : 4;
18404 uint32_t control : 2;
18405 uint32_t
mask : 16;
18409 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_STOP)), reserved0(0),
18410 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
mask(_mask & ((1U << 16) - 1))
18414 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_STOP)), reserved0(0),
18415 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
mask(0)
18420 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP) &&
18421 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18425 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_STOP);
18426 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18428 operator uint32_t()
18431 std::memcpy(&word,
this,
sizeof(word));
18434 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
18436 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
18440 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
18443 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
18445 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
18449 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
18454 return static_cast<uint32_t
>(
mask);
18458 mask =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
18461#ifdef NPU_DISASSEMBLE
18462 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
18464 fields.push_back(std::make_pair<std::string, std::string>(
"mask", std::to_string(
mask)));
18475 uint32_t opcode : 10;
18476 uint32_t reserved0 : 4;
18477 uint32_t control : 2;
18478 uint32_t
mask : 16;
18482 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_IRQ)), reserved0(0),
18483 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
mask(_mask & ((1U << 16) - 1))
18487 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_IRQ)), reserved0(0),
18488 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
mask(0)
18493 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ) &&
18494 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18498 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_IRQ);
18499 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18501 operator uint32_t()
18504 std::memcpy(&word,
this,
sizeof(word));
18507 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
18509 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
18513 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
18516 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
18518 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
18522 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
18527 return static_cast<uint32_t
>(
mask);
18531 mask =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
18534#ifdef NPU_DISASSEMBLE
18535 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
18537 fields.push_back(std::make_pair<std::string, std::string>(
"mask", std::to_string(
mask)));
18548 uint32_t opcode : 10;
18549 uint32_t reserved0 : 4;
18550 uint32_t control : 2;
18551 uint32_t reserved1 : 16;
18555 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_CONV)), reserved0(0),
18556 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), reserved1(0)
18561 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV) &&
18562 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18566 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_CONV);
18567 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18569 operator uint32_t()
18572 std::memcpy(&word,
this,
sizeof(word));
18575 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
18577 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
18581 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
18584 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
18586 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
18590 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
18593#ifdef NPU_DISASSEMBLE
18594 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const {}
18604 uint32_t opcode : 10;
18605 uint32_t reserved0 : 4;
18606 uint32_t control : 2;
18607 uint32_t reserved1 : 16;
18611 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_DEPTHWISE)), reserved0(0),
18612 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), reserved1(0)
18617 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE) &&
18618 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18622 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DEPTHWISE);
18623 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18625 operator uint32_t()
18628 std::memcpy(&word,
this,
sizeof(word));
18631 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
18633 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
18637 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
18640 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
18642 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
18646 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
18649#ifdef NPU_DISASSEMBLE
18650 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const {}
18660 uint32_t opcode : 10;
18661 uint32_t reserved0 : 4;
18662 uint32_t control : 2;
18664 uint32_t reserved1 : 13;
18668 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_POOL)), reserved0(0),
18669 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
18670 pooling_mode(static_cast<uint8_t>(_pooling_mode) & ((1U << 3) - 1)), reserved1(0)
18674 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_POOL)), reserved0(0),
18675 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
pooling_mode(0), reserved1(0)
18680 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL) &&
18681 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18685 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_POOL);
18686 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18688 operator uint32_t()
18691 std::memcpy(&word,
this,
sizeof(word));
18694 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
18696 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
18700 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
18703 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
18705 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
18709 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
18712 CONSTEXPR NPU_NAMESPACE::pooling_mode get_pooling_mode()
const
18714 return static_cast<NPU_NAMESPACE::pooling_mode
>(
pooling_mode);
18721#ifdef NPU_DISASSEMBLE
18722 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
18724 fields.push_back(std::make_pair<std::string, std::string>(
18726 (
pooling_mode < (
sizeof(pooling_mode_str) /
sizeof(pooling_mode_str[0])) ?
18739 uint32_t opcode : 10;
18740 uint32_t reserved0 : 4;
18741 uint32_t control : 2;
18743 uint32_t reserved1 : 10;
18747 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_ELEMENTWISE)), reserved0(0),
18748 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
18749 elementwise_mode(static_cast<uint8_t>(_elementwise_mode) & ((1U << 6) - 1)), reserved1(0)
18753 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_ELEMENTWISE)), reserved0(0),
18759 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE) &&
18760 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18764 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_ELEMENTWISE);
18765 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18767 operator uint32_t()
18770 std::memcpy(&word,
this,
sizeof(word));
18773 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
18775 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
18779 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
18782 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
18784 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
18788 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
18791 CONSTEXPR NPU_NAMESPACE::elementwise_mode get_elementwise_mode()
const
18800#ifdef NPU_DISASSEMBLE
18801 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
18803 fields.push_back(std::make_pair<std::string, std::string>(
18804 "elementwise_mode",
18805 (
elementwise_mode < (
sizeof(elementwise_mode_str) /
sizeof(elementwise_mode_str[0])) ?
18818 uint32_t opcode : 10;
18819 uint32_t reserved0 : 4;
18820 uint32_t control : 2;
18821 uint32_t reserved1 : 16;
18825 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_DMA_START)), reserved0(0),
18826 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), reserved1(0)
18831 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START) &&
18832 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18836 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_START);
18837 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18839 operator uint32_t()
18842 std::memcpy(&word,
this,
sizeof(word));
18845 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
18847 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
18851 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
18854 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
18856 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
18860 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
18863#ifdef NPU_DISASSEMBLE
18864 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const {}
18874 uint32_t opcode : 10;
18875 uint32_t reserved0 : 4;
18876 uint32_t control : 2;
18878 uint32_t reserved1 : 12;
18882 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_DMA_WAIT)), reserved0(0),
18883 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), k(_k & ((1U << 4) - 1)), reserved1(0)
18887 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_DMA_WAIT)), reserved0(0),
18888 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), k(0), reserved1(0)
18893 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT) &&
18894 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18898 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_DMA_WAIT);
18899 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18901 operator uint32_t()
18904 std::memcpy(&word,
this,
sizeof(word));
18907 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
18909 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
18913 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
18916 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
18918 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
18922 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
18927 return static_cast<uint32_t
>(k);
18931 k =
static_cast<uint8_t
>(
value) & ((1U << 4) - 1);
18934#ifdef NPU_DISASSEMBLE
18935 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
18937 fields.push_back(std::make_pair<std::string, std::string>(
"k", std::to_string(k)));
18948 uint32_t opcode : 10;
18949 uint32_t reserved0 : 4;
18950 uint32_t control : 2;
18952 uint32_t reserved1 : 14;
18956 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_KERNEL_WAIT)), reserved0(0),
18957 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), n(_n & ((1U << 2) - 1)), reserved1(0)
18961 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_KERNEL_WAIT)), reserved0(0),
18962 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), n(0), reserved1(0)
18967 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT) &&
18968 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18972 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_KERNEL_WAIT);
18973 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
18975 operator uint32_t()
18978 std::memcpy(&word,
this,
sizeof(word));
18981 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
18983 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
18987 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
18990 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
18992 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
18996 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19001 return static_cast<uint32_t
>(n);
19005 n =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19008#ifdef NPU_DISASSEMBLE
19009 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19011 fields.push_back(std::make_pair<std::string, std::string>(
"n", std::to_string(n)));
19022 uint32_t opcode : 10;
19023 uint32_t reserved0 : 4;
19024 uint32_t control : 2;
19025 uint32_t enable : 1;
19026 uint32_t reserved1 : 15;
19030 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_PMU_MASK)), reserved0(0),
19031 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), enable(_enable & ((1U << 1) - 1)),
19036 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_OP_PMU_MASK)), reserved0(0),
19037 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), enable(0), reserved1(0)
19042 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK) &&
19043 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19047 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_OP_PMU_MASK);
19048 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19050 operator uint32_t()
19053 std::memcpy(&word,
this,
sizeof(word));
19056 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19058 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19062 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19065 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19067 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19071 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19076 return static_cast<uint32_t
>(enable);
19080 enable =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
19083#ifdef NPU_DISASSEMBLE
19084 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19086 fields.push_back(std::make_pair<std::string, std::string>(
"enable", std::to_string(enable)));
19097 uint32_t opcode : 10;
19098 uint32_t reserved0 : 4;
19099 uint32_t control : 2;
19101 uint32_t reserved1 : 9;
19105 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_PAD_TOP)), reserved0(0),
19106 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 7) - 1)), reserved1(0)
19110 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_PAD_TOP)), reserved0(0),
19111 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19116 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP) &&
19117 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19121 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_TOP);
19122 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19124 operator uint32_t()
19127 std::memcpy(&word,
this,
sizeof(word));
19130 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19132 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19136 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19139 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19141 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19145 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19150 return static_cast<uint32_t
>(pad);
19154 pad =
static_cast<uint8_t
>(
value) & ((1U << 7) - 1);
19157#ifdef NPU_DISASSEMBLE
19158 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19160 fields.push_back(std::make_pair<std::string, std::string>(
"pad", std::to_string(pad)));
19171 uint32_t opcode : 10;
19172 uint32_t reserved0 : 4;
19173 uint32_t control : 2;
19175 uint32_t reserved1 : 9;
19179 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_PAD_LEFT)), reserved0(0),
19180 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 7) - 1)), reserved1(0)
19184 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_PAD_LEFT)), reserved0(0),
19185 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19190 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT) &&
19191 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19195 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_LEFT);
19196 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19198 operator uint32_t()
19201 std::memcpy(&word,
this,
sizeof(word));
19204 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19206 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19210 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19213 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19215 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19219 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19224 return static_cast<uint32_t
>(pad);
19228 pad =
static_cast<uint8_t
>(
value) & ((1U << 7) - 1);
19231#ifdef NPU_DISASSEMBLE
19232 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19234 fields.push_back(std::make_pair<std::string, std::string>(
"pad", std::to_string(pad)));
19245 uint32_t opcode : 10;
19246 uint32_t reserved0 : 4;
19247 uint32_t control : 2;
19249 uint32_t reserved1 : 8;
19253 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_PAD_RIGHT)), reserved0(0),
19254 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 8) - 1)), reserved1(0)
19258 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_PAD_RIGHT)), reserved0(0),
19259 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19264 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT) &&
19265 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19269 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_RIGHT);
19270 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19272 operator uint32_t()
19275 std::memcpy(&word,
this,
sizeof(word));
19278 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19280 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19284 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19287 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19289 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19293 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19298 return static_cast<uint32_t
>(pad);
19302 pad =
static_cast<uint8_t
>(
value) & ((1U << 8) - 1);
19305#ifdef NPU_DISASSEMBLE
19306 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19308 fields.push_back(std::make_pair<std::string, std::string>(
"pad", std::to_string(pad)));
19319 uint32_t opcode : 10;
19320 uint32_t reserved0 : 4;
19321 uint32_t control : 2;
19323 uint32_t reserved1 : 8;
19327 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM)), reserved0(0),
19328 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), pad(_pad & ((1U << 8) - 1)), reserved1(0)
19332 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM)), reserved0(0),
19333 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), pad(0), reserved1(0)
19338 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM) &&
19339 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19343 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PAD_BOTTOM);
19344 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19346 operator uint32_t()
19349 std::memcpy(&word,
this,
sizeof(word));
19352 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19354 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19358 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19361 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19363 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19367 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19372 return static_cast<uint32_t
>(pad);
19376 pad =
static_cast<uint8_t
>(
value) & ((1U << 8) - 1);
19379#ifdef NPU_DISASSEMBLE
19380 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19382 fields.push_back(std::make_pair<std::string, std::string>(
"pad", std::to_string(pad)));
19393 uint32_t opcode : 10;
19394 uint32_t reserved0 : 4;
19395 uint32_t control : 2;
19396 uint32_t depth_m1 : 16;
19400 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_DEPTH_M1)), reserved0(0),
19401 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 16) - 1))
19405 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_DEPTH_M1)), reserved0(0),
19406 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), depth_m1(0)
19411 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1) &&
19412 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19416 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_DEPTH_M1);
19417 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19419 operator uint32_t()
19422 std::memcpy(&word,
this,
sizeof(word));
19425 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19427 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19431 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19434 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19436 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19440 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19443 CONSTEXPR uint32_t get_depth_m1()
const
19445 return static_cast<uint32_t
>(depth_m1);
19449 depth_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
19452#ifdef NPU_DISASSEMBLE
19453 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19455 fields.push_back(std::make_pair<std::string, std::string>(
"depth_m1", std::to_string(depth_m1)));
19466 uint32_t opcode : 10;
19467 uint32_t reserved0 : 4;
19468 uint32_t control : 2;
19470 uint32_t reserved1 : 1;
19472 uint32_t reserved2 : 2;
19474 uint32_t scale_mode : 2;
19475 uint32_t reserved3 : 4;
19480 NPU_NAMESPACE::activation_precision _activation_precision,
19481 NPU_NAMESPACE::activation_format _activation_format,
19482 NPU_NAMESPACE::ifm_scale_mode _scale_mode,
19483 NPU_NAMESPACE::round_mode _round_mode) :
19484 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_PRECISION)),
19485 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
19486 activation_type(static_cast<uint8_t>(_activation_type) & ((1U << 1) - 1)), reserved1(0),
19487 activation_precision(static_cast<uint8_t>(_activation_precision) & ((1U << 2) - 1)), reserved2(0),
19489 scale_mode(static_cast<uint8_t>(_scale_mode) & ((1U << 2) - 1)), reserved3(0),
19490 round_mode(static_cast<uint8_t>(_round_mode) & ((1U << 2) - 1))
19494 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_PRECISION)), reserved0(0),
19501 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION) &&
19502 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19506 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_PRECISION);
19507 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19509 operator uint32_t()
19512 std::memcpy(&word,
this,
sizeof(word));
19515 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19517 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19521 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19524 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19526 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19530 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19533 CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type()
const
19542 CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision()
const
19551 CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format()
const
19560 CONSTEXPR NPU_NAMESPACE::ifm_scale_mode get_scale_mode()
const
19562 return static_cast<NPU_NAMESPACE::ifm_scale_mode
>(scale_mode);
19566 scale_mode =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19569 CONSTEXPR NPU_NAMESPACE::round_mode get_round_mode()
const
19571 return static_cast<NPU_NAMESPACE::round_mode
>(
round_mode);
19578#ifdef NPU_DISASSEMBLE
19579 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19581 fields.push_back(std::make_pair<std::string, std::string>(
19583 (
activation_type < (
sizeof(activation_type_str) /
sizeof(activation_type_str[0])) ?
19586 fields.push_back(std::make_pair<std::string, std::string>(
19587 "activation_precision",
19588 (
activation_precision < (
sizeof(activation_precision_str) /
sizeof(activation_precision_str[0])) ?
19591 fields.push_back(std::make_pair<std::string, std::string>(
19592 "activation_format",
19593 (
activation_format < (
sizeof(activation_format_str) /
sizeof(activation_format_str[0])) ?
19596 fields.push_back(std::make_pair<std::string, std::string>(
19598 (scale_mode < (
sizeof(ifm_scale_mode_str) /
sizeof(ifm_scale_mode_str[0])) ?
19599 ifm_scale_mode_str[scale_mode] :
19601 fields.push_back(std::make_pair<std::string, std::string>(
19603 (
round_mode < (
sizeof(round_mode_str) /
sizeof(round_mode_str[0])) ? round_mode_str[
round_mode] :
19615 uint32_t opcode : 10;
19616 uint32_t reserved0 : 4;
19617 uint32_t control : 2;
19619 uint32_t reserved1 : 14;
19623 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_UPSCALE)), reserved0(0),
19624 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
19625 mode(static_cast<uint8_t>(_mode) & ((1U << 2) - 1)), reserved1(0)
19629 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_UPSCALE)), reserved0(0),
19630 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), mode(0), reserved1(0)
19635 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE) &&
19636 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19640 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_UPSCALE);
19641 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19643 operator uint32_t()
19646 std::memcpy(&word,
this,
sizeof(word));
19649 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19651 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19655 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19658 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19660 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19664 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19667 CONSTEXPR NPU_NAMESPACE::ifm_upscale_mode get_mode()
const
19669 return static_cast<NPU_NAMESPACE::ifm_upscale_mode
>(mode);
19673 mode =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19676#ifdef NPU_DISASSEMBLE
19677 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19679 fields.push_back(std::make_pair<std::string, std::string>(
19681 (mode < (
sizeof(ifm_upscale_mode_str) /
sizeof(ifm_upscale_mode_str[0])) ? ifm_upscale_mode_str[mode] :
19693 uint32_t opcode : 10;
19694 uint32_t reserved0 : 4;
19695 uint32_t control : 2;
19700 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_ZERO_POINT)), reserved0(0),
19701 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
19706 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_ZERO_POINT)), reserved0(0),
19712 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT) &&
19713 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19717 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_ZERO_POINT);
19718 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19720 operator uint32_t()
19723 std::memcpy(&word,
this,
sizeof(word));
19726 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19728 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19732 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19735 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19737 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19741 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19744 CONSTEXPR uint32_t get_zero_point()
const
19753#ifdef NPU_DISASSEMBLE
19754 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19756 fields.push_back(std::make_pair<std::string, std::string>(
"zero_point", std::to_string(
zero_point)));
19767 uint32_t opcode : 10;
19768 uint32_t reserved0 : 4;
19769 uint32_t control : 2;
19770 uint32_t width_m1 : 16;
19774 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_WIDTH0_M1)), reserved0(0),
19775 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
19779 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_WIDTH0_M1)), reserved0(0),
19780 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(0)
19785 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1) &&
19786 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19790 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_WIDTH0_M1);
19791 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19793 operator uint32_t()
19796 std::memcpy(&word,
this,
sizeof(word));
19799 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19801 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19805 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19808 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19810 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19814 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19817 CONSTEXPR uint32_t get_width_m1()
const
19819 return static_cast<uint32_t
>(width_m1);
19823 width_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
19826#ifdef NPU_DISASSEMBLE
19827 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19829 fields.push_back(std::make_pair<std::string, std::string>(
"width_m1", std::to_string(width_m1)));
19840 uint32_t opcode : 10;
19841 uint32_t reserved0 : 4;
19842 uint32_t control : 2;
19843 uint32_t height_m1 : 16;
19847 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1)), reserved0(0),
19848 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
19852 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1)), reserved0(0),
19853 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(0)
19858 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1) &&
19859 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19863 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT0_M1);
19864 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19866 operator uint32_t()
19869 std::memcpy(&word,
this,
sizeof(word));
19872 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19874 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19878 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19881 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19883 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19887 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19890 CONSTEXPR uint32_t get_height_m1()
const
19892 return static_cast<uint32_t
>(height_m1);
19896 height_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
19899#ifdef NPU_DISASSEMBLE
19900 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19902 fields.push_back(std::make_pair<std::string, std::string>(
"height_m1", std::to_string(height_m1)));
19913 uint32_t opcode : 10;
19914 uint32_t reserved0 : 4;
19915 uint32_t control : 2;
19916 uint32_t height_m1 : 16;
19920 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1)), reserved0(0),
19921 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
19925 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1)), reserved0(0),
19926 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(0)
19931 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1) &&
19932 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19936 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_HEIGHT1_M1);
19937 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
19939 operator uint32_t()
19942 std::memcpy(&word,
this,
sizeof(word));
19945 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
19947 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
19951 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
19954 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
19956 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
19960 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
19963 CONSTEXPR uint32_t get_height_m1()
const
19965 return static_cast<uint32_t
>(height_m1);
19969 height_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
19972#ifdef NPU_DISASSEMBLE
19973 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
19975 fields.push_back(std::make_pair<std::string, std::string>(
"height_m1", std::to_string(height_m1)));
19986 uint32_t opcode : 10;
19987 uint32_t reserved0 : 4;
19988 uint32_t control : 2;
19989 uint32_t ib_end : 6;
19990 uint32_t reserved1 : 10;
19994 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_IB_END)), reserved0(0),
19995 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), ib_end(_ib_end & ((1U << 6) - 1)),
20000 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_IB_END)), reserved0(0),
20001 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), ib_end(0), reserved1(0)
20006 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END) &&
20007 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20011 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_IB_END);
20012 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20014 operator uint32_t()
20017 std::memcpy(&word,
this,
sizeof(word));
20020 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20022 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20026 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20029 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20031 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20035 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20040 return static_cast<uint32_t
>(ib_end);
20044 ib_end =
static_cast<uint8_t
>(
value) & ((1U << 6) - 1);
20047#ifdef NPU_DISASSEMBLE
20048 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20050 fields.push_back(std::make_pair<std::string, std::string>(
"ib_end", std::to_string(ib_end)));
20061 uint32_t opcode : 10;
20062 uint32_t reserved0 : 4;
20063 uint32_t control : 2;
20064 uint32_t region : 3;
20065 uint32_t reserved1 : 13;
20069 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_REGION)), reserved0(0),
20070 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
20075 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM_REGION)), reserved0(0),
20076 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
20081 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION) &&
20082 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20086 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM_REGION);
20087 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20089 operator uint32_t()
20092 std::memcpy(&word,
this,
sizeof(word));
20095 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20097 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20101 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20104 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20106 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20110 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20115 return static_cast<uint32_t
>(region);
20119 region =
static_cast<uint8_t
>(
value) & ((1U << 3) - 1);
20122#ifdef NPU_DISASSEMBLE
20123 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20125 fields.push_back(std::make_pair<std::string, std::string>(
"region", std::to_string(region)));
20136 uint32_t opcode : 10;
20137 uint32_t reserved0 : 4;
20138 uint32_t control : 2;
20139 uint32_t width_m1 : 16;
20143 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_WIDTH_M1)), reserved0(0),
20144 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
20148 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_WIDTH_M1)), reserved0(0),
20149 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(0)
20154 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1) &&
20155 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20159 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH_M1);
20160 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20162 operator uint32_t()
20165 std::memcpy(&word,
this,
sizeof(word));
20168 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20170 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20174 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20177 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20179 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20183 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20186 CONSTEXPR uint32_t get_width_m1()
const
20188 return static_cast<uint32_t
>(width_m1);
20192 width_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
20195#ifdef NPU_DISASSEMBLE
20196 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20198 fields.push_back(std::make_pair<std::string, std::string>(
"width_m1", std::to_string(width_m1)));
20209 uint32_t opcode : 10;
20210 uint32_t reserved0 : 4;
20211 uint32_t control : 2;
20212 uint32_t height_m1 : 16;
20216 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_HEIGHT_M1)), reserved0(0),
20217 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
20221 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_HEIGHT_M1)), reserved0(0),
20222 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(0)
20227 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1) &&
20228 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20232 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT_M1);
20233 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20235 operator uint32_t()
20238 std::memcpy(&word,
this,
sizeof(word));
20241 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20243 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20247 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20250 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20252 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20256 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20259 CONSTEXPR uint32_t get_height_m1()
const
20261 return static_cast<uint32_t
>(height_m1);
20265 height_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
20268#ifdef NPU_DISASSEMBLE
20269 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20271 fields.push_back(std::make_pair<std::string, std::string>(
"height_m1", std::to_string(height_m1)));
20282 uint32_t opcode : 10;
20283 uint32_t reserved0 : 4;
20284 uint32_t control : 2;
20285 uint32_t depth_m1 : 16;
20289 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_DEPTH_M1)), reserved0(0),
20290 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 16) - 1))
20294 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_DEPTH_M1)), reserved0(0),
20295 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), depth_m1(0)
20300 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1) &&
20301 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20305 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_DEPTH_M1);
20306 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20308 operator uint32_t()
20311 std::memcpy(&word,
this,
sizeof(word));
20314 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20316 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20320 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20323 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20325 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20329 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20332 CONSTEXPR uint32_t get_depth_m1()
const
20334 return static_cast<uint32_t
>(depth_m1);
20338 depth_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
20341#ifdef NPU_DISASSEMBLE
20342 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20344 fields.push_back(std::make_pair<std::string, std::string>(
"depth_m1", std::to_string(depth_m1)));
20355 uint32_t opcode : 10;
20356 uint32_t reserved0 : 4;
20357 uint32_t control : 2;
20360 uint32_t reserved1 : 3;
20362 uint32_t scale_mode : 1;
20363 uint32_t reserved2 : 5;
20368 NPU_NAMESPACE::activation_precision _activation_precision,
20369 NPU_NAMESPACE::activation_format _activation_format,
20370 NPU_NAMESPACE::ofm_scale_mode _scale_mode,
20371 NPU_NAMESPACE::round_mode _round_mode) :
20372 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_PRECISION)),
20373 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
20374 activation_type(static_cast<uint8_t>(_activation_type) & ((1U << 1) - 1)),
20375 activation_precision(static_cast<uint8_t>(_activation_precision) & ((1U << 2) - 1)), reserved1(0),
20377 scale_mode(static_cast<uint8_t>(_scale_mode) & ((1U << 1) - 1)), reserved2(0),
20378 round_mode(static_cast<uint8_t>(_round_mode) & ((1U << 2) - 1))
20382 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_PRECISION)), reserved0(0),
20389 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION) &&
20390 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20394 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_PRECISION);
20395 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20397 operator uint32_t()
20400 std::memcpy(&word,
this,
sizeof(word));
20403 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20405 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20409 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20412 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20414 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20418 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20421 CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type()
const
20430 CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision()
const
20439 CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format()
const
20448 CONSTEXPR NPU_NAMESPACE::ofm_scale_mode get_scale_mode()
const
20450 return static_cast<NPU_NAMESPACE::ofm_scale_mode
>(scale_mode);
20454 scale_mode =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
20457 CONSTEXPR NPU_NAMESPACE::round_mode get_round_mode()
const
20459 return static_cast<NPU_NAMESPACE::round_mode
>(
round_mode);
20466#ifdef NPU_DISASSEMBLE
20467 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20469 fields.push_back(std::make_pair<std::string, std::string>(
20471 (
activation_type < (
sizeof(activation_type_str) /
sizeof(activation_type_str[0])) ?
20474 fields.push_back(std::make_pair<std::string, std::string>(
20475 "activation_precision",
20476 (
activation_precision < (
sizeof(activation_precision_str) /
sizeof(activation_precision_str[0])) ?
20479 fields.push_back(std::make_pair<std::string, std::string>(
20480 "activation_format",
20481 (
activation_format < (
sizeof(activation_format_str) /
sizeof(activation_format_str[0])) ?
20484 fields.push_back(std::make_pair<std::string, std::string>(
20486 (scale_mode < (
sizeof(ofm_scale_mode_str) /
sizeof(ofm_scale_mode_str[0])) ?
20487 ofm_scale_mode_str[scale_mode] :
20489 fields.push_back(std::make_pair<std::string, std::string>(
20491 (
round_mode < (
sizeof(round_mode_str) /
sizeof(round_mode_str[0])) ? round_mode_str[
round_mode] :
20503 uint32_t opcode : 10;
20504 uint32_t reserved0 : 4;
20505 uint32_t control : 2;
20506 uint32_t width_m1 : 6;
20507 uint32_t reserved1 : 10;
20511 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1)), reserved0(0),
20512 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 6) - 1)),
20517 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1)), reserved0(0),
20518 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(0), reserved1(0)
20523 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1) &&
20524 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20528 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_WIDTH_M1);
20529 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20531 operator uint32_t()
20534 std::memcpy(&word,
this,
sizeof(word));
20537 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20539 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20543 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20546 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20548 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20552 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20555 CONSTEXPR uint32_t get_width_m1()
const
20557 return static_cast<uint32_t
>(width_m1);
20561 width_m1 =
static_cast<uint8_t
>(
value) & ((1U << 6) - 1);
20564#ifdef NPU_DISASSEMBLE
20565 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20567 fields.push_back(std::make_pair<std::string, std::string>(
"width_m1", std::to_string(width_m1)));
20578 uint32_t opcode : 10;
20579 uint32_t reserved0 : 4;
20580 uint32_t control : 2;
20581 uint32_t height_m1 : 5;
20582 uint32_t reserved1 : 11;
20586 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1)), reserved0(0),
20587 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 5) - 1)),
20592 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1)), reserved0(0),
20593 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(0), reserved1(0)
20598 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1) &&
20599 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20603 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_HEIGHT_M1);
20604 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20606 operator uint32_t()
20609 std::memcpy(&word,
this,
sizeof(word));
20612 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20614 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20618 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20621 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20623 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20627 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20630 CONSTEXPR uint32_t get_height_m1()
const
20632 return static_cast<uint32_t
>(height_m1);
20636 height_m1 =
static_cast<uint8_t
>(
value) & ((1U << 5) - 1);
20639#ifdef NPU_DISASSEMBLE
20640 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20642 fields.push_back(std::make_pair<std::string, std::string>(
"height_m1", std::to_string(height_m1)));
20653 uint32_t opcode : 10;
20654 uint32_t reserved0 : 4;
20655 uint32_t control : 2;
20656 uint32_t depth_m1 : 7;
20657 uint32_t reserved1 : 9;
20661 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1)), reserved0(0),
20662 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), depth_m1(_depth_m1 & ((1U << 7) - 1)),
20667 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1)), reserved0(0),
20668 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), depth_m1(0), reserved1(0)
20673 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1) &&
20674 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20678 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_BLK_DEPTH_M1);
20679 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20681 operator uint32_t()
20684 std::memcpy(&word,
this,
sizeof(word));
20687 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20689 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20693 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20696 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20698 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20702 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20705 CONSTEXPR uint32_t get_depth_m1()
const
20707 return static_cast<uint32_t
>(depth_m1);
20711 depth_m1 =
static_cast<uint8_t
>(
value) & ((1U << 7) - 1);
20714#ifdef NPU_DISASSEMBLE
20715 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20717 fields.push_back(std::make_pair<std::string, std::string>(
"depth_m1", std::to_string(depth_m1)));
20728 uint32_t opcode : 10;
20729 uint32_t reserved0 : 4;
20730 uint32_t control : 2;
20735 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_ZERO_POINT)), reserved0(0),
20736 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
20741 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_ZERO_POINT)), reserved0(0),
20747 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT) &&
20748 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20752 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_ZERO_POINT);
20753 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20755 operator uint32_t()
20758 std::memcpy(&word,
this,
sizeof(word));
20761 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20763 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20767 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20770 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20772 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20776 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20779 CONSTEXPR uint32_t get_zero_point()
const
20788#ifdef NPU_DISASSEMBLE
20789 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20791 fields.push_back(std::make_pair<std::string, std::string>(
"zero_point", std::to_string(
zero_point)));
20802 uint32_t opcode : 10;
20803 uint32_t reserved0 : 4;
20804 uint32_t control : 2;
20805 uint32_t width_m1 : 16;
20809 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_WIDTH0_M1)), reserved0(0),
20810 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
20814 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_WIDTH0_M1)), reserved0(0),
20815 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(0)
20820 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1) &&
20821 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20825 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_WIDTH0_M1);
20826 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20828 operator uint32_t()
20831 std::memcpy(&word,
this,
sizeof(word));
20834 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20836 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20840 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20843 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20845 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20849 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20852 CONSTEXPR uint32_t get_width_m1()
const
20854 return static_cast<uint32_t
>(width_m1);
20858 width_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
20861#ifdef NPU_DISASSEMBLE
20862 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20864 fields.push_back(std::make_pair<std::string, std::string>(
"width_m1", std::to_string(width_m1)));
20875 uint32_t opcode : 10;
20876 uint32_t reserved0 : 4;
20877 uint32_t control : 2;
20878 uint32_t height_m1 : 16;
20882 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1)), reserved0(0),
20883 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
20887 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1)), reserved0(0),
20888 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(0)
20893 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1) &&
20894 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20898 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT0_M1);
20899 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20901 operator uint32_t()
20904 std::memcpy(&word,
this,
sizeof(word));
20907 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20909 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20913 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20916 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20918 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20922 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20925 CONSTEXPR uint32_t get_height_m1()
const
20927 return static_cast<uint32_t
>(height_m1);
20931 height_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
20934#ifdef NPU_DISASSEMBLE
20935 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
20937 fields.push_back(std::make_pair<std::string, std::string>(
"height_m1", std::to_string(height_m1)));
20948 uint32_t opcode : 10;
20949 uint32_t reserved0 : 4;
20950 uint32_t control : 2;
20951 uint32_t height_m1 : 16;
20955 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1)), reserved0(0),
20956 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
20960 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1)), reserved0(0),
20961 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(0)
20966 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1) &&
20967 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20971 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_HEIGHT1_M1);
20972 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
20974 operator uint32_t()
20977 std::memcpy(&word,
this,
sizeof(word));
20980 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
20982 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
20986 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
20989 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
20991 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
20995 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
20998 CONSTEXPR uint32_t get_height_m1()
const
21000 return static_cast<uint32_t
>(height_m1);
21004 height_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
21007#ifdef NPU_DISASSEMBLE
21008 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21010 fields.push_back(std::make_pair<std::string, std::string>(
"height_m1", std::to_string(height_m1)));
21021 uint32_t opcode : 10;
21022 uint32_t reserved0 : 4;
21023 uint32_t control : 2;
21024 uint32_t region : 3;
21025 uint32_t reserved1 : 13;
21029 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_REGION)), reserved0(0),
21030 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
21035 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_OFM_REGION)), reserved0(0),
21036 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
21041 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION) &&
21042 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21046 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_OFM_REGION);
21047 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21049 operator uint32_t()
21052 std::memcpy(&word,
this,
sizeof(word));
21055 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21057 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21061 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21064 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21066 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21070 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21075 return static_cast<uint32_t
>(region);
21079 region =
static_cast<uint8_t
>(
value) & ((1U << 3) - 1);
21082#ifdef NPU_DISASSEMBLE
21083 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21085 fields.push_back(std::make_pair<std::string, std::string>(
"region", std::to_string(region)));
21096 uint32_t opcode : 10;
21097 uint32_t reserved0 : 4;
21098 uint32_t control : 2;
21099 uint32_t width_m1 : 16;
21103 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1)), reserved0(0),
21104 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
21108 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1)), reserved0(0),
21109 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(0)
21114 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1) &&
21115 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21119 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_WIDTH_M1);
21120 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21122 operator uint32_t()
21125 std::memcpy(&word,
this,
sizeof(word));
21128 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21130 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21134 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21137 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21139 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21143 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21146 CONSTEXPR uint32_t get_width_m1()
const
21148 return static_cast<uint32_t
>(width_m1);
21152 width_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
21155#ifdef NPU_DISASSEMBLE
21156 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21158 fields.push_back(std::make_pair<std::string, std::string>(
"width_m1", std::to_string(width_m1)));
21169 uint32_t opcode : 10;
21170 uint32_t reserved0 : 4;
21171 uint32_t control : 2;
21172 uint32_t height_m1 : 16;
21176 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1)), reserved0(0),
21177 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
21181 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1)), reserved0(0),
21182 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(0)
21187 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1) &&
21188 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21192 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_HEIGHT_M1);
21193 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21195 operator uint32_t()
21198 std::memcpy(&word,
this,
sizeof(word));
21201 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21203 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21207 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21210 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21212 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21216 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21219 CONSTEXPR uint32_t get_height_m1()
const
21221 return static_cast<uint32_t
>(height_m1);
21225 height_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
21228#ifdef NPU_DISASSEMBLE
21229 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21231 fields.push_back(std::make_pair<std::string, std::string>(
"height_m1", std::to_string(height_m1)));
21242 uint32_t opcode : 10;
21243 uint32_t reserved0 : 4;
21244 uint32_t control : 2;
21245 uint32_t stride_x_lsb : 1;
21246 uint32_t stride_y_lsb : 1;
21248 uint32_t dilation_x : 1;
21249 uint32_t dilation_y : 1;
21250 uint32_t decomposition : 1;
21251 uint32_t stride_x_msb : 1;
21252 uint32_t reserved1 : 2;
21253 uint32_t stride_y_msb : 1;
21254 uint32_t reserved2 : 6;
21258 uint32_t _stride_y_lsb,
21259 NPU_NAMESPACE::weight_order _weight_order,
21260 NPU_NAMESPACE::kernel_dilation _dilation_x,
21261 NPU_NAMESPACE::kernel_dilation _dilation_y,
21262 NPU_NAMESPACE::kernel_decomposition _decomposition,
21263 uint32_t _stride_x_msb,
21264 uint32_t _stride_y_msb) :
21265 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_KERNEL_STRIDE)),
21266 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
21267 stride_x_lsb(_stride_x_lsb & ((1U << 1) - 1)), stride_y_lsb(_stride_y_lsb & ((1U << 1) - 1)),
21268 weight_order(static_cast<uint8_t>(_weight_order) & ((1U << 1) - 1)),
21269 dilation_x(static_cast<uint8_t>(_dilation_x) & ((1U << 1) - 1)),
21270 dilation_y(static_cast<uint8_t>(_dilation_y) & ((1U << 1) - 1)),
21271 decomposition(static_cast<uint8_t>(_decomposition) & ((1U << 1) - 1)),
21272 stride_x_msb(_stride_x_msb & ((1U << 1) - 1)), reserved1(0), stride_y_msb(_stride_y_msb & ((1U << 1) - 1)),
21277 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_KERNEL_STRIDE)), reserved0(0),
21278 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), stride_x_lsb(0), stride_y_lsb(0),
21279 weight_order(0), dilation_x(0), dilation_y(0), decomposition(0), stride_x_msb(0), reserved1(0),
21280 stride_y_msb(0), reserved2(0)
21285 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE) &&
21286 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21290 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_KERNEL_STRIDE);
21291 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21293 operator uint32_t()
21296 std::memcpy(&word,
this,
sizeof(word));
21299 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21301 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21305 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21308 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21310 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21314 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21317 CONSTEXPR uint32_t get_stride_x_lsb()
const
21319 return static_cast<uint32_t
>(stride_x_lsb);
21323 stride_x_lsb =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
21326 CONSTEXPR uint32_t get_stride_y_lsb()
const
21328 return static_cast<uint32_t
>(stride_y_lsb);
21332 stride_y_lsb =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
21335 CONSTEXPR NPU_NAMESPACE::weight_order get_weight_order()
const
21337 return static_cast<NPU_NAMESPACE::weight_order
>(
weight_order);
21344 CONSTEXPR NPU_NAMESPACE::kernel_dilation get_dilation_x()
const
21346 return static_cast<NPU_NAMESPACE::kernel_dilation
>(dilation_x);
21350 dilation_x =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
21353 CONSTEXPR NPU_NAMESPACE::kernel_dilation get_dilation_y()
const
21355 return static_cast<NPU_NAMESPACE::kernel_dilation
>(dilation_y);
21359 dilation_y =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
21362 CONSTEXPR NPU_NAMESPACE::kernel_decomposition get_decomposition()
const
21364 return static_cast<NPU_NAMESPACE::kernel_decomposition
>(decomposition);
21368 decomposition =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
21371 CONSTEXPR uint32_t get_stride_x_msb()
const
21373 return static_cast<uint32_t
>(stride_x_msb);
21377 stride_x_msb =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
21380 CONSTEXPR uint32_t get_stride_y_msb()
const
21382 return static_cast<uint32_t
>(stride_y_msb);
21386 stride_y_msb =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
21389#ifdef NPU_DISASSEMBLE
21390 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21392 fields.push_back(std::make_pair<std::string, std::string>(
"stride_x_lsb", std::to_string(stride_x_lsb)));
21393 fields.push_back(std::make_pair<std::string, std::string>(
"stride_y_lsb", std::to_string(stride_y_lsb)));
21394 fields.push_back(std::make_pair<std::string, std::string>(
21396 (
weight_order < (
sizeof(weight_order_str) /
sizeof(weight_order_str[0])) ?
21399 fields.push_back(std::make_pair<std::string, std::string>(
21401 (dilation_x < (
sizeof(kernel_dilation_str) /
sizeof(kernel_dilation_str[0])) ?
21402 kernel_dilation_str[dilation_x] :
21404 fields.push_back(std::make_pair<std::string, std::string>(
21406 (dilation_y < (
sizeof(kernel_dilation_str) /
sizeof(kernel_dilation_str[0])) ?
21407 kernel_dilation_str[dilation_y] :
21409 fields.push_back(std::make_pair<std::string, std::string>(
21411 (decomposition < (
sizeof(kernel_decomposition_str) /
sizeof(kernel_decomposition_str[0])) ?
21412 kernel_decomposition_str[decomposition] :
21414 fields.push_back(std::make_pair<std::string, std::string>(
"stride_x_msb", std::to_string(stride_x_msb)));
21415 fields.push_back(std::make_pair<std::string, std::string>(
"stride_y_msb", std::to_string(stride_y_msb)));
21434 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_PARALLEL_MODE)), reserved0(0),
21435 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
21436 parallel_mode(static_cast<uint8_t>(_parallel_mode) & ((1U << 1) - 1)), reserved1(0)
21440 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_PARALLEL_MODE)), reserved0(0),
21446 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE) &&
21447 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21451 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_PARALLEL_MODE);
21452 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21454 operator uint32_t()
21457 std::memcpy(&word,
this,
sizeof(word));
21460 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21462 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21466 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21469 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21471 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21475 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21478 CONSTEXPR NPU_NAMESPACE::parallel_mode get_parallel_mode()
const
21480 return static_cast<NPU_NAMESPACE::parallel_mode
>(
parallel_mode);
21487#ifdef NPU_DISASSEMBLE
21488 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21490 fields.push_back(std::make_pair<std::string, std::string>(
21492 (
parallel_mode < (
sizeof(parallel_mode_str) /
sizeof(parallel_mode_str[0])) ?
21505 uint32_t opcode : 10;
21506 uint32_t reserved0 : 4;
21507 uint32_t control : 2;
21509 uint32_t reserved1 : 14;
21513 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_ACC_FORMAT)), reserved0(0),
21514 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
21515 acc_format(static_cast<uint8_t>(_acc_format) & ((1U << 2) - 1)), reserved1(0)
21519 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_ACC_FORMAT)), reserved0(0),
21520 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
acc_format(0), reserved1(0)
21525 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT) &&
21526 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21530 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACC_FORMAT);
21531 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21533 operator uint32_t()
21536 std::memcpy(&word,
this,
sizeof(word));
21539 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21541 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21545 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21548 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21550 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21554 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21557 CONSTEXPR NPU_NAMESPACE::acc_format get_acc_format()
const
21559 return static_cast<NPU_NAMESPACE::acc_format
>(
acc_format);
21566#ifdef NPU_DISASSEMBLE
21567 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21569 fields.push_back(std::make_pair<std::string, std::string>(
21571 (
acc_format < (
sizeof(acc_format_str) /
sizeof(acc_format_str[0])) ? acc_format_str[
acc_format] :
21583 uint32_t opcode : 10;
21584 uint32_t reserved0 : 4;
21585 uint32_t control : 2;
21587 uint32_t reserved1 : 7;
21589 uint32_t reserved2 : 1;
21593 NPU_NAMESPACE::activation_clip_range _activation_clip_range) :
21594 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_ACTIVATION)),
21595 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
21596 activation_function(static_cast<uint8_t>(_activation_function) & ((1U << 5) - 1)), reserved1(0),
21597 activation_clip_range(static_cast<uint8_t>(_activation_clip_range) & ((1U << 3) - 1)), reserved2(0)
21601 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_ACTIVATION)), reserved0(0),
21608 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION) &&
21609 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21613 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION);
21614 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21616 operator uint32_t()
21619 std::memcpy(&word,
this,
sizeof(word));
21622 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21624 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21628 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21631 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21633 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21637 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21640 CONSTEXPR NPU_NAMESPACE::activation_function get_activation_function()
const
21649 CONSTEXPR NPU_NAMESPACE::activation_clip_range get_activation_clip_range()
const
21658#ifdef NPU_DISASSEMBLE
21659 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21661 fields.push_back(std::make_pair<std::string, std::string>(
21662 "activation_function",
21663 (
activation_function < (
sizeof(activation_function_str) /
sizeof(activation_function_str[0])) ?
21666 fields.push_back(std::make_pair<std::string, std::string>(
21667 "activation_clip_range",
21668 (
activation_clip_range < (
sizeof(activation_clip_range_str) /
sizeof(activation_clip_range_str[0])) ?
21681 uint32_t opcode : 10;
21682 uint32_t reserved0 : 4;
21683 uint32_t control : 2;
21684 uint32_t clip_boundary : 16;
21688 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_ACTIVATION_MIN)), reserved0(0),
21689 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
21690 clip_boundary(_clip_boundary & ((1U << 16) - 1))
21694 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_ACTIVATION_MIN)), reserved0(0),
21695 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), clip_boundary(0)
21700 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN) &&
21701 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21705 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MIN);
21706 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21708 operator uint32_t()
21711 std::memcpy(&word,
this,
sizeof(word));
21714 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21716 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21720 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21723 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21725 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21729 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21732 CONSTEXPR uint32_t get_clip_boundary()
const
21734 return static_cast<uint32_t
>(clip_boundary);
21738 clip_boundary =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
21741#ifdef NPU_DISASSEMBLE
21742 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21744 fields.push_back(std::make_pair<std::string, std::string>(
"clip_boundary", std::to_string(clip_boundary)));
21755 uint32_t opcode : 10;
21756 uint32_t reserved0 : 4;
21757 uint32_t control : 2;
21758 uint32_t clip_boundary : 16;
21762 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_ACTIVATION_MAX)), reserved0(0),
21763 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
21764 clip_boundary(_clip_boundary & ((1U << 16) - 1))
21768 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_ACTIVATION_MAX)), reserved0(0),
21769 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), clip_boundary(0)
21774 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX) &&
21775 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21779 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_ACTIVATION_MAX);
21780 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21782 operator uint32_t()
21785 std::memcpy(&word,
this,
sizeof(word));
21788 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21790 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21794 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21797 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21799 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21803 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21806 CONSTEXPR uint32_t get_clip_boundary()
const
21808 return static_cast<uint32_t
>(clip_boundary);
21812 clip_boundary =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
21815#ifdef NPU_DISASSEMBLE
21816 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21818 fields.push_back(std::make_pair<std::string, std::string>(
"clip_boundary", std::to_string(clip_boundary)));
21829 uint32_t opcode : 10;
21830 uint32_t reserved0 : 4;
21831 uint32_t control : 2;
21832 uint32_t region : 3;
21833 uint32_t reserved1 : 13;
21837 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_WEIGHT_REGION)), reserved0(0),
21838 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
21843 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_WEIGHT_REGION)), reserved0(0),
21844 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
21849 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION) &&
21850 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21854 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_WEIGHT_REGION);
21855 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21857 operator uint32_t()
21860 std::memcpy(&word,
this,
sizeof(word));
21863 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21865 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21869 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21872 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21874 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21878 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21883 return static_cast<uint32_t
>(region);
21887 region =
static_cast<uint8_t
>(
value) & ((1U << 3) - 1);
21890#ifdef NPU_DISASSEMBLE
21891 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21893 fields.push_back(std::make_pair<std::string, std::string>(
"region", std::to_string(region)));
21904 uint32_t opcode : 10;
21905 uint32_t reserved0 : 4;
21906 uint32_t control : 2;
21907 uint32_t region : 3;
21908 uint32_t reserved1 : 13;
21912 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_SCALE_REGION)), reserved0(0),
21913 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
21918 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_SCALE_REGION)), reserved0(0),
21919 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
21924 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION) &&
21925 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21929 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_SCALE_REGION);
21930 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
21932 operator uint32_t()
21935 std::memcpy(&word,
this,
sizeof(word));
21938 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
21940 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
21944 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
21947 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
21949 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
21953 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
21958 return static_cast<uint32_t
>(region);
21962 region =
static_cast<uint8_t
>(
value) & ((1U << 3) - 1);
21965#ifdef NPU_DISASSEMBLE
21966 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
21968 fields.push_back(std::make_pair<std::string, std::string>(
"region", std::to_string(region)));
21979 uint32_t opcode : 10;
21980 uint32_t reserved0 : 4;
21981 uint32_t control : 2;
21982 uint32_t ab_start : 6;
21983 uint32_t reserved1 : 10;
21987 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_AB_START)), reserved0(0),
21988 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), ab_start(_ab_start & ((1U << 6) - 1)),
21993 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_AB_START)), reserved0(0),
21994 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), ab_start(0), reserved1(0)
21999 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START) &&
22000 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22004 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_AB_START);
22005 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22007 operator uint32_t()
22010 std::memcpy(&word,
this,
sizeof(word));
22013 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22015 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22019 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22022 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22024 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22028 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22031 CONSTEXPR uint32_t get_ab_start()
const
22033 return static_cast<uint32_t
>(ab_start);
22037 ab_start =
static_cast<uint8_t
>(
value) & ((1U << 6) - 1);
22040#ifdef NPU_DISASSEMBLE
22041 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22043 fields.push_back(std::make_pair<std::string, std::string>(
"ab_start", std::to_string(ab_start)));
22054 uint32_t opcode : 10;
22055 uint32_t reserved0 : 4;
22056 uint32_t control : 2;
22057 uint32_t blockdep : 2;
22058 uint32_t reserved1 : 14;
22062 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_BLOCKDEP)), reserved0(0),
22063 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), blockdep(_blockdep & ((1U << 2) - 1)),
22068 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_BLOCKDEP)), reserved0(0),
22069 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), blockdep(0), reserved1(0)
22074 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP) &&
22075 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22079 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_BLOCKDEP);
22080 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22082 operator uint32_t()
22085 std::memcpy(&word,
this,
sizeof(word));
22088 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22090 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22094 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22097 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22099 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22103 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22106 CONSTEXPR uint32_t get_blockdep()
const
22108 return static_cast<uint32_t
>(blockdep);
22112 blockdep =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22115#ifdef NPU_DISASSEMBLE
22116 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22118 fields.push_back(std::make_pair<std::string, std::string>(
"blockdep", std::to_string(blockdep)));
22129 uint32_t opcode : 10;
22130 uint32_t reserved0 : 4;
22131 uint32_t control : 2;
22132 uint32_t region : 3;
22133 uint32_t reserved1 : 5;
22134 uint32_t region_mode : 1;
22135 uint32_t stride_mode : 2;
22136 uint32_t reserved2 : 5;
22140 NPU_NAMESPACE::dma_region_mode _region_mode,
22141 NPU_NAMESPACE::dma_stride_mode _stride_mode) :
22142 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_DMA0_SRC_REGION)),
22143 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
22144 region(_region & ((1U << 3) - 1)), reserved1(0),
22145 region_mode(static_cast<uint8_t>(_region_mode) & ((1U << 1) - 1)),
22146 stride_mode(static_cast<uint8_t>(_stride_mode) & ((1U << 2) - 1)), reserved2(0)
22150 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_DMA0_SRC_REGION)), reserved0(0),
22151 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), region_mode(0),
22152 stride_mode(0), reserved2(0)
22157 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION) &&
22158 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22162 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SRC_REGION);
22163 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22165 operator uint32_t()
22168 std::memcpy(&word,
this,
sizeof(word));
22171 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22173 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22177 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22180 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22182 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22186 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22191 return static_cast<uint32_t
>(region);
22195 region =
static_cast<uint8_t
>(
value) & ((1U << 3) - 1);
22198 CONSTEXPR NPU_NAMESPACE::dma_region_mode get_region_mode()
const
22200 return static_cast<NPU_NAMESPACE::dma_region_mode
>(region_mode);
22204 region_mode =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
22207 CONSTEXPR NPU_NAMESPACE::dma_stride_mode get_stride_mode()
const
22209 return static_cast<NPU_NAMESPACE::dma_stride_mode
>(stride_mode);
22213 stride_mode =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22216#ifdef NPU_DISASSEMBLE
22217 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22219 fields.push_back(std::make_pair<std::string, std::string>(
"region", std::to_string(region)));
22220 fields.push_back(std::make_pair<std::string, std::string>(
22222 (region_mode < (
sizeof(dma_region_mode_str) /
sizeof(dma_region_mode_str[0])) ?
22223 dma_region_mode_str[region_mode] :
22225 fields.push_back(std::make_pair<std::string, std::string>(
22227 (stride_mode < (
sizeof(dma_stride_mode_str) /
sizeof(dma_stride_mode_str[0])) ?
22228 dma_stride_mode_str[stride_mode] :
22240 uint32_t opcode : 10;
22241 uint32_t reserved0 : 4;
22242 uint32_t control : 2;
22243 uint32_t region : 3;
22245 uint32_t reserved1 : 5;
22246 uint32_t region_mode : 1;
22247 uint32_t stride_mode : 2;
22248 uint32_t reserved2 : 5;
22252 NPU_NAMESPACE::dma_region_mode _region_mode,
22253 NPU_NAMESPACE::dma_stride_mode _stride_mode) :
22254 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_DMA0_DST_REGION)),
22255 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
22256 region(_region & ((1U << 3) - 1)), reserved1(0),
22257 region_mode(static_cast<uint8_t>(_region_mode) & ((1U << 1) - 1)),
22258 stride_mode(static_cast<uint8_t>(_stride_mode) & ((1U << 2) - 1)), reserved2(0)
22262 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_DMA0_DST_REGION)), reserved0(0),
22263 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0), region_mode(0),
22264 stride_mode(0), reserved2(0)
22269 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION) &&
22270 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22274 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_DST_REGION);
22275 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22277 operator uint32_t()
22280 std::memcpy(&word,
this,
sizeof(word));
22283 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22285 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22289 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22292 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22294 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22298 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22303 return static_cast<uint32_t
>(region);
22307 region =
static_cast<uint8_t
>(
value) & ((1U << 3) - 1);
22310 CONSTEXPR NPU_NAMESPACE::dma_region_mode get_region_mode()
const
22312 return static_cast<NPU_NAMESPACE::dma_region_mode
>(region_mode);
22316 region_mode =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
22319 CONSTEXPR NPU_NAMESPACE::dma_stride_mode get_stride_mode()
const
22321 return static_cast<NPU_NAMESPACE::dma_stride_mode
>(stride_mode);
22325 stride_mode =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22328#ifdef NPU_DISASSEMBLE
22329 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22331 fields.push_back(std::make_pair<std::string, std::string>(
"region", std::to_string(region)));
22332 fields.push_back(std::make_pair<std::string, std::string>(
22334 (region_mode < (
sizeof(dma_region_mode_str) /
sizeof(dma_region_mode_str[0])) ?
22335 dma_region_mode_str[region_mode] :
22337 fields.push_back(std::make_pair<std::string, std::string>(
22339 (stride_mode < (
sizeof(dma_stride_mode_str) /
sizeof(dma_stride_mode_str[0])) ?
22340 dma_stride_mode_str[stride_mode] :
22352 uint32_t opcode : 10;
22353 uint32_t reserved0 : 4;
22354 uint32_t control : 2;
22355 uint32_t
size : 16;
22359 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_DMA0_SIZE0)), reserved0(0),
22360 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
size(_size & ((1U << 16) - 1))
22364 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_DMA0_SIZE0)), reserved0(0),
22365 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
size(0)
22370 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0) &&
22371 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22375 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE0);
22376 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22378 operator uint32_t()
22381 std::memcpy(&word,
this,
sizeof(word));
22384 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22386 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22390 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22393 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22395 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22399 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22404 return static_cast<uint32_t
>(
size);
22408 size =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
22411#ifdef NPU_DISASSEMBLE
22412 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22414 fields.push_back(std::make_pair<std::string, std::string>(
"size", std::to_string(
size)));
22425 uint32_t opcode : 10;
22426 uint32_t reserved0 : 4;
22427 uint32_t control : 2;
22428 uint32_t
size : 16;
22432 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_DMA0_SIZE1)), reserved0(0),
22433 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
size(_size & ((1U << 16) - 1))
22437 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_DMA0_SIZE1)), reserved0(0),
22438 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
size(0)
22443 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1) &&
22444 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22448 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_DMA0_SIZE1);
22449 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22451 operator uint32_t()
22454 std::memcpy(&word,
this,
sizeof(word));
22457 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22459 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22463 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22466 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22468 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22472 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22477 return static_cast<uint32_t
>(
size);
22481 size =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
22484#ifdef NPU_DISASSEMBLE
22485 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22487 fields.push_back(std::make_pair<std::string, std::string>(
"size", std::to_string(
size)));
22498 uint32_t opcode : 10;
22499 uint32_t reserved0 : 4;
22500 uint32_t control : 2;
22503 uint32_t broadcast_w : 1;
22504 uint32_t broadcast_c : 1;
22505 uint32_t reserved1 : 3;
22506 uint32_t operand_order : 1;
22507 uint32_t broadcast_constant : 1;
22508 uint32_t reserved2 : 8;
22512 NPU_NAMESPACE::broadcast_mode _broadcast_w,
22513 NPU_NAMESPACE::broadcast_mode _broadcast_c,
22514 NPU_NAMESPACE::ifm2_operand_order _operand_order,
22515 NPU_NAMESPACE::broadcast_mode _broadcast_constant) :
22516 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_BROADCAST)),
22517 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
22518 broadcast_h(static_cast<uint8_t>(_broadcast_h) & ((1U << 1) - 1)),
22519 broadcast_w(static_cast<uint8_t>(_broadcast_w) & ((1U << 1) - 1)),
22520 broadcast_c(static_cast<uint8_t>(_broadcast_c) & ((1U << 1) - 1)), reserved1(0),
22521 operand_order(static_cast<uint8_t>(_operand_order) & ((1U << 1) - 1)),
22522 broadcast_constant(static_cast<uint8_t>(_broadcast_constant) & ((1U << 1) - 1)), reserved2(0)
22526 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_BROADCAST)), reserved0(0),
22527 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), broadcast_h(0), broadcast_w(0),
22528 broadcast_c(0), reserved1(0), operand_order(0), broadcast_constant(0), reserved2(0)
22533 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST) &&
22534 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22538 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_BROADCAST);
22539 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22541 operator uint32_t()
22544 std::memcpy(&word,
this,
sizeof(word));
22547 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22549 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22553 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22556 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22558 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22562 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22565 CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_h()
const
22567 return static_cast<NPU_NAMESPACE::broadcast_mode
>(broadcast_h);
22571 broadcast_h =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
22574 CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_w()
const
22576 return static_cast<NPU_NAMESPACE::broadcast_mode
>(broadcast_w);
22580 broadcast_w =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
22583 CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_c()
const
22585 return static_cast<NPU_NAMESPACE::broadcast_mode
>(broadcast_c);
22589 broadcast_c =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
22592 CONSTEXPR NPU_NAMESPACE::ifm2_operand_order get_operand_order()
const
22594 return static_cast<NPU_NAMESPACE::ifm2_operand_order
>(operand_order);
22598 operand_order =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
22601 CONSTEXPR NPU_NAMESPACE::broadcast_mode get_broadcast_constant()
const
22603 return static_cast<NPU_NAMESPACE::broadcast_mode
>(broadcast_constant);
22607 broadcast_constant =
static_cast<uint8_t
>(
value) & ((1U << 1) - 1);
22610#ifdef NPU_DISASSEMBLE
22611 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22613 fields.push_back(std::make_pair<std::string, std::string>(
22615 (broadcast_h < (
sizeof(broadcast_mode_str) /
sizeof(broadcast_mode_str[0])) ?
22616 broadcast_mode_str[broadcast_h] :
22618 fields.push_back(std::make_pair<std::string, std::string>(
22620 (broadcast_w < (
sizeof(broadcast_mode_str) /
sizeof(broadcast_mode_str[0])) ?
22621 broadcast_mode_str[broadcast_w] :
22623 fields.push_back(std::make_pair<std::string, std::string>(
22625 (broadcast_c < (
sizeof(broadcast_mode_str) /
sizeof(broadcast_mode_str[0])) ?
22626 broadcast_mode_str[broadcast_c] :
22628 fields.push_back(std::make_pair<std::string, std::string>(
22630 (operand_order < (
sizeof(ifm2_operand_order_str) /
sizeof(ifm2_operand_order_str[0])) ?
22631 ifm2_operand_order_str[operand_order] :
22633 fields.push_back(std::make_pair<std::string, std::string>(
22634 "broadcast_constant",
22635 (broadcast_constant < (
sizeof(broadcast_mode_str) /
sizeof(broadcast_mode_str[0])) ?
22636 broadcast_mode_str[broadcast_constant] :
22648 uint32_t opcode : 10;
22649 uint32_t reserved0 : 4;
22650 uint32_t control : 2;
22651 uint32_t scalar : 16;
22655 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_SCALAR)), reserved0(0),
22656 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), scalar(_scalar & ((1U << 16) - 1))
22660 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_SCALAR)), reserved0(0),
22661 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), scalar(0)
22666 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR) &&
22667 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22671 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_SCALAR);
22672 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22674 operator uint32_t()
22677 std::memcpy(&word,
this,
sizeof(word));
22680 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22682 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22686 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22689 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22691 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22695 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22700 return static_cast<uint32_t
>(scalar);
22704 scalar =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
22707#ifdef NPU_DISASSEMBLE
22708 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22710 fields.push_back(std::make_pair<std::string, std::string>(
"scalar", std::to_string(scalar)));
22721 uint32_t opcode : 10;
22722 uint32_t reserved0 : 4;
22723 uint32_t control : 2;
22725 uint32_t reserved1 : 1;
22727 uint32_t reserved2 : 2;
22729 uint32_t reserved3 : 8;
22733 NPU_NAMESPACE::activation_precision _activation_precision,
22734 NPU_NAMESPACE::activation_format _activation_format) :
22735 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_PRECISION)),
22736 reserved0(0), control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
22737 activation_type(static_cast<uint8_t>(_activation_type) & ((1U << 1) - 1)), reserved1(0),
22738 activation_precision(static_cast<uint8_t>(_activation_precision) & ((1U << 2) - 1)), reserved2(0),
22739 activation_format(static_cast<uint8_t>(_activation_format) & ((1U << 2) - 1)), reserved3(0)
22743 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_PRECISION)), reserved0(0),
22750 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION) &&
22751 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22755 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_PRECISION);
22756 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22758 operator uint32_t()
22761 std::memcpy(&word,
this,
sizeof(word));
22764 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22766 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22770 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22773 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22775 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22779 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22782 CONSTEXPR NPU_NAMESPACE::activation_type get_activation_type()
const
22791 CONSTEXPR NPU_NAMESPACE::activation_precision get_activation_precision()
const
22800 CONSTEXPR NPU_NAMESPACE::activation_format get_activation_format()
const
22809#ifdef NPU_DISASSEMBLE
22810 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22812 fields.push_back(std::make_pair<std::string, std::string>(
22814 (
activation_type < (
sizeof(activation_type_str) /
sizeof(activation_type_str[0])) ?
22817 fields.push_back(std::make_pair<std::string, std::string>(
22818 "activation_precision",
22819 (
activation_precision < (
sizeof(activation_precision_str) /
sizeof(activation_precision_str[0])) ?
22822 fields.push_back(std::make_pair<std::string, std::string>(
22823 "activation_format",
22824 (
activation_format < (
sizeof(activation_format_str) /
sizeof(activation_format_str[0])) ?
22837 uint32_t opcode : 10;
22838 uint32_t reserved0 : 4;
22839 uint32_t control : 2;
22844 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_ZERO_POINT)), reserved0(0),
22845 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)),
22850 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_ZERO_POINT)), reserved0(0),
22856 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT) &&
22857 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22861 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_ZERO_POINT);
22862 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22864 operator uint32_t()
22867 std::memcpy(&word,
this,
sizeof(word));
22870 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22872 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22876 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22879 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22881 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22885 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22888 CONSTEXPR uint32_t get_zero_point()
const
22897#ifdef NPU_DISASSEMBLE
22898 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22900 fields.push_back(std::make_pair<std::string, std::string>(
"zero_point", std::to_string(
zero_point)));
22911 uint32_t opcode : 10;
22912 uint32_t reserved0 : 4;
22913 uint32_t control : 2;
22914 uint32_t width_m1 : 16;
22918 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1)), reserved0(0),
22919 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(_width_m1 & ((1U << 16) - 1))
22923 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1)), reserved0(0),
22924 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), width_m1(0)
22929 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1) &&
22930 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22934 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_WIDTH0_M1);
22935 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
22937 operator uint32_t()
22940 std::memcpy(&word,
this,
sizeof(word));
22943 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
22945 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
22949 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
22952 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
22954 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
22958 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
22961 CONSTEXPR uint32_t get_width_m1()
const
22963 return static_cast<uint32_t
>(width_m1);
22967 width_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
22970#ifdef NPU_DISASSEMBLE
22971 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
22973 fields.push_back(std::make_pair<std::string, std::string>(
"width_m1", std::to_string(width_m1)));
22984 uint32_t opcode : 10;
22985 uint32_t reserved0 : 4;
22986 uint32_t control : 2;
22987 uint32_t height_m1 : 16;
22991 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1)), reserved0(0),
22992 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
22996 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1)), reserved0(0),
22997 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(0)
23002 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1) &&
23003 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23007 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT0_M1);
23008 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23010 operator uint32_t()
23013 std::memcpy(&word,
this,
sizeof(word));
23016 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
23018 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
23022 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
23025 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
23027 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
23031 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
23034 CONSTEXPR uint32_t get_height_m1()
const
23036 return static_cast<uint32_t
>(height_m1);
23040 height_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
23043#ifdef NPU_DISASSEMBLE
23044 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23046 fields.push_back(std::make_pair<std::string, std::string>(
"height_m1", std::to_string(height_m1)));
23057 uint32_t opcode : 10;
23058 uint32_t reserved0 : 4;
23059 uint32_t control : 2;
23060 uint32_t height_m1 : 16;
23064 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1)), reserved0(0),
23065 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(_height_m1 & ((1U << 16) - 1))
23069 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1)), reserved0(0),
23070 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), height_m1(0)
23075 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1) &&
23076 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23080 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_HEIGHT1_M1);
23081 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23083 operator uint32_t()
23086 std::memcpy(&word,
this,
sizeof(word));
23089 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
23091 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
23095 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
23098 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
23100 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
23104 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
23107 CONSTEXPR uint32_t get_height_m1()
const
23109 return static_cast<uint32_t
>(height_m1);
23113 height_m1 =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
23116#ifdef NPU_DISASSEMBLE
23117 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23119 fields.push_back(std::make_pair<std::string, std::string>(
"height_m1", std::to_string(height_m1)));
23130 uint32_t opcode : 10;
23131 uint32_t reserved0 : 4;
23132 uint32_t control : 2;
23133 uint32_t ib_start : 6;
23134 uint32_t reserved1 : 10;
23138 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_IB_START)), reserved0(0),
23139 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), ib_start(_ib_start & ((1U << 6) - 1)),
23144 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_IB_START)), reserved0(0),
23145 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), ib_start(0), reserved1(0)
23150 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START) &&
23151 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23155 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_IB_START);
23156 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23158 operator uint32_t()
23161 std::memcpy(&word,
this,
sizeof(word));
23164 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
23166 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
23170 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
23173 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
23175 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
23179 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
23182 CONSTEXPR uint32_t get_ib_start()
const
23184 return static_cast<uint32_t
>(ib_start);
23188 ib_start =
static_cast<uint8_t
>(
value) & ((1U << 6) - 1);
23191#ifdef NPU_DISASSEMBLE
23192 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23194 fields.push_back(std::make_pair<std::string, std::string>(
"ib_start", std::to_string(ib_start)));
23205 uint32_t opcode : 10;
23206 uint32_t reserved0 : 4;
23207 uint32_t control : 2;
23208 uint32_t region : 3;
23209 uint32_t reserved1 : 13;
23213 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_REGION)), reserved0(0),
23214 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(_region & ((1U << 3) - 1)),
23219 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd0_opcode::NPU_SET_IFM2_REGION)), reserved0(0),
23220 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD0_CTRL)), region(0), reserved1(0)
23225 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION) &&
23226 control ==
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23230 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd0_opcode::NPU_SET_IFM2_REGION);
23231 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD0_CTRL);
23233 operator uint32_t()
23236 std::memcpy(&word,
this,
sizeof(word));
23239 CONSTEXPR NPU_NAMESPACE::cmd0_opcode get_opcode()
const
23241 return static_cast<NPU_NAMESPACE::cmd0_opcode
>(opcode);
23245 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
23248 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
23250 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
23254 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
23259 return static_cast<uint32_t
>(region);
23263 region =
static_cast<uint8_t
>(
value) & ((1U << 3) - 1);
23266#ifdef NPU_DISASSEMBLE
23267 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23269 fields.push_back(std::make_pair<std::string, std::string>(
"region", std::to_string(region)));
23280 uint32_t opcode : 10;
23281 uint32_t reserved0 : 4;
23282 uint32_t control : 2;
23284 uint32_t reserved1 : 8;
23289 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_BASE0)), reserved0(0),
23290 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23291 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23292 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23296 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_BASE0)), reserved0(0),
23297 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23302 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0) && control >= 1 &&
23307 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE0);
23308 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23310 operator uint64_t()
23313 std::memcpy(&word,
this,
sizeof(word));
23318 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23322 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23323 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23326#ifdef NPU_DISASSEMBLE
23327 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23329 std::stringstream saddr;
23330 saddr << std::hex <<
"0x" << get_addr();
23331 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23342 uint32_t opcode : 10;
23343 uint32_t reserved0 : 4;
23344 uint32_t control : 2;
23346 uint32_t reserved1 : 8;
23351 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_BASE1)), reserved0(0),
23352 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23353 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23354 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23358 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_BASE1)), reserved0(0),
23359 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23364 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1) && control >= 1 &&
23369 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE1);
23370 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23372 operator uint64_t()
23375 std::memcpy(&word,
this,
sizeof(word));
23380 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23384 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23385 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23388#ifdef NPU_DISASSEMBLE
23389 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23391 std::stringstream saddr;
23392 saddr << std::hex <<
"0x" << get_addr();
23393 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23404 uint32_t opcode : 10;
23405 uint32_t reserved0 : 4;
23406 uint32_t control : 2;
23408 uint32_t reserved1 : 8;
23413 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_BASE2)), reserved0(0),
23414 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23415 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23416 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23420 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_BASE2)), reserved0(0),
23421 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23426 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2) && control >= 1 &&
23431 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE2);
23432 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23434 operator uint64_t()
23437 std::memcpy(&word,
this,
sizeof(word));
23442 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23446 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23447 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23450#ifdef NPU_DISASSEMBLE
23451 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23453 std::stringstream saddr;
23454 saddr << std::hex <<
"0x" << get_addr();
23455 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23466 uint32_t opcode : 10;
23467 uint32_t reserved0 : 4;
23468 uint32_t control : 2;
23470 uint32_t reserved1 : 8;
23475 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_BASE3)), reserved0(0),
23476 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23477 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23478 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23482 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_BASE3)), reserved0(0),
23483 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23488 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3) && control >= 1 &&
23493 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_BASE3);
23494 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23496 operator uint64_t()
23499 std::memcpy(&word,
this,
sizeof(word));
23504 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23508 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23509 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23512#ifdef NPU_DISASSEMBLE
23513 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23515 std::stringstream saddr;
23516 saddr << std::hex <<
"0x" << get_addr();
23517 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23528 uint32_t opcode : 10;
23529 uint32_t reserved0 : 4;
23530 uint32_t control : 2;
23532 uint32_t reserved1 : 8;
23537 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_STRIDE_X)), reserved0(0),
23538 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23539 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23540 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23544 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_STRIDE_X)), reserved0(0),
23545 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23550 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X) && control >= 1 &&
23555 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_X);
23556 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23558 operator uint64_t()
23561 std::memcpy(&word,
this,
sizeof(word));
23566 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23570 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23571 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23574#ifdef NPU_DISASSEMBLE
23575 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23577 std::stringstream saddr;
23578 saddr << std::hex <<
"0x" << get_addr();
23579 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23590 uint32_t opcode : 10;
23591 uint32_t reserved0 : 4;
23592 uint32_t control : 2;
23594 uint32_t reserved1 : 8;
23599 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_STRIDE_Y)), reserved0(0),
23600 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23601 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23602 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23606 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_STRIDE_Y)), reserved0(0),
23607 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23612 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y) && control >= 1 &&
23617 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_Y);
23618 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23620 operator uint64_t()
23623 std::memcpy(&word,
this,
sizeof(word));
23628 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23632 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23633 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23636#ifdef NPU_DISASSEMBLE
23637 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23639 std::stringstream saddr;
23640 saddr << std::hex <<
"0x" << get_addr();
23641 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23652 uint32_t opcode : 10;
23653 uint32_t reserved0 : 4;
23654 uint32_t control : 2;
23656 uint32_t reserved1 : 8;
23661 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_STRIDE_C)), reserved0(0),
23662 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23663 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23664 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23668 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM_STRIDE_C)), reserved0(0),
23669 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23674 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C) && control >= 1 &&
23679 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM_STRIDE_C);
23680 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23682 operator uint64_t()
23685 std::memcpy(&word,
this,
sizeof(word));
23690 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23694 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23695 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23698#ifdef NPU_DISASSEMBLE
23699 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23701 std::stringstream saddr;
23702 saddr << std::hex <<
"0x" << get_addr();
23703 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23714 uint32_t opcode : 10;
23715 uint32_t reserved0 : 4;
23716 uint32_t control : 2;
23718 uint32_t reserved1 : 8;
23723 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_BASE0)), reserved0(0),
23724 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23725 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23726 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23730 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_BASE0)), reserved0(0),
23731 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23736 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0) && control >= 1 &&
23741 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE0);
23742 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23744 operator uint64_t()
23747 std::memcpy(&word,
this,
sizeof(word));
23752 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23756 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23757 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23760#ifdef NPU_DISASSEMBLE
23761 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23763 std::stringstream saddr;
23764 saddr << std::hex <<
"0x" << get_addr();
23765 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23776 uint32_t opcode : 10;
23777 uint32_t reserved0 : 4;
23778 uint32_t control : 2;
23780 uint32_t reserved1 : 8;
23785 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_BASE1)), reserved0(0),
23786 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23787 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23788 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23792 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_BASE1)), reserved0(0),
23793 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23798 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1) && control >= 1 &&
23803 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE1);
23804 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23806 operator uint64_t()
23809 std::memcpy(&word,
this,
sizeof(word));
23814 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23818 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23819 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23822#ifdef NPU_DISASSEMBLE
23823 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23825 std::stringstream saddr;
23826 saddr << std::hex <<
"0x" << get_addr();
23827 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23838 uint32_t opcode : 10;
23839 uint32_t reserved0 : 4;
23840 uint32_t control : 2;
23842 uint32_t reserved1 : 8;
23847 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_BASE2)), reserved0(0),
23848 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23849 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23850 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23854 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_BASE2)), reserved0(0),
23855 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23860 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2) && control >= 1 &&
23865 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE2);
23866 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23868 operator uint64_t()
23871 std::memcpy(&word,
this,
sizeof(word));
23876 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23880 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23881 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23884#ifdef NPU_DISASSEMBLE
23885 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23887 std::stringstream saddr;
23888 saddr << std::hex <<
"0x" << get_addr();
23889 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23900 uint32_t opcode : 10;
23901 uint32_t reserved0 : 4;
23902 uint32_t control : 2;
23904 uint32_t reserved1 : 8;
23909 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_BASE3)), reserved0(0),
23910 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23911 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23912 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23916 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_BASE3)), reserved0(0),
23917 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23922 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3) && control >= 1 &&
23927 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_BASE3);
23928 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23930 operator uint64_t()
23933 std::memcpy(&word,
this,
sizeof(word));
23938 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
23942 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
23943 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
23946#ifdef NPU_DISASSEMBLE
23947 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
23949 std::stringstream saddr;
23950 saddr << std::hex <<
"0x" << get_addr();
23951 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
23962 uint32_t opcode : 10;
23963 uint32_t reserved0 : 4;
23964 uint32_t control : 2;
23966 uint32_t reserved1 : 8;
23971 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_STRIDE_X)), reserved0(0),
23972 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
23973 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
23974 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
23978 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_STRIDE_X)), reserved0(0),
23979 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
23984 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X) && control >= 1 &&
23989 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_X);
23990 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
23992 operator uint64_t()
23995 std::memcpy(&word,
this,
sizeof(word));
24000 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
24004 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
24005 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
24008#ifdef NPU_DISASSEMBLE
24009 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24011 std::stringstream saddr;
24012 saddr << std::hex <<
"0x" << get_addr();
24013 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
24024 uint32_t opcode : 10;
24025 uint32_t reserved0 : 4;
24026 uint32_t control : 2;
24028 uint32_t reserved1 : 8;
24033 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_STRIDE_Y)), reserved0(0),
24034 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
24035 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
24036 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
24040 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_STRIDE_Y)), reserved0(0),
24041 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24046 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y) && control >= 1 &&
24051 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_Y);
24052 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24054 operator uint64_t()
24057 std::memcpy(&word,
this,
sizeof(word));
24062 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
24066 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
24067 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
24070#ifdef NPU_DISASSEMBLE
24071 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24073 std::stringstream saddr;
24074 saddr << std::hex <<
"0x" << get_addr();
24075 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
24086 uint32_t opcode : 10;
24087 uint32_t reserved0 : 4;
24088 uint32_t control : 2;
24090 uint32_t reserved1 : 8;
24095 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_STRIDE_C)), reserved0(0),
24096 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
24097 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
24098 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
24102 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_STRIDE_C)), reserved0(0),
24103 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24108 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C) && control >= 1 &&
24113 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_STRIDE_C);
24114 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24116 operator uint64_t()
24119 std::memcpy(&word,
this,
sizeof(word));
24124 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
24128 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
24129 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
24132#ifdef NPU_DISASSEMBLE
24133 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24135 std::stringstream saddr;
24136 saddr << std::hex <<
"0x" << get_addr();
24137 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
24148 uint32_t opcode : 10;
24149 uint32_t reserved0 : 4;
24150 uint32_t control : 2;
24152 uint32_t reserved1 : 8;
24157 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_WEIGHT_BASE)), reserved0(0),
24158 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
24159 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
24160 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
24164 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_WEIGHT_BASE)), reserved0(0),
24165 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24170 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE) && control >= 1 &&
24175 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_BASE);
24176 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24178 operator uint64_t()
24181 std::memcpy(&word,
this,
sizeof(word));
24186 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
24190 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
24191 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
24194#ifdef NPU_DISASSEMBLE
24195 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24197 std::stringstream saddr;
24198 saddr << std::hex <<
"0x" << get_addr();
24199 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
24210 uint32_t opcode : 10;
24211 uint32_t reserved0 : 4;
24212 uint32_t control : 2;
24213 uint32_t reserved1 : 16;
24214 uint32_t length : 32;
24218 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_WEIGHT_LENGTH)), reserved0(0),
24219 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), reserved1(0), length(_length)
24223 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_WEIGHT_LENGTH)), reserved0(0),
24224 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0)
24229 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH) && control >= 1 &&
24234 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT_LENGTH);
24235 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24237 operator uint64_t()
24240 std::memcpy(&word,
this,
sizeof(word));
24243 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode()
const
24245 return static_cast<NPU_NAMESPACE::cmd1_opcode
>(opcode);
24249 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
24252 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
24254 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
24258 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
24263 return static_cast<uint32_t
>(length);
24270#ifdef NPU_DISASSEMBLE
24271 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24273 fields.push_back(std::make_pair<std::string, std::string>(
"length", std::to_string(length)));
24284 uint32_t opcode : 10;
24285 uint32_t reserved0 : 4;
24286 uint32_t control : 2;
24288 uint32_t reserved1 : 8;
24293 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_SCALE_BASE)), reserved0(0),
24294 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
24295 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
24296 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
24300 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_SCALE_BASE)), reserved0(0),
24301 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24306 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE) && control >= 1 &&
24311 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_BASE);
24312 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24314 operator uint64_t()
24317 std::memcpy(&word,
this,
sizeof(word));
24322 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
24326 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
24327 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
24330#ifdef NPU_DISASSEMBLE
24331 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24333 std::stringstream saddr;
24334 saddr << std::hex <<
"0x" << get_addr();
24335 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
24346 uint32_t opcode : 10;
24347 uint32_t reserved0 : 4;
24348 uint32_t control : 2;
24349 uint32_t reserved1 : 16;
24350 uint32_t length : 20;
24351 uint32_t reserved2 : 12;
24355 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_SCALE_LENGTH)), reserved0(0),
24356 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), reserved1(0),
24357 length(_length & ((1U << 20) - 1)), reserved2(0)
24361 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_SCALE_LENGTH)), reserved0(0),
24362 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0), reserved2(0)
24367 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH) && control >= 1 &&
24372 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE_LENGTH);
24373 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24375 operator uint64_t()
24378 std::memcpy(&word,
this,
sizeof(word));
24381 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode()
const
24383 return static_cast<NPU_NAMESPACE::cmd1_opcode
>(opcode);
24387 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
24390 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
24392 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
24396 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
24401 return static_cast<uint32_t
>(length);
24405 length =
value & ((1U << 20) - 1);
24408#ifdef NPU_DISASSEMBLE
24409 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24411 fields.push_back(std::make_pair<std::string, std::string>(
"length", std::to_string(length)));
24422 uint32_t opcode : 10;
24423 uint32_t reserved0 : 4;
24424 uint32_t control : 2;
24425 uint32_t
shift : 6;
24426 uint32_t reserved1 : 10;
24427 uint32_t
scale : 32;
24431 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_SCALE)), reserved0(0),
24432 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
shift(_shift & ((1U << 6) - 1)),
24433 reserved1(0),
scale(_scale)
24437 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OFM_SCALE)), reserved0(0),
24438 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
shift(0), reserved1(0),
scale(0)
24443 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE) && control >= 1 &&
24448 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OFM_SCALE);
24449 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24451 operator uint64_t()
24454 std::memcpy(&word,
this,
sizeof(word));
24457 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode()
const
24459 return static_cast<NPU_NAMESPACE::cmd1_opcode
>(opcode);
24463 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
24466 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
24468 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
24472 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
24477 return static_cast<uint32_t
>(
shift);
24481 shift =
static_cast<uint8_t
>(
value) & ((1U << 6) - 1);
24486 return static_cast<uint32_t
>(
scale);
24493#ifdef NPU_DISASSEMBLE
24494 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24496 fields.push_back(std::make_pair<std::string, std::string>(
"shift", std::to_string(
shift)));
24497 fields.push_back(std::make_pair<std::string, std::string>(
"scale", std::to_string(
scale)));
24508 uint32_t opcode : 10;
24509 uint32_t reserved0 : 4;
24510 uint32_t control : 2;
24511 uint32_t
shift : 6;
24512 uint32_t reserved1 : 10;
24513 uint32_t
scale : 32;
24517 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OPA_SCALE)), reserved0(0),
24518 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
shift(_shift & ((1U << 6) - 1)),
24519 reserved1(0),
scale(_scale)
24523 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OPA_SCALE)), reserved0(0),
24524 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
shift(0), reserved1(0),
scale(0)
24529 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE) && control >= 1 &&
24534 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPA_SCALE);
24535 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24537 operator uint64_t()
24540 std::memcpy(&word,
this,
sizeof(word));
24543 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode()
const
24545 return static_cast<NPU_NAMESPACE::cmd1_opcode
>(opcode);
24549 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
24552 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
24554 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
24558 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
24563 return static_cast<uint32_t
>(
shift);
24567 shift =
static_cast<uint8_t
>(
value) & ((1U << 6) - 1);
24572 return static_cast<uint32_t
>(
scale);
24579#ifdef NPU_DISASSEMBLE
24580 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24582 fields.push_back(std::make_pair<std::string, std::string>(
"shift", std::to_string(
shift)));
24583 fields.push_back(std::make_pair<std::string, std::string>(
"scale", std::to_string(
scale)));
24594 uint32_t opcode : 10;
24595 uint32_t reserved0 : 4;
24596 uint32_t control : 2;
24597 uint32_t reserved1 : 16;
24598 uint32_t
scale : 16;
24599 uint32_t reserved2 : 16;
24603 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OPB_SCALE)), reserved0(0),
24604 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), reserved1(0),
24605 scale(_scale & ((1U << 16) - 1)), reserved2(0)
24609 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_OPB_SCALE)), reserved0(0),
24610 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), reserved1(0),
scale(0), reserved2(0)
24615 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE) && control >= 1 &&
24620 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_OPB_SCALE);
24621 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24623 operator uint64_t()
24626 std::memcpy(&word,
this,
sizeof(word));
24629 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode()
const
24631 return static_cast<NPU_NAMESPACE::cmd1_opcode
>(opcode);
24635 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
24638 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
24640 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
24644 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
24649 return static_cast<uint32_t
>(
scale);
24653 scale =
static_cast<uint16_t
>(
value) & ((1U << 16) - 1);
24656#ifdef NPU_DISASSEMBLE
24657 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24659 fields.push_back(std::make_pair<std::string, std::string>(
"scale", std::to_string(
scale)));
24670 uint32_t opcode : 10;
24671 uint32_t reserved0 : 4;
24672 uint32_t control : 2;
24674 uint32_t reserved1 : 8;
24679 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_DMA0_SRC)), reserved0(0),
24680 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
24681 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
24682 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
24686 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_DMA0_SRC)), reserved0(0),
24687 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24692 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC) && control >= 1 &&
24697 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SRC);
24698 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24700 operator uint64_t()
24703 std::memcpy(&word,
this,
sizeof(word));
24708 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
24712 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
24713 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
24716#ifdef NPU_DISASSEMBLE
24717 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24719 std::stringstream saddr;
24720 saddr << std::hex <<
"0x" << get_addr();
24721 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
24732 uint32_t opcode : 10;
24733 uint32_t reserved0 : 4;
24734 uint32_t control : 2;
24736 uint32_t reserved1 : 8;
24741 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_DMA0_DST)), reserved0(0),
24742 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
24743 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
24744 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
24748 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_DMA0_DST)), reserved0(0),
24749 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24754 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST) && control >= 1 &&
24759 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_DST);
24760 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24762 operator uint64_t()
24765 std::memcpy(&word,
this,
sizeof(word));
24770 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
24774 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
24775 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
24778#ifdef NPU_DISASSEMBLE
24779 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24781 std::stringstream saddr;
24782 saddr << std::hex <<
"0x" << get_addr();
24783 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
24794 uint32_t opcode : 10;
24795 uint32_t reserved0 : 4;
24796 uint32_t control : 2;
24798 uint32_t reserved1 : 8;
24803 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_DMA0_LEN)), reserved0(0),
24804 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
24805 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
24806 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
24810 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_DMA0_LEN)), reserved0(0),
24811 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24816 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN) && control >= 1 &&
24821 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_LEN);
24822 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24824 operator uint64_t()
24827 std::memcpy(&word,
this,
sizeof(word));
24832 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
24836 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
24837 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
24840#ifdef NPU_DISASSEMBLE
24841 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24843 std::stringstream saddr;
24844 saddr << std::hex <<
"0x" << get_addr();
24845 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
24865 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_DMA0_SKIP0)), reserved0(0),
24866 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
24867 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
24868 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
24872 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_DMA0_SKIP0)), reserved0(0),
24873 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24878 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0) && control >= 1 &&
24883 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP0);
24884 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24886 operator uint64_t()
24889 std::memcpy(&word,
this,
sizeof(word));
24894 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
24898 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
24899 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
24902#ifdef NPU_DISASSEMBLE
24903 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24905 std::stringstream saddr;
24906 saddr << std::hex <<
"0x" << get_addr();
24907 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
24927 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_DMA0_SKIP1)), reserved0(0),
24928 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
24929 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
24930 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
24934 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_DMA0_SKIP1)), reserved0(0),
24935 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
24940 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1) && control >= 1 &&
24945 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_DMA0_SKIP1);
24946 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
24948 operator uint64_t()
24951 std::memcpy(&word,
this,
sizeof(word));
24956 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
24960 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
24961 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
24964#ifdef NPU_DISASSEMBLE
24965 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
24967 std::stringstream saddr;
24968 saddr << std::hex <<
"0x" << get_addr();
24969 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
24980 uint32_t opcode : 10;
24981 uint32_t reserved0 : 4;
24982 uint32_t control : 2;
24984 uint32_t reserved1 : 8;
24989 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_BASE0)), reserved0(0),
24990 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
24991 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
24992 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
24996 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_BASE0)), reserved0(0),
24997 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25002 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0) && control >= 1 &&
25007 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE0);
25008 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25010 operator uint64_t()
25013 std::memcpy(&word,
this,
sizeof(word));
25018 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
25022 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
25023 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
25026#ifdef NPU_DISASSEMBLE
25027 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25029 std::stringstream saddr;
25030 saddr << std::hex <<
"0x" << get_addr();
25031 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
25042 uint32_t opcode : 10;
25043 uint32_t reserved0 : 4;
25044 uint32_t control : 2;
25046 uint32_t reserved1 : 8;
25051 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_BASE1)), reserved0(0),
25052 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
25053 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
25054 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
25058 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_BASE1)), reserved0(0),
25059 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25064 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1) && control >= 1 &&
25069 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE1);
25070 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25072 operator uint64_t()
25075 std::memcpy(&word,
this,
sizeof(word));
25080 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
25084 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
25085 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
25088#ifdef NPU_DISASSEMBLE
25089 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25091 std::stringstream saddr;
25092 saddr << std::hex <<
"0x" << get_addr();
25093 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
25104 uint32_t opcode : 10;
25105 uint32_t reserved0 : 4;
25106 uint32_t control : 2;
25108 uint32_t reserved1 : 8;
25113 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_BASE2)), reserved0(0),
25114 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
25115 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
25116 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
25120 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_BASE2)), reserved0(0),
25121 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25126 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2) && control >= 1 &&
25131 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE2);
25132 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25134 operator uint64_t()
25137 std::memcpy(&word,
this,
sizeof(word));
25142 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
25146 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
25147 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
25150#ifdef NPU_DISASSEMBLE
25151 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25153 std::stringstream saddr;
25154 saddr << std::hex <<
"0x" << get_addr();
25155 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
25166 uint32_t opcode : 10;
25167 uint32_t reserved0 : 4;
25168 uint32_t control : 2;
25170 uint32_t reserved1 : 8;
25175 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_BASE3)), reserved0(0),
25176 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
25177 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
25178 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
25182 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_BASE3)), reserved0(0),
25183 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25188 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3) && control >= 1 &&
25193 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_BASE3);
25194 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25196 operator uint64_t()
25199 std::memcpy(&word,
this,
sizeof(word));
25204 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
25208 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
25209 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
25212#ifdef NPU_DISASSEMBLE
25213 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25215 std::stringstream saddr;
25216 saddr << std::hex <<
"0x" << get_addr();
25217 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
25228 uint32_t opcode : 10;
25229 uint32_t reserved0 : 4;
25230 uint32_t control : 2;
25232 uint32_t reserved1 : 8;
25237 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_STRIDE_X)), reserved0(0),
25238 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
25239 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
25240 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
25244 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_STRIDE_X)), reserved0(0),
25245 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25250 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X) && control >= 1 &&
25255 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_X);
25256 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25258 operator uint64_t()
25261 std::memcpy(&word,
this,
sizeof(word));
25266 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
25270 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
25271 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
25274#ifdef NPU_DISASSEMBLE
25275 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25277 std::stringstream saddr;
25278 saddr << std::hex <<
"0x" << get_addr();
25279 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
25290 uint32_t opcode : 10;
25291 uint32_t reserved0 : 4;
25292 uint32_t control : 2;
25294 uint32_t reserved1 : 8;
25299 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_STRIDE_Y)), reserved0(0),
25300 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
25301 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
25302 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
25306 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_STRIDE_Y)), reserved0(0),
25307 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25312 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y) && control >= 1 &&
25317 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_Y);
25318 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25320 operator uint64_t()
25323 std::memcpy(&word,
this,
sizeof(word));
25328 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
25332 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
25333 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
25336#ifdef NPU_DISASSEMBLE
25337 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25339 std::stringstream saddr;
25340 saddr << std::hex <<
"0x" << get_addr();
25341 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
25352 uint32_t opcode : 10;
25353 uint32_t reserved0 : 4;
25354 uint32_t control : 2;
25356 uint32_t reserved1 : 8;
25361 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_STRIDE_C)), reserved0(0),
25362 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
25363 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
25364 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
25368 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_IFM2_STRIDE_C)), reserved0(0),
25369 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25374 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C) && control >= 1 &&
25379 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_IFM2_STRIDE_C);
25380 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25382 operator uint64_t()
25385 std::memcpy(&word,
this,
sizeof(word));
25390 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
25394 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
25395 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
25398#ifdef NPU_DISASSEMBLE
25399 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25401 std::stringstream saddr;
25402 saddr << std::hex <<
"0x" << get_addr();
25403 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
25423 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_WEIGHT1_BASE)), reserved0(0),
25424 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
25425 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
25426 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
25430 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_WEIGHT1_BASE)), reserved0(0),
25431 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25436 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE) && control >= 1 &&
25441 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_BASE);
25442 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25444 operator uint64_t()
25447 std::memcpy(&word,
this,
sizeof(word));
25452 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
25456 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
25457 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
25460#ifdef NPU_DISASSEMBLE
25461 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25463 std::stringstream saddr;
25464 saddr << std::hex <<
"0x" << get_addr();
25465 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
25484 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_WEIGHT1_LENGTH)), reserved0(0),
25485 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), reserved1(0), length(_length)
25489 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_WEIGHT1_LENGTH)), reserved0(0),
25490 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0)
25495 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH) &&
25496 control >= 1 && control <= 2;
25500 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_WEIGHT1_LENGTH);
25501 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25503 operator uint64_t()
25506 std::memcpy(&word,
this,
sizeof(word));
25509 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode()
const
25511 return static_cast<NPU_NAMESPACE::cmd1_opcode
>(opcode);
25515 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
25518 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
25520 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
25524 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
25529 return static_cast<uint32_t
>(length);
25536#ifdef NPU_DISASSEMBLE
25537 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25539 fields.push_back(std::make_pair<std::string, std::string>(
"length", std::to_string(length)));
25559 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_SCALE1_BASE)), reserved0(0),
25560 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)),
25561 addr_hi(static_cast<uint8_t>((_addr >> 32) & std::numeric_limits<uint64_t>::
max())), reserved1(0),
25562 addr_lo(static_cast<uint32_t>((_addr)&std::numeric_limits<uint64_t>::
max()))
25566 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_SCALE1_BASE)), reserved0(0),
25567 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), addr_hi(0), reserved1(0), addr_lo(0)
25572 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE) && control >= 1 &&
25577 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_BASE);
25578 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25580 operator uint64_t()
25583 std::memcpy(&word,
this,
sizeof(word));
25588 return (
static_cast<uint64_t
>(addr_hi) << 32) | addr_lo;
25592 addr_lo =
static_cast<uint32_t
>((
value)&std::numeric_limits<uint64_t>::max());
25593 addr_hi =
static_cast<uint8_t
>((
value >> 32) & std::numeric_limits<uint64_t>::max());
25596#ifdef NPU_DISASSEMBLE
25597 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25599 std::stringstream saddr;
25600 saddr << std::hex <<
"0x" << get_addr();
25601 fields.push_back(std::make_pair<std::string, std::string>(
"addr", saddr.str()));
25621 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_SCALE1_LENGTH)), reserved0(0),
25622 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), reserved1(0),
25623 length(_length & ((1U << 20) - 1)), reserved2(0)
25627 opcode(static_cast<uint16_t>(NPU_NAMESPACE::
cmd1_opcode::NPU_SET_SCALE1_LENGTH)), reserved0(0),
25628 control(static_cast<uint8_t>(NPU_NAMESPACE::
cmd_ctrl::CMD1_CTRL)), reserved1(0), length(0), reserved2(0)
25633 return opcode ==
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH) && control >= 1 &&
25638 opcode =
static_cast<uint16_t
>(NPU_NAMESPACE::cmd1_opcode::NPU_SET_SCALE1_LENGTH);
25639 control =
static_cast<uint8_t
>(NPU_NAMESPACE::cmd_ctrl::CMD1_CTRL);
25641 operator uint64_t()
25644 std::memcpy(&word,
this,
sizeof(word));
25647 CONSTEXPR NPU_NAMESPACE::cmd1_opcode get_opcode()
const
25649 return static_cast<NPU_NAMESPACE::cmd1_opcode
>(opcode);
25653 opcode =
static_cast<uint16_t
>(
value) & ((1U << 10) - 1);
25656 CONSTEXPR NPU_NAMESPACE::cmd_ctrl get_control()
const
25658 return static_cast<NPU_NAMESPACE::cmd_ctrl
>(control);
25662 control =
static_cast<uint8_t
>(
value) & ((1U << 2) - 1);
25667 return static_cast<uint32_t
>(length);
25671 length =
value & ((1U << 20) - 1);
25674#ifdef NPU_DISASSEMBLE
25675 void disassemble(std::vector<std::pair<std::string, std::string>> &fields)
const
25677 fields.push_back(std::make_pair<std::string, std::string>(
"length", std::to_string(length)));
25685#define NPU_OP_STRUCTS \
25689 NPU_OP_(depthwise) \
25691 NPU_OP_(elementwise) \
25692 NPU_OP_(dma_start) \
25693 NPU_OP_(dma_wait) \
25694 NPU_OP_(kernel_wait) \
25697#define NPU_SET_STRUCTS \
25698 NPU_SET_(ifm_pad_top) \
25699 NPU_SET_(ifm_pad_left) \
25700 NPU_SET_(ifm_pad_right) \
25701 NPU_SET_(ifm_pad_bottom) \
25702 NPU_SET_(ifm_depth_m1) \
25703 NPU_SET_(ifm_precision) \
25704 NPU_SET_(ifm_upscale) \
25705 NPU_SET_(ifm_zero_point) \
25706 NPU_SET_(ifm_width0_m1) \
25707 NPU_SET_(ifm_height0_m1) \
25708 NPU_SET_(ifm_height1_m1) \
25709 NPU_SET_(ifm_ib_end) \
25710 NPU_SET_(ifm_region) \
25711 NPU_SET_(ofm_width_m1) \
25712 NPU_SET_(ofm_height_m1) \
25713 NPU_SET_(ofm_depth_m1) \
25714 NPU_SET_(ofm_precision) \
25715 NPU_SET_(ofm_blk_width_m1) \
25716 NPU_SET_(ofm_blk_height_m1) \
25717 NPU_SET_(ofm_blk_depth_m1) \
25718 NPU_SET_(ofm_zero_point) \
25719 NPU_SET_(ofm_width0_m1) \
25720 NPU_SET_(ofm_height0_m1) \
25721 NPU_SET_(ofm_height1_m1) \
25722 NPU_SET_(ofm_region) \
25723 NPU_SET_(kernel_width_m1) \
25724 NPU_SET_(kernel_height_m1) \
25725 NPU_SET_(kernel_stride) \
25726 NPU_SET_(parallel_mode) \
25727 NPU_SET_(acc_format) \
25728 NPU_SET_(activation) \
25729 NPU_SET_(activation_min) \
25730 NPU_SET_(activation_max) \
25731 NPU_SET_(weight_region) \
25732 NPU_SET_(scale_region) \
25733 NPU_SET_(ab_start) \
25734 NPU_SET_(blockdep) \
25735 NPU_SET_(dma0_src_region) \
25736 NPU_SET_(dma0_dst_region) \
25737 NPU_SET_(dma0_size0) \
25738 NPU_SET_(dma0_size1) \
25739 NPU_SET_(ifm2_broadcast) \
25740 NPU_SET_(ifm2_scalar) \
25741 NPU_SET_(ifm2_precision) \
25742 NPU_SET_(ifm2_zero_point) \
25743 NPU_SET_(ifm2_width0_m1) \
25744 NPU_SET_(ifm2_height0_m1) \
25745 NPU_SET_(ifm2_height1_m1) \
25746 NPU_SET_(ifm2_ib_start) \
25747 NPU_SET_(ifm2_region) \
25748 NPU_SET_(ifm_base0) \
25749 NPU_SET_(ifm_base1) \
25750 NPU_SET_(ifm_base2) \
25751 NPU_SET_(ifm_base3) \
25752 NPU_SET_(ifm_stride_x) \
25753 NPU_SET_(ifm_stride_y) \
25754 NPU_SET_(ifm_stride_c) \
25755 NPU_SET_(ofm_base0) \
25756 NPU_SET_(ofm_base1) \
25757 NPU_SET_(ofm_base2) \
25758 NPU_SET_(ofm_base3) \
25759 NPU_SET_(ofm_stride_x) \
25760 NPU_SET_(ofm_stride_y) \
25761 NPU_SET_(ofm_stride_c) \
25762 NPU_SET_(weight_base) \
25763 NPU_SET_(weight_length) \
25764 NPU_SET_(scale_base) \
25765 NPU_SET_(scale_length) \
25766 NPU_SET_(ofm_scale) \
25767 NPU_SET_(opa_scale) \
25768 NPU_SET_(opb_scale) \
25769 NPU_SET_(dma0_src) \
25770 NPU_SET_(dma0_dst) \
25771 NPU_SET_(dma0_len) \
25772 NPU_SET_(dma0_skip0) \
25773 NPU_SET_(dma0_skip1) \
25774 NPU_SET_(ifm2_base0) \
25775 NPU_SET_(ifm2_base1) \
25776 NPU_SET_(ifm2_base2) \
25777 NPU_SET_(ifm2_base3) \
25778 NPU_SET_(ifm2_stride_x) \
25779 NPU_SET_(ifm2_stride_y) \
25780 NPU_SET_(ifm2_stride_c) \
25781 NPU_SET_(weight1_base) \
25782 NPU_SET_(weight1_length) \
25783 NPU_SET_(scale1_base) \
25784 NPU_SET_(scale1_length)
25786#define EXPAND_ACC_FORMAT(FUNC, SEP) FUNC(acc_format, I32) SEP FUNC(acc_format, I40) SEP FUNC(acc_format, F16)
25788#define EXPAND_ACTIVATION_CLIP_RANGE(FUNC, SEP) \
25789 FUNC(activation_clip_range, OFM_PRECISION) \
25790 SEP FUNC(activation_clip_range, FORCE_UINT8) SEP FUNC(activation_clip_range, FORCE_INT8) \
25791 SEP FUNC(activation_clip_range, FORCE_INT16)
25793#define EXPAND_ACTIVATION_FORMAT(FUNC, SEP) FUNC(activation_format, NHWC) SEP FUNC(activation_format, NHCWB16)
25795#define EXPAND_ACTIVATION_FUNCTION(FUNC, SEP) \
25796 FUNC(activation_function, RELU) \
25797 SEP FUNC(activation_function, TANH) SEP FUNC(activation_function, SIGMOID) SEP FUNC(activation_function, TABLE_0) \
25798 SEP FUNC(activation_function, TABLE_1) SEP FUNC(activation_function, TABLE_2) \
25799 SEP FUNC(activation_function, TABLE_3) SEP FUNC(activation_function, TABLE_4) \
25800 SEP FUNC(activation_function, TABLE_5) SEP FUNC(activation_function, TABLE_6) \
25801 SEP FUNC(activation_function, TABLE_7)
25803#define EXPAND_ACTIVATION_PRECISION(FUNC, SEP) \
25804 FUNC(activation_precision, B8) \
25805 SEP FUNC(activation_precision, B16) SEP FUNC(activation_precision, B32) SEP FUNC(activation_precision, B64)
25807#define EXPAND_ACTIVATION_TYPE(FUNC, SEP) FUNC(activation_type, UNSIGNED) SEP FUNC(activation_type, SIGNED)
25809#define EXPAND_AXI_MEM_ENCODING(FUNC, SEP) \
25810 FUNC(axi_mem_encoding, DEVICE_NON_BUFFERABLE) \
25811 SEP FUNC(axi_mem_encoding, DEVICE_BUFFERABLE) SEP FUNC(axi_mem_encoding, NORMAL_NON_CACHEABLE_NON_BUFFERABLE) \
25812 SEP FUNC(axi_mem_encoding, NORMAL_NON_CACHEABLE_BUFFERABLE) \
25813 SEP FUNC(axi_mem_encoding, WRITE_THROUGH_NO_ALLOCATE) \
25814 SEP FUNC(axi_mem_encoding, WRITE_THROUGH_READ_ALLOCATE) \
25815 SEP FUNC(axi_mem_encoding, WRITE_THROUGH_WRITE_ALLOCATE) \
25816 SEP FUNC(axi_mem_encoding, WRITE_THROUGH_READ_AND_WRITE_ALLOCATE) \
25817 SEP FUNC(axi_mem_encoding, WRITE_BACK_NO_ALLOCATE) \
25818 SEP FUNC(axi_mem_encoding, WRITE_BACK_READ_ALLOCATE) \
25819 SEP FUNC(axi_mem_encoding, WRITE_BACK_WRITE_ALLOCATE) \
25820 SEP FUNC(axi_mem_encoding, WRITE_BACK_READ_AND_WRITE_ALLOCATE)
25822#define EXPAND_BROADCAST_MODE(FUNC, SEP) FUNC(broadcast_mode, DISABLE) SEP FUNC(broadcast_mode, ENABLE)
25824#define EXPAND_CMD0_OPCODE(FUNC, SEP) \
25825 FUNC(cmd0_opcode, NPU_OP_STOP) \
25826 SEP FUNC(cmd0_opcode, NPU_OP_IRQ) SEP FUNC(cmd0_opcode, NPU_OP_CONV) SEP FUNC( \
25827 cmd0_opcode, NPU_OP_DEPTHWISE) SEP FUNC(cmd0_opcode, NPU_OP_POOL) SEP FUNC(cmd0_opcode, NPU_OP_ELEMENTWISE) \
25828 SEP FUNC(cmd0_opcode, NPU_OP_DMA_START) SEP FUNC(cmd0_opcode, NPU_OP_DMA_WAIT) SEP FUNC( \
25829 cmd0_opcode, NPU_OP_KERNEL_WAIT) SEP FUNC(cmd0_opcode, NPU_OP_PMU_MASK) SEP FUNC(cmd0_opcode, \
25830 NPU_SET_IFM_PAD_TOP) \
25831 SEP FUNC(cmd0_opcode, NPU_SET_IFM_PAD_LEFT) SEP FUNC(cmd0_opcode, NPU_SET_IFM_PAD_RIGHT) SEP FUNC( \
25832 cmd0_opcode, NPU_SET_IFM_PAD_BOTTOM) SEP FUNC(cmd0_opcode, \
25833 NPU_SET_IFM_DEPTH_M1) SEP FUNC(cmd0_opcode, \
25834 NPU_SET_IFM_PRECISION) \
25835 SEP FUNC(cmd0_opcode, NPU_SET_IFM_UPSCALE) SEP FUNC(cmd0_opcode, NPU_SET_IFM_ZERO_POINT) SEP FUNC( \
25836 cmd0_opcode, NPU_SET_IFM_WIDTH0_M1) SEP FUNC(cmd0_opcode, NPU_SET_IFM_HEIGHT0_M1) \
25837 SEP FUNC(cmd0_opcode, NPU_SET_IFM_HEIGHT1_M1) SEP FUNC(cmd0_opcode, NPU_SET_IFM_IB_END) SEP FUNC( \
25838 cmd0_opcode, NPU_SET_IFM_REGION) SEP FUNC(cmd0_opcode, NPU_SET_OFM_WIDTH_M1) \
25839 SEP FUNC(cmd0_opcode, NPU_SET_OFM_HEIGHT_M1) SEP FUNC(cmd0_opcode, NPU_SET_OFM_DEPTH_M1) \
25840 SEP FUNC(cmd0_opcode, NPU_SET_OFM_PRECISION) SEP FUNC( \
25841 cmd0_opcode, NPU_SET_OFM_BLK_WIDTH_M1) SEP FUNC(cmd0_opcode, \
25842 NPU_SET_OFM_BLK_HEIGHT_M1) \
25843 SEP FUNC(cmd0_opcode, NPU_SET_OFM_BLK_DEPTH_M1) SEP FUNC( \
25844 cmd0_opcode, NPU_SET_OFM_ZERO_POINT) SEP FUNC(cmd0_opcode, NPU_SET_OFM_WIDTH0_M1) \
25845 SEP FUNC(cmd0_opcode, NPU_SET_OFM_HEIGHT0_M1) SEP FUNC( \
25847 NPU_SET_OFM_HEIGHT1_M1) SEP FUNC(cmd0_opcode, NPU_SET_OFM_REGION) \
25848 SEP FUNC(cmd0_opcode, NPU_SET_KERNEL_WIDTH_M1) SEP FUNC( \
25850 NPU_SET_KERNEL_HEIGHT_M1) SEP FUNC(cmd0_opcode, NPU_SET_KERNEL_STRIDE) \
25851 SEP FUNC(cmd0_opcode, NPU_SET_PARALLEL_MODE) SEP FUNC( \
25853 NPU_SET_ACC_FORMAT) SEP FUNC(cmd0_opcode, NPU_SET_ACTIVATION) \
25854 SEP FUNC(cmd0_opcode, \
25855 NPU_SET_ACTIVATION_MIN) SEP FUNC(cmd0_opcode, \
25856 NPU_SET_ACTIVATION_MAX) \
25857 SEP FUNC(cmd0_opcode, NPU_SET_WEIGHT_REGION) SEP FUNC( \
25859 NPU_SET_SCALE_REGION) SEP FUNC(cmd0_opcode, NPU_SET_AB_START) \
25860 SEP FUNC(cmd0_opcode, NPU_SET_BLOCKDEP) \
25861 SEP FUNC(cmd0_opcode, NPU_SET_DMA0_SRC_REGION) SEP FUNC( \
25863 NPU_SET_DMA0_DST_REGION) SEP FUNC(cmd0_opcode, \
25864 NPU_SET_DMA0_SIZE0) \
25865 SEP FUNC(cmd0_opcode, NPU_SET_DMA0_SIZE1) SEP FUNC( \
25867 NPU_SET_IFM2_BROADCAST) SEP \
25868 FUNC(cmd0_opcode, NPU_SET_IFM2_SCALAR) SEP FUNC( \
25870 NPU_SET_IFM2_PRECISION) SEP \
25871 FUNC(cmd0_opcode, NPU_SET_IFM2_ZERO_POINT) SEP \
25872 FUNC(cmd0_opcode, \
25873 NPU_SET_IFM2_WIDTH0_M1) SEP \
25874 FUNC(cmd0_opcode, \
25875 NPU_SET_IFM2_HEIGHT0_M1) SEP \
25876 FUNC(cmd0_opcode, \
25877 NPU_SET_IFM2_HEIGHT1_M1) \
25880 NPU_SET_IFM2_IB_START) \
25883 NPU_SET_IFM2_REGION)
25885#define EXPAND_CMD1_OPCODE(FUNC, SEP) \
25886 FUNC(cmd1_opcode, NPU_SET_IFM_BASE0) \
25887 SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE1) SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE2) \
25888 SEP FUNC(cmd1_opcode, NPU_SET_IFM_BASE3) SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_X) \
25889 SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_Y) SEP FUNC(cmd1_opcode, NPU_SET_IFM_STRIDE_C) SEP FUNC( \
25890 cmd1_opcode, NPU_SET_OFM_BASE0) SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE1) \
25891 SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE2) SEP FUNC(cmd1_opcode, NPU_SET_OFM_BASE3) SEP FUNC( \
25892 cmd1_opcode, NPU_SET_OFM_STRIDE_X) SEP FUNC(cmd1_opcode, NPU_SET_OFM_STRIDE_Y) \
25893 SEP FUNC(cmd1_opcode, NPU_SET_OFM_STRIDE_C) SEP FUNC(cmd1_opcode, NPU_SET_WEIGHT_BASE) SEP FUNC( \
25894 cmd1_opcode, NPU_SET_WEIGHT_LENGTH) SEP FUNC(cmd1_opcode, NPU_SET_SCALE_BASE) \
25895 SEP FUNC(cmd1_opcode, NPU_SET_SCALE_LENGTH) SEP FUNC(cmd1_opcode, NPU_SET_OFM_SCALE) \
25896 SEP FUNC(cmd1_opcode, NPU_SET_OPA_SCALE) SEP FUNC(cmd1_opcode, NPU_SET_OPB_SCALE) \
25897 SEP FUNC(cmd1_opcode, NPU_SET_DMA0_SRC) SEP FUNC(cmd1_opcode, NPU_SET_DMA0_DST) \
25898 SEP FUNC(cmd1_opcode, NPU_SET_DMA0_LEN) SEP FUNC(cmd1_opcode, NPU_SET_DMA0_SKIP0) \
25899 SEP FUNC(cmd1_opcode, NPU_SET_DMA0_SKIP1) SEP FUNC( \
25900 cmd1_opcode, NPU_SET_IFM2_BASE0) SEP FUNC(cmd1_opcode, NPU_SET_IFM2_BASE1) \
25901 SEP FUNC(cmd1_opcode, NPU_SET_IFM2_BASE2) SEP FUNC(cmd1_opcode, \
25902 NPU_SET_IFM2_BASE3) \
25903 SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_X) \
25904 SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_Y) \
25905 SEP FUNC(cmd1_opcode, NPU_SET_IFM2_STRIDE_C) \
25906 SEP FUNC(cmd1_opcode, NPU_SET_WEIGHT1_BASE) \
25907 SEP FUNC(cmd1_opcode, NPU_SET_WEIGHT1_LENGTH) \
25908 SEP FUNC(cmd1_opcode, NPU_SET_SCALE1_BASE) \
25909 SEP FUNC(cmd1_opcode, NPU_SET_SCALE1_LENGTH)
25911#define EXPAND_CMD_CTRL(FUNC, SEP) FUNC(cmd_ctrl, CMD0_CTRL) SEP FUNC(cmd_ctrl, CMD1_CTRL)
25913#define EXPAND_CUSTOM_DMA(FUNC, SEP) FUNC(custom_dma, NOT_IMPLEMENTED) SEP FUNC(custom_dma, IMPLEMENTED)
25915#define EXPAND_DMA_FAULT_SRC(FUNC, SEP) FUNC(dma_fault_src, AXI_M0) SEP FUNC(dma_fault_src, AXI_M1)
25917#define EXPAND_DMA_REGION_MODE(FUNC, SEP) FUNC(dma_region_mode, EXTERNAL) SEP FUNC(dma_region_mode, INTERNAL)
25919#define EXPAND_DMA_STRIDE_MODE(FUNC, SEP) \
25920 FUNC(dma_stride_mode, D1) SEP FUNC(dma_stride_mode, D2) SEP FUNC(dma_stride_mode, D3)
25922#define EXPAND_ELEMENTWISE_MODE(FUNC, SEP) \
25923 FUNC(elementwise_mode, MUL) \
25924 SEP FUNC(elementwise_mode, ADD) SEP FUNC(elementwise_mode, SUB) SEP FUNC(elementwise_mode, MIN) \
25925 SEP FUNC(elementwise_mode, MAX) SEP FUNC(elementwise_mode, LRELU) SEP FUNC(elementwise_mode, ABS) \
25926 SEP FUNC(elementwise_mode, CLZ) SEP FUNC(elementwise_mode, SHR) SEP FUNC(elementwise_mode, SHL)
25928#define EXPAND_FUNCTIONAL_SAFETY(FUNC, SEP) \
25929 FUNC(functional_safety, NOT_IMPLEMENTED) SEP FUNC(functional_safety, IMPLEMENTED)
25931#define EXPAND_IFM2_OPERAND_ORDER(FUNC, SEP) FUNC(ifm2_operand_order, ORDER_B) SEP FUNC(ifm2_operand_order, ORDER_A)
25933#define EXPAND_IFM_SCALE_MODE(FUNC, SEP) \
25934 FUNC(ifm_scale_mode, OPA_OPB_16) SEP FUNC(ifm_scale_mode, OPA_32) SEP FUNC(ifm_scale_mode, OPB_32)
25936#define EXPAND_IFM_UPSCALE_MODE(FUNC, SEP) \
25937 FUNC(ifm_upscale_mode, NONE) SEP FUNC(ifm_upscale_mode, NEAREST) SEP FUNC(ifm_upscale_mode, ZEROS)
25939#define EXPAND_KERNEL_DECOMPOSITION(FUNC, SEP) FUNC(kernel_decomposition, D8X8) SEP FUNC(kernel_decomposition, D4X4)
25941#define EXPAND_KERNEL_DILATION(FUNC, SEP) FUNC(kernel_dilation, NONE) SEP FUNC(kernel_dilation, X2)
25943#define EXPAND_MAX_BEATS(FUNC, SEP) FUNC(max_beats, B64) SEP FUNC(max_beats, B128) SEP FUNC(max_beats, B256)
25945#define EXPAND_MEM_ATTR(FUNC, SEP) \
25946 FUNC(mem_attr, AXI0_OUTSTANDING_COUNTER0) \
25947 SEP FUNC(mem_attr, AXI0_OUTSTANDING_COUNTER1) SEP FUNC(mem_attr, AXI1_OUTSTANDING_COUNTER2) \
25948 SEP FUNC(mem_attr, AXI1_OUTSTANDING_COUNTER3)
25950#define EXPAND_OFM_SCALE_MODE(FUNC, SEP) FUNC(ofm_scale_mode, PER_CHANNEL) SEP FUNC(ofm_scale_mode, GLOBAL)
25952#define EXPAND_PARALLEL_MODE(FUNC, SEP) FUNC(parallel_mode, SINGLE_CORE) SEP FUNC(parallel_mode, DUAL_CORE_DEPTH)
25954#define EXPAND_PMU_AXI_CHANNEL(FUNC, SEP) \
25955 FUNC(pmu_axi_channel, RD_CMD) \
25956 SEP FUNC(pmu_axi_channel, RD_IFM) SEP FUNC(pmu_axi_channel, RD_WEIGHTS) SEP FUNC(pmu_axi_channel, RD_SCALE_BIAS) \
25957 SEP FUNC(pmu_axi_channel, RD_MEM2MEM) SEP FUNC(pmu_axi_channel, WR_OFM) SEP FUNC(pmu_axi_channel, WR_MEM2MEM)
25959#define EXPAND_PMU_EVENT(FUNC, SEP) \
25960 FUNC(pmu_event, NO_EVENT) \
25961 SEP FUNC(pmu_event, CYCLE) SEP FUNC(pmu_event, NPU_IDLE) SEP FUNC(pmu_event, CC_STALLED_ON_BLOCKDEP) SEP FUNC( \
25962 pmu_event, CC_STALLED_ON_SHRAM_RECONFIG) SEP FUNC(pmu_event, NPU_ACTIVE) SEP FUNC(pmu_event, MAC_ACTIVE) \
25963 SEP FUNC(pmu_event, MAC_ACTIVE_8BIT) SEP FUNC(pmu_event, MAC_ACTIVE_16BIT) SEP FUNC( \
25964 pmu_event, MAC_DPU_ACTIVE) SEP FUNC(pmu_event, MAC_STALLED_BY_WD_ACC) SEP FUNC(pmu_event, \
25965 MAC_STALLED_BY_WD) \
25966 SEP FUNC(pmu_event, MAC_STALLED_BY_ACC) SEP FUNC(pmu_event, MAC_STALLED_BY_IB) SEP FUNC( \
25968 MAC_ACTIVE_32BIT) SEP FUNC(pmu_event, \
25969 MAC_STALLED_BY_INT_W) SEP FUNC(pmu_event, \
25970 MAC_STALLED_BY_INT_ACC) SEP FUNC(pmu_event, \
25972 SEP FUNC(pmu_event, AO_ACTIVE_8BIT) SEP FUNC(pmu_event, AO_ACTIVE_16BIT) SEP FUNC( \
25973 pmu_event, AO_STALLED_BY_OFMP_OB) SEP FUNC(pmu_event, AO_STALLED_BY_OFMP) SEP \
25974 FUNC(pmu_event, AO_STALLED_BY_OB) SEP FUNC(pmu_event, AO_STALLED_BY_ACC_IB) SEP FUNC( \
25975 pmu_event, AO_STALLED_BY_ACC) SEP FUNC(pmu_event, AO_STALLED_BY_IB) SEP \
25976 FUNC(pmu_event, WD_ACTIVE) SEP FUNC(pmu_event, WD_STALLED) SEP FUNC(pmu_event, WD_STALLED_BY_WS) SEP FUNC( \
25977 pmu_event, WD_STALLED_BY_WD_BUF) SEP FUNC(pmu_event, \
25978 WD_PARSE_ACTIVE) SEP \
25979 FUNC(pmu_event, WD_PARSE_STALLED) SEP FUNC(pmu_event, WD_PARSE_STALLED_IN) SEP FUNC( \
25980 pmu_event, WD_PARSE_STALLED_OUT) SEP FUNC(pmu_event, \
25982 FUNC(pmu_event, WD_TRANS_WB) SEP FUNC(pmu_event, WD_TRANS_DW0) SEP FUNC( \
25983 pmu_event, WD_TRANS_DW1) SEP FUNC(pmu_event, \
25984 AXI0_RD_TRANS_ACCEPTED) SEP \
25985 FUNC(pmu_event, AXI0_RD_TRANS_COMPLETED) SEP FUNC(pmu_event, AXI0_RD_DATA_BEAT_RECEIVED) SEP FUNC( \
25986 pmu_event, AXI0_RD_TRAN_REQ_STALLED) SEP FUNC(pmu_event, \
25987 AXI0_WR_TRANS_ACCEPTED) SEP \
25988 FUNC(pmu_event, AXI0_WR_TRANS_COMPLETED_M) SEP FUNC( \
25989 pmu_event, AXI0_WR_TRANS_COMPLETED_S) SEP \
25990 FUNC(pmu_event, AXI0_WR_DATA_BEAT_WRITTEN) SEP FUNC( \
25991 pmu_event, AXI0_WR_TRAN_REQ_STALLED) SEP \
25992 FUNC(pmu_event, AXI0_WR_DATA_BEAT_STALLED) SEP FUNC( \
25994 AXI0_ENABLED_CYCLES) SEP FUNC(pmu_event, \
25995 AXI0_RD_STALL_LIMIT) SEP \
25996 FUNC(pmu_event, AXI0_WR_STALL_LIMIT) SEP FUNC( \
25998 AXI_LATENCY_ANY) SEP FUNC(pmu_event, \
25999 AXI_LATENCY_32) SEP \
26001 AXI_LATENCY_64) SEP FUNC(pmu_event, \
26002 AXI_LATENCY_128) SEP \
26003 FUNC(pmu_event, AXI_LATENCY_256) SEP FUNC( \
26005 AXI_LATENCY_512) SEP FUNC(pmu_event, \
26006 AXI_LATENCY_1024) SEP \
26007 FUNC(pmu_event, ECC_DMA) SEP FUNC( \
26009 ECC_SB0) SEP FUNC(pmu_event, \
26010 AXI1_RD_TRANS_ACCEPTED) SEP \
26011 FUNC(pmu_event, AXI1_RD_TRANS_COMPLETED) SEP FUNC( \
26012 pmu_event, AXI1_RD_DATA_BEAT_RECEIVED) SEP \
26013 FUNC(pmu_event, AXI1_RD_TRAN_REQ_STALLED) SEP FUNC( \
26014 pmu_event, AXI1_WR_TRANS_ACCEPTED) SEP \
26015 FUNC(pmu_event, AXI1_WR_TRANS_COMPLETED_M) SEP FUNC( \
26017 AXI1_WR_TRANS_COMPLETED_S) SEP \
26019 AXI1_WR_DATA_BEAT_WRITTEN) SEP \
26021 AXI1_WR_TRAN_REQ_STALLED) SEP \
26024 AXI1_WR_DATA_BEAT_STALLED) SEP \
26027 AXI1_ENABLED_CYCLES) SEP \
26030 AXI1_RD_STALL_LIMIT) SEP \
26033 AXI1_WR_STALL_LIMIT) \
26038#define EXPAND_POOLING_MODE(FUNC, SEP) \
26039 FUNC(pooling_mode, MAX) SEP FUNC(pooling_mode, AVERAGE) SEP FUNC(pooling_mode, REDUCE_SUM)
26041#define EXPAND_PRIVILEGE_LEVEL(FUNC, SEP) FUNC(privilege_level, USER) SEP FUNC(privilege_level, PRIVILEGED)
26043#define EXPAND_ROUND_MODE(FUNC, SEP) FUNC(round_mode, DBL) SEP FUNC(round_mode, TRUNCATE) SEP FUNC(round_mode, NATURAL)
26045#define EXPAND_SECURITY_LEVEL(FUNC, SEP) FUNC(security_level, SECURE) SEP FUNC(security_level, NON_SECURE)
26047#define EXPAND_STATE(FUNC, SEP) FUNC(state, STOPPED) SEP FUNC(state, RUNNING)
26049#define EXPAND_WD_CORE_SLICE_STATE(FUNC, SEP) \
26050 FUNC(wd_core_slice_state, HEADER) SEP FUNC(wd_core_slice_state, PALETTE) SEP FUNC(wd_core_slice_state, WEIGHTS)
26052#define EXPAND_WD_CTRL_STATE(FUNC, SEP) \
26053 FUNC(wd_ctrl_state, IDLE) \
26054 SEP FUNC(wd_ctrl_state, DRAIN) SEP FUNC(wd_ctrl_state, OFD_INIT) SEP FUNC(wd_ctrl_state, OFD_RUN)
26056#define EXPAND_WEIGHT_ORDER(FUNC, SEP) FUNC(weight_order, DEPTH_FIRST) SEP FUNC(weight_order, PART_KERNEL_FIRST)
#define MAX(A, B)
Definition arm_nnsupportfunctions.h:48
#define MIN(A, B)
Definition arm_nnsupportfunctions.h:49
int offset
Definition mirror_pad.cpp:27
int zero_point
Definition batch_matmul_test.cc:45
float scale
Definition batch_matmul_test.cc:44
#define max(a, b)
Definition common_functions.h:29
kernel_dilation
Definition ethosu55_interface.h:1069
@ KERNEL_DILATION_NONE
Definition ethosu55_interface.h:1070
@ KERNEL_DILATION_X2
Definition ethosu55_interface.h:1071
privilege_level
Definition ethosu55_interface.h:1192
@ PRIVILEGE_LEVEL_USER
Definition ethosu55_interface.h:1193
@ PRIVILEGE_LEVEL_PRIVILEGED
Definition ethosu55_interface.h:1194
ifm2_operand_order
Definition ethosu55_interface.h:1043
@ IFM2_OPERAND_ORDER_ORDER_A
Definition ethosu55_interface.h:1045
@ IFM2_OPERAND_ORDER_ORDER_B
Definition ethosu55_interface.h:1044
wd_ctrl_state
Definition ethosu55_interface.h:1224
@ WD_CTRL_STATE_IDLE
Definition ethosu55_interface.h:1225
@ WD_CTRL_STATE_DRAIN
Definition ethosu55_interface.h:1226
@ WD_CTRL_STATE_OFD_RUN
Definition ethosu55_interface.h:1228
@ WD_CTRL_STATE_OFD_INIT
Definition ethosu55_interface.h:1227
weight_order
Definition ethosu55_interface.h:1232
@ WEIGHT_ORDER_DEPTH_FIRST
Definition ethosu55_interface.h:1233
@ WEIGHT_ORDER_PART_KERNEL_FIRST
Definition ethosu55_interface.h:1234
dma_region_mode
Definition ethosu55_interface.h:1012
@ DMA_REGION_MODE_INTERNAL
Definition ethosu55_interface.h:1014
@ DMA_REGION_MODE_EXTERNAL
Definition ethosu55_interface.h:1013
round_mode
Definition ethosu55_interface.h:1198
@ ROUND_MODE_DBL
Definition ethosu55_interface.h:1199
@ ROUND_MODE_TRUNCATE
Definition ethosu55_interface.h:1200
@ ROUND_MODE_NATURAL
Definition ethosu55_interface.h:1201
security_level
Definition ethosu55_interface.h:1205
@ SECURITY_LEVEL_NON_SECURE
Definition ethosu55_interface.h:1207
@ SECURITY_LEVEL_SECURE
Definition ethosu55_interface.h:1206
activation_format
Definition ethosu55_interface.h:825
@ ACTIVATION_FORMAT_NHWC
Definition ethosu55_interface.h:826
@ ACTIVATION_FORMAT_NHCWB16
Definition ethosu55_interface.h:827
pooling_mode
Definition ethosu55_interface.h:1185
@ POOLING_MODE_AVERAGE
Definition ethosu55_interface.h:1187
@ POOLING_MODE_MAX
Definition ethosu55_interface.h:1186
@ POOLING_MODE_REDUCE_SUM
Definition ethosu55_interface.h:1188
cmd0_opcode
Definition ethosu55_interface.h:882
@ CMD0_OPCODE_NPU_SET_IFM_PRECISION
Definition ethosu55_interface.h:898
@ CMD0_OPCODE_NPU_SET_ACTIVATION_MIN
Definition ethosu55_interface.h:923
@ CMD0_OPCODE_NPU_OP_POOL
Definition ethosu55_interface.h:887
@ CMD0_OPCODE_NPU_SET_OFM_WIDTH_M1
Definition ethosu55_interface.h:906
@ CMD0_OPCODE_NPU_SET_KERNEL_WIDTH_M1
Definition ethosu55_interface.h:918
@ CMD0_OPCODE_NPU_SET_IFM2_SCALAR
Definition ethosu55_interface.h:934
@ CMD0_OPCODE_NPU_SET_IFM_DEPTH_M1
Definition ethosu55_interface.h:897
@ CMD0_OPCODE_NPU_OP_IRQ
Definition ethosu55_interface.h:884
@ CMD0_OPCODE_NPU_SET_DMA0_SRC_REGION
Definition ethosu55_interface.h:929
@ CMD0_OPCODE_NPU_SET_KERNEL_HEIGHT_M1
Definition ethosu55_interface.h:919
@ CMD0_OPCODE_NPU_SET_IFM2_ZERO_POINT
Definition ethosu55_interface.h:936
@ CMD0_OPCODE_NPU_SET_OFM_HEIGHT0_M1
Definition ethosu55_interface.h:915
@ CMD0_OPCODE_NPU_SET_IFM_PAD_BOTTOM
Definition ethosu55_interface.h:896
@ CMD0_OPCODE_NPU_SET_KERNEL_STRIDE
Definition ethosu55_interface.h:920
@ CMD0_OPCODE_NPU_SET_IFM_UPSCALE
Definition ethosu55_interface.h:899
@ CMD0_OPCODE_NPU_SET_OFM_BLK_WIDTH_M1
Definition ethosu55_interface.h:910
@ CMD0_OPCODE_NPU_OP_PMU_MASK
Definition ethosu55_interface.h:892
@ CMD0_OPCODE_NPU_SET_IFM2_PRECISION
Definition ethosu55_interface.h:935
@ CMD0_OPCODE_NPU_SET_OFM_HEIGHT1_M1
Definition ethosu55_interface.h:916
@ CMD0_OPCODE_NPU_OP_ELEMENTWISE
Definition ethosu55_interface.h:888
@ CMD0_OPCODE_NPU_SET_ACTIVATION
Definition ethosu55_interface.h:922
@ CMD0_OPCODE_NPU_SET_OFM_DEPTH_M1
Definition ethosu55_interface.h:908
@ CMD0_OPCODE_NPU_SET_OFM_WIDTH0_M1
Definition ethosu55_interface.h:914
@ CMD0_OPCODE_NPU_SET_IFM2_BROADCAST
Definition ethosu55_interface.h:933
@ CMD0_OPCODE_NPU_SET_IFM_PAD_TOP
Definition ethosu55_interface.h:893
@ CMD0_OPCODE_NPU_SET_IFM2_REGION
Definition ethosu55_interface.h:941
@ CMD0_OPCODE_NPU_OP_STOP
Definition ethosu55_interface.h:883
@ CMD0_OPCODE_NPU_SET_IFM_HEIGHT1_M1
Definition ethosu55_interface.h:903
@ CMD0_OPCODE_NPU_SET_IFM_HEIGHT0_M1
Definition ethosu55_interface.h:902
@ CMD0_OPCODE_NPU_SET_BLOCKDEP
Definition ethosu55_interface.h:928
@ CMD0_OPCODE_NPU_SET_OFM_BLK_DEPTH_M1
Definition ethosu55_interface.h:912
@ CMD0_OPCODE_NPU_SET_IFM_WIDTH0_M1
Definition ethosu55_interface.h:901
@ CMD0_OPCODE_NPU_SET_AB_START
Definition ethosu55_interface.h:927
@ CMD0_OPCODE_NPU_SET_ACTIVATION_MAX
Definition ethosu55_interface.h:924
@ CMD0_OPCODE_NPU_SET_DMA0_SIZE1
Definition ethosu55_interface.h:932
@ CMD0_OPCODE_NPU_SET_DMA0_DST_REGION
Definition ethosu55_interface.h:930
@ CMD0_OPCODE_NPU_SET_IFM2_HEIGHT1_M1
Definition ethosu55_interface.h:939
@ CMD0_OPCODE_NPU_SET_SCALE_REGION
Definition ethosu55_interface.h:926
@ CMD0_OPCODE_NPU_SET_IFM2_WIDTH0_M1
Definition ethosu55_interface.h:937
@ CMD0_OPCODE_NPU_SET_DMA0_SIZE0
Definition ethosu55_interface.h:931
@ CMD0_OPCODE_NPU_SET_WEIGHT_REGION
Definition ethosu55_interface.h:925
@ CMD0_OPCODE_NPU_SET_OFM_PRECISION
Definition ethosu55_interface.h:909
@ CMD0_OPCODE_NPU_SET_IFM_ZERO_POINT
Definition ethosu55_interface.h:900
@ CMD0_OPCODE_NPU_SET_IFM_PAD_RIGHT
Definition ethosu55_interface.h:895
@ CMD0_OPCODE_NPU_SET_OFM_HEIGHT_M1
Definition ethosu55_interface.h:907
@ CMD0_OPCODE_NPU_SET_IFM_PAD_LEFT
Definition ethosu55_interface.h:894
@ CMD0_OPCODE_NPU_SET_ACC_FORMAT
Definition ethosu55_interface.h:921
@ CMD0_OPCODE_NPU_OP_DEPTHWISE
Definition ethosu55_interface.h:886
@ CMD0_OPCODE_NPU_SET_IFM_IB_END
Definition ethosu55_interface.h:904
@ CMD0_OPCODE_NPU_SET_OFM_REGION
Definition ethosu55_interface.h:917
@ CMD0_OPCODE_NPU_OP_DMA_START
Definition ethosu55_interface.h:889
@ CMD0_OPCODE_NPU_OP_CONV
Definition ethosu55_interface.h:885
@ CMD0_OPCODE_NPU_SET_IFM2_HEIGHT0_M1
Definition ethosu55_interface.h:938
@ CMD0_OPCODE_NPU_SET_OFM_BLK_HEIGHT_M1
Definition ethosu55_interface.h:911
@ CMD0_OPCODE_NPU_SET_IFM2_IB_START
Definition ethosu55_interface.h:940
@ CMD0_OPCODE_NPU_SET_OFM_ZERO_POINT
Definition ethosu55_interface.h:913
@ CMD0_OPCODE_NPU_SET_IFM_REGION
Definition ethosu55_interface.h:905
@ CMD0_OPCODE_NPU_OP_DMA_WAIT
Definition ethosu55_interface.h:890
@ CMD0_OPCODE_NPU_OP_KERNEL_WAIT
Definition ethosu55_interface.h:891
custom_dma
Definition ethosu55_interface.h:1000
@ CUSTOM_DMA_NOT_IMPLEMENTED
Definition ethosu55_interface.h:1001
@ CUSTOM_DMA_IMPLEMENTED
Definition ethosu55_interface.h:1002
pmu_axi_channel
Definition ethosu55_interface.h:1096
@ PMU_AXI_CHANNEL_RD_MEM2MEM
Definition ethosu55_interface.h:1101
@ PMU_AXI_CHANNEL_RD_WEIGHTS
Definition ethosu55_interface.h:1099
@ PMU_AXI_CHANNEL_RD_CMD
Definition ethosu55_interface.h:1097
@ PMU_AXI_CHANNEL_WR_MEM2MEM
Definition ethosu55_interface.h:1103
@ PMU_AXI_CHANNEL_RD_SCALE_BIAS
Definition ethosu55_interface.h:1100
@ PMU_AXI_CHANNEL_RD_IFM
Definition ethosu55_interface.h:1098
@ PMU_AXI_CHANNEL_WR_OFM
Definition ethosu55_interface.h:1102
dma_stride_mode
Definition ethosu55_interface.h:1018
@ DMA_STRIDE_MODE_D1
Definition ethosu55_interface.h:1019
#define STRUCT
Definition ethosu55_interface.h:36
activation_type
Definition ethosu55_interface.h:854
@ ACTIVATION_TYPE_SIGNED
Definition ethosu55_interface.h:856
@ ACTIVATION_TYPE_UNSIGNED
Definition ethosu55_interface.h:855
activation_clip_range
Definition ethosu55_interface.h:817
@ ACTIVATION_CLIP_RANGE_FORCE_INT16
Definition ethosu55_interface.h:821
@ ACTIVATION_CLIP_RANGE_FORCE_UINT8
Definition ethosu55_interface.h:819
@ ACTIVATION_CLIP_RANGE_OFM_PRECISION
Definition ethosu55_interface.h:818
@ ACTIVATION_CLIP_RANGE_FORCE_INT8
Definition ethosu55_interface.h:820
cmd_ctrl
Definition ethosu55_interface.h:988
@ CMD_CTRL_CMD1_CTRL
Definition ethosu55_interface.h:990
@ CMD_CTRL_CMD0_CTRL
Definition ethosu55_interface.h:989
activation_function
Definition ethosu55_interface.h:831
@ ACTIVATION_FUNCTION_TABLE_7
Definition ethosu55_interface.h:842
@ ACTIVATION_FUNCTION_TABLE_4
Definition ethosu55_interface.h:839
@ ACTIVATION_FUNCTION_RELU
Definition ethosu55_interface.h:832
@ ACTIVATION_FUNCTION_TABLE_2
Definition ethosu55_interface.h:837
@ ACTIVATION_FUNCTION_TABLE_1
Definition ethosu55_interface.h:836
@ ACTIVATION_FUNCTION_TANH
Definition ethosu55_interface.h:833
@ ACTIVATION_FUNCTION_TABLE_6
Definition ethosu55_interface.h:841
@ ACTIVATION_FUNCTION_SIGMOID
Definition ethosu55_interface.h:834
@ ACTIVATION_FUNCTION_TABLE_0
Definition ethosu55_interface.h:835
@ ACTIVATION_FUNCTION_TABLE_3
Definition ethosu55_interface.h:838
@ ACTIVATION_FUNCTION_TABLE_5
Definition ethosu55_interface.h:840
mem_attr
Definition ethosu55_interface.h:1082
@ MEM_ATTR_AXI1_OUTSTANDING_COUNTER3
Definition ethosu55_interface.h:1086
@ MEM_ATTR_AXI0_OUTSTANDING_COUNTER1
Definition ethosu55_interface.h:1084
@ MEM_ATTR_AXI0_OUTSTANDING_COUNTER0
Definition ethosu55_interface.h:1083
@ MEM_ATTR_AXI1_OUTSTANDING_COUNTER2
Definition ethosu55_interface.h:1085
activation_precision
Definition ethosu55_interface.h:846
@ ACTIVATION_PRECISION_B64
Definition ethosu55_interface.h:850
@ ACTIVATION_PRECISION_B32
Definition ethosu55_interface.h:849
@ ACTIVATION_PRECISION_B16
Definition ethosu55_interface.h:848
@ ACTIVATION_PRECISION_B8
Definition ethosu55_interface.h:847
broadcast_mode
Definition ethosu55_interface.h:876
@ BROADCAST_MODE_DISABLE
Definition ethosu55_interface.h:877
@ BROADCAST_MODE_ENABLE
Definition ethosu55_interface.h:878
pmu_event
Definition ethosu55_interface.h:1107
@ PMU_EVENT_AXI0_WR_TRANS_ACCEPTED
Definition ethosu55_interface.h:1150
@ PMU_EVENT_MAC_STALLED_BY_ACC
Definition ethosu55_interface.h:1120
@ PMU_EVENT_MAC_ACTIVE_32BIT
Definition ethosu55_interface.h:1122
@ PMU_EVENT_AXI_LATENCY_ANY
Definition ethosu55_interface.h:1159
@ PMU_EVENT_AXI0_WR_DATA_BEAT_WRITTEN
Definition ethosu55_interface.h:1153
@ PMU_EVENT_MAC_ACTIVE
Definition ethosu55_interface.h:1114
@ PMU_EVENT_AXI1_RD_TRAN_REQ_STALLED
Definition ethosu55_interface.h:1171
@ PMU_EVENT_AXI0_RD_STALL_LIMIT
Definition ethosu55_interface.h:1157
@ PMU_EVENT_AXI1_WR_DATA_BEAT_WRITTEN
Definition ethosu55_interface.h:1175
@ PMU_EVENT_AXI0_RD_TRANS_COMPLETED
Definition ethosu55_interface.h:1147
@ PMU_EVENT_ECC_DMA
Definition ethosu55_interface.h:1166
@ PMU_EVENT_WD_TRANS_WS
Definition ethosu55_interface.h:1142
@ PMU_EVENT_WD_PARSE_STALLED_OUT
Definition ethosu55_interface.h:1141
@ PMU_EVENT_MAC_STALLED_BY_WD
Definition ethosu55_interface.h:1119
@ PMU_EVENT_WD_STALLED
Definition ethosu55_interface.h:1135
@ PMU_EVENT_AXI1_RD_STALL_LIMIT
Definition ethosu55_interface.h:1179
@ PMU_EVENT_MAC_ACTIVE_8BIT
Definition ethosu55_interface.h:1115
@ PMU_EVENT_MAC_ACTIVE_16BIT
Definition ethosu55_interface.h:1116
@ PMU_EVENT_NO_EVENT
Definition ethosu55_interface.h:1108
@ PMU_EVENT_AXI1_WR_TRANS_COMPLETED_S
Definition ethosu55_interface.h:1174
@ PMU_EVENT_WD_PARSE_STALLED_IN
Definition ethosu55_interface.h:1140
@ PMU_EVENT_AO_STALLED_BY_ACC_IB
Definition ethosu55_interface.h:1131
@ PMU_EVENT_MAC_STALLED_BY_IB
Definition ethosu55_interface.h:1121
@ PMU_EVENT_CYCLE
Definition ethosu55_interface.h:1109
@ PMU_EVENT_WD_TRANS_WB
Definition ethosu55_interface.h:1143
@ PMU_EVENT_WD_PARSE_ACTIVE
Definition ethosu55_interface.h:1138
@ PMU_EVENT_AXI1_WR_TRANS_COMPLETED_M
Definition ethosu55_interface.h:1173
@ PMU_EVENT_WD_STALLED_BY_WD_BUF
Definition ethosu55_interface.h:1137
@ PMU_EVENT_WD_STALLED_BY_WS
Definition ethosu55_interface.h:1136
@ PMU_EVENT_AXI_LATENCY_64
Definition ethosu55_interface.h:1161
@ PMU_EVENT_AXI_LATENCY_512
Definition ethosu55_interface.h:1164
@ PMU_EVENT_AO_STALLED_BY_OFMP
Definition ethosu55_interface.h:1129
@ PMU_EVENT_NPU_ACTIVE
Definition ethosu55_interface.h:1113
@ PMU_EVENT_AXI1_RD_TRANS_COMPLETED
Definition ethosu55_interface.h:1169
@ PMU_EVENT_AXI1_ENABLED_CYCLES
Definition ethosu55_interface.h:1178
@ PMU_EVENT_AXI1_WR_TRAN_REQ_STALLED
Definition ethosu55_interface.h:1176
@ PMU_EVENT_AO_STALLED_BY_IB
Definition ethosu55_interface.h:1133
@ PMU_EVENT_AXI0_WR_TRAN_REQ_STALLED
Definition ethosu55_interface.h:1154
@ PMU_EVENT_AXI0_WR_TRANS_COMPLETED_S
Definition ethosu55_interface.h:1152
@ PMU_EVENT_NPU_IDLE
Definition ethosu55_interface.h:1110
@ PMU_EVENT_AXI_LATENCY_1024
Definition ethosu55_interface.h:1165
@ PMU_EVENT_AXI0_RD_TRAN_REQ_STALLED
Definition ethosu55_interface.h:1149
@ PMU_EVENT_AXI1_RD_TRANS_ACCEPTED
Definition ethosu55_interface.h:1168
@ PMU_EVENT_AXI0_WR_TRANS_COMPLETED_M
Definition ethosu55_interface.h:1151
@ PMU_EVENT_AXI0_RD_TRANS_ACCEPTED
Definition ethosu55_interface.h:1146
@ PMU_EVENT_ECC_SB0
Definition ethosu55_interface.h:1167
@ PMU_EVENT_CC_STALLED_ON_BLOCKDEP
Definition ethosu55_interface.h:1111
@ PMU_EVENT_AO_ACTIVE_8BIT
Definition ethosu55_interface.h:1126
@ PMU_EVENT_CC_STALLED_ON_SHRAM_RECONFIG
Definition ethosu55_interface.h:1112
@ PMU_EVENT_AO_ACTIVE_16BIT
Definition ethosu55_interface.h:1127
@ PMU_EVENT_AXI0_WR_DATA_BEAT_STALLED
Definition ethosu55_interface.h:1155
@ PMU_EVENT_AXI1_WR_STALL_LIMIT
Definition ethosu55_interface.h:1180
@ PMU_EVENT_AXI1_WR_DATA_BEAT_STALLED
Definition ethosu55_interface.h:1177
@ PMU_EVENT_AXI0_WR_STALL_LIMIT
Definition ethosu55_interface.h:1158
@ PMU_EVENT_AXI0_ENABLED_CYCLES
Definition ethosu55_interface.h:1156
@ PMU_EVENT_AO_STALLED_BY_OB
Definition ethosu55_interface.h:1130
@ PMU_EVENT_MAC_STALLED_BY_INT_ACC
Definition ethosu55_interface.h:1124
@ PMU_EVENT_AO_STALLED_BY_OFMP_OB
Definition ethosu55_interface.h:1128
@ PMU_EVENT_AXI_LATENCY_256
Definition ethosu55_interface.h:1163
@ PMU_EVENT_ECC_SB1
Definition ethosu55_interface.h:1181
@ PMU_EVENT_MAC_DPU_ACTIVE
Definition ethosu55_interface.h:1117
@ PMU_EVENT_AXI_LATENCY_128
Definition ethosu55_interface.h:1162
@ PMU_EVENT_AXI1_RD_DATA_BEAT_RECEIVED
Definition ethosu55_interface.h:1170
@ PMU_EVENT_WD_ACTIVE
Definition ethosu55_interface.h:1134
@ PMU_EVENT_WD_PARSE_STALLED
Definition ethosu55_interface.h:1139
@ PMU_EVENT_MAC_STALLED_BY_INT_W
Definition ethosu55_interface.h:1123
@ PMU_EVENT_WD_TRANS_DW0
Definition ethosu55_interface.h:1144
@ PMU_EVENT_AXI1_WR_TRANS_ACCEPTED
Definition ethosu55_interface.h:1172
@ PMU_EVENT_WD_TRANS_DW1
Definition ethosu55_interface.h:1145
@ PMU_EVENT_MAC_STALLED_BY_WD_ACC
Definition ethosu55_interface.h:1118
@ PMU_EVENT_AO_STALLED_BY_ACC
Definition ethosu55_interface.h:1132
@ PMU_EVENT_AO_ACTIVE
Definition ethosu55_interface.h:1125
@ PMU_EVENT_AXI0_RD_DATA_BEAT_RECEIVED
Definition ethosu55_interface.h:1148
@ PMU_EVENT_AXI_LATENCY_32
Definition ethosu55_interface.h:1160
wd_core_slice_state
Definition ethosu55_interface.h:1217
@ WD_CORE_SLICE_STATE_PALETTE
Definition ethosu55_interface.h:1219
@ WD_CORE_SLICE_STATE_WEIGHTS
Definition ethosu55_interface.h:1220
@ WD_CORE_SLICE_STATE_HEADER
Definition ethosu55_interface.h:1218
ofm_scale_mode
Definition ethosu55_interface.h:1090
@ OFM_SCALE_MODE_GLOBAL
Definition ethosu55_interface.h:1092
@ OFM_SCALE_MODE_PER_CHANNEL
Definition ethosu55_interface.h:1091
ifm_scale_mode
Definition ethosu55_interface.h:1049
@ IFM_SCALE_MODE_OPA_OPB_16
Definition ethosu55_interface.h:1050
@ IFM_SCALE_MODE_OPA_32
Definition ethosu55_interface.h:1051
@ IFM_SCALE_MODE_OPB_32
Definition ethosu55_interface.h:1052
acc_format
Definition ethosu55_interface.h:810
@ ACC_FORMAT_I40
Definition ethosu55_interface.h:812
@ ACC_FORMAT_I32
Definition ethosu55_interface.h:811
@ ACC_FORMAT_F16
Definition ethosu55_interface.h:813
#define CONSTEXPR
Definition ethosu55_interface.h:30
cmd1_opcode
Definition ethosu55_interface.h:945
@ CMD1_OPCODE_NPU_SET_OFM_STRIDE_X
Definition ethosu55_interface.h:957
@ CMD1_OPCODE_NPU_SET_DMA0_LEN
Definition ethosu55_interface.h:969
@ CMD1_OPCODE_NPU_SET_IFM2_BASE2
Definition ethosu55_interface.h:972
@ CMD1_OPCODE_NPU_SET_IFM_STRIDE_X
Definition ethosu55_interface.h:950
@ CMD1_OPCODE_NPU_SET_OFM_STRIDE_C
Definition ethosu55_interface.h:959
@ CMD1_OPCODE_NPU_SET_IFM_BASE1
Definition ethosu55_interface.h:947
@ CMD1_OPCODE_NPU_SET_SCALE_BASE
Definition ethosu55_interface.h:962
@ CMD1_OPCODE_NPU_SET_SCALE_LENGTH
Definition ethosu55_interface.h:963
@ CMD1_OPCODE_NPU_SET_OPB_SCALE
Definition ethosu55_interface.h:966
@ CMD1_OPCODE_NPU_SET_DMA0_SRC
Definition ethosu55_interface.h:967
@ CMD1_OPCODE_NPU_SET_OFM_BASE2
Definition ethosu55_interface.h:955
@ CMD1_OPCODE_NPU_SET_IFM2_STRIDE_X
Definition ethosu55_interface.h:974
@ CMD1_OPCODE_NPU_SET_IFM2_BASE1
Definition ethosu55_interface.h:971
@ CMD1_OPCODE_NPU_SET_IFM_BASE3
Definition ethosu55_interface.h:949
@ CMD1_OPCODE_NPU_SET_OFM_BASE0
Definition ethosu55_interface.h:953
@ CMD1_OPCODE_NPU_SET_IFM_BASE0
Definition ethosu55_interface.h:946
@ CMD1_OPCODE_NPU_SET_WEIGHT_LENGTH
Definition ethosu55_interface.h:961
@ CMD1_OPCODE_NPU_SET_IFM2_BASE0
Definition ethosu55_interface.h:970
@ CMD1_OPCODE_NPU_SET_OFM_SCALE
Definition ethosu55_interface.h:964
@ CMD1_OPCODE_NPU_SET_IFM2_BASE3
Definition ethosu55_interface.h:973
@ CMD1_OPCODE_NPU_SET_DMA0_DST
Definition ethosu55_interface.h:968
@ CMD1_OPCODE_NPU_SET_OFM_BASE3
Definition ethosu55_interface.h:956
@ CMD1_OPCODE_NPU_SET_IFM_STRIDE_C
Definition ethosu55_interface.h:952
@ CMD1_OPCODE_NPU_SET_IFM2_STRIDE_C
Definition ethosu55_interface.h:976
@ CMD1_OPCODE_NPU_SET_WEIGHT_BASE
Definition ethosu55_interface.h:960
@ CMD1_OPCODE_NPU_SET_OPA_SCALE
Definition ethosu55_interface.h:965
@ CMD1_OPCODE_NPU_SET_IFM_STRIDE_Y
Definition ethosu55_interface.h:951
@ CMD1_OPCODE_NPU_SET_IFM2_STRIDE_Y
Definition ethosu55_interface.h:975
@ CMD1_OPCODE_NPU_SET_IFM_BASE2
Definition ethosu55_interface.h:948
@ CMD1_OPCODE_NPU_SET_OFM_STRIDE_Y
Definition ethosu55_interface.h:958
@ CMD1_OPCODE_NPU_SET_OFM_BASE1
Definition ethosu55_interface.h:954
state
Definition ethosu55_interface.h:1211
@ STATE_STOPPED
Definition ethosu55_interface.h:1212
@ STATE_RUNNING
Definition ethosu55_interface.h:1213
ifm_upscale_mode
Definition ethosu55_interface.h:1056
@ IFM_UPSCALE_MODE_ZEROS
Definition ethosu55_interface.h:1059
@ IFM_UPSCALE_MODE_NONE
Definition ethosu55_interface.h:1057
@ IFM_UPSCALE_MODE_NEAREST
Definition ethosu55_interface.h:1058
max_beats
Definition ethosu55_interface.h:1075
@ MAX_BEATS_B64
Definition ethosu55_interface.h:1076
@ MAX_BEATS_B256
Definition ethosu55_interface.h:1078
@ MAX_BEATS_B128
Definition ethosu55_interface.h:1077
axi_mem_encoding
Definition ethosu55_interface.h:860
@ AXI_MEM_ENCODING_WRITE_BACK_READ_ALLOCATE
Definition ethosu55_interface.h:870
@ AXI_MEM_ENCODING_WRITE_BACK_READ_AND_WRITE_ALLOCATE
Definition ethosu55_interface.h:872
@ AXI_MEM_ENCODING_WRITE_THROUGH_WRITE_ALLOCATE
Definition ethosu55_interface.h:867
@ AXI_MEM_ENCODING_WRITE_BACK_WRITE_ALLOCATE
Definition ethosu55_interface.h:871
@ AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_NON_BUFFERABLE
Definition ethosu55_interface.h:863
@ AXI_MEM_ENCODING_WRITE_THROUGH_READ_ALLOCATE
Definition ethosu55_interface.h:866
@ AXI_MEM_ENCODING_NORMAL_NON_CACHEABLE_BUFFERABLE
Definition ethosu55_interface.h:864
@ AXI_MEM_ENCODING_WRITE_THROUGH_READ_AND_WRITE_ALLOCATE
Definition ethosu55_interface.h:868
@ AXI_MEM_ENCODING_WRITE_BACK_NO_ALLOCATE
Definition ethosu55_interface.h:869
@ AXI_MEM_ENCODING_DEVICE_BUFFERABLE
Definition ethosu55_interface.h:862
@ AXI_MEM_ENCODING_DEVICE_NON_BUFFERABLE
Definition ethosu55_interface.h:861
@ AXI_MEM_ENCODING_WRITE_THROUGH_NO_ALLOCATE
Definition ethosu55_interface.h:865
kernel_decomposition
Definition ethosu55_interface.h:1063
@ KERNEL_DECOMPOSITION_D4X4
Definition ethosu55_interface.h:1065
@ KERNEL_DECOMPOSITION_D8X8
Definition ethosu55_interface.h:1064
functional_safety
Definition ethosu55_interface.h:1037
@ FUNCTIONAL_SAFETY_NOT_IMPLEMENTED
Definition ethosu55_interface.h:1038
@ FUNCTIONAL_SAFETY_IMPLEMENTED
Definition ethosu55_interface.h:1039
dma_fault_src
Definition ethosu55_interface.h:1006
@ DMA_FAULT_SRC_AXI_M0
Definition ethosu55_interface.h:1007
@ DMA_FAULT_SRC_AXI_M1
Definition ethosu55_interface.h:1008
elementwise_mode
Definition ethosu55_interface.h:1023
@ ELEMENTWISE_MODE_SHR
Definition ethosu55_interface.h:1032
@ ELEMENTWISE_MODE_SHL
Definition ethosu55_interface.h:1033
@ ELEMENTWISE_MODE_SUB
Definition ethosu55_interface.h:1026
@ ELEMENTWISE_MODE_MAX
Definition ethosu55_interface.h:1028
@ ELEMENTWISE_MODE_MUL
Definition ethosu55_interface.h:1024
@ ELEMENTWISE_MODE_CLZ
Definition ethosu55_interface.h:1031
@ ELEMENTWISE_MODE_ABS
Definition ethosu55_interface.h:1030
@ ELEMENTWISE_MODE_ADD
Definition ethosu55_interface.h:1025
@ ELEMENTWISE_MODE_MIN
Definition ethosu55_interface.h:1027
@ ELEMENTWISE_MODE_LRELU
Definition ethosu55_interface.h:1029
cmd0_opcode
Definition ethosu65_interface.h:895
@ CMD0_OPCODE_NPU_SET_PARALLEL_MODE
Definition ethosu65_interface.h:934
@ DMA_STRIDE_MODE_D2
Definition ethosu65_interface.h:1026
@ DMA_STRIDE_MODE_D3
Definition ethosu65_interface.h:1027
cmd_ctrl
Definition ethosu65_interface.h:1000
parallel_mode
Definition ethosu65_interface.h:1104
@ PARALLEL_MODE_SINGLE_CORE
Definition ethosu65_interface.h:1105
@ PARALLEL_MODE_DUAL_CORE_DEPTH
Definition ethosu65_interface.h:1106
cmd1_opcode
Definition ethosu65_interface.h:959
@ CMD1_OPCODE_NPU_SET_SCALE1_LENGTH
Definition ethosu65_interface.h:996
@ CMD1_OPCODE_NPU_SET_WEIGHT1_LENGTH
Definition ethosu65_interface.h:994
@ CMD1_OPCODE_NPU_SET_DMA0_SKIP1
Definition ethosu65_interface.h:985
@ CMD1_OPCODE_NPU_SET_WEIGHT1_BASE
Definition ethosu65_interface.h:993
@ CMD1_OPCODE_NPU_SET_SCALE1_BASE
Definition ethosu65_interface.h:995
@ CMD1_OPCODE_NPU_SET_DMA0_SKIP0
Definition ethosu65_interface.h:984
int size
Definition hello_world_model.cc:113
Definition ethosu55_interface.h:15885
STRUCT debugcore_r DEBUGCORE
Definition ethosu65_interface.h:16345
STRUCT scale1_base_r SCALE1_BASE
Definition ethosu65_interface.h:16502
STRUCT scale1_length_r SCALE1_LENGTH
Definition ethosu65_interface.h:16503
STRUCT parallel_mode_r PARALLEL_MODE
Definition ethosu65_interface.h:16431
STRUCT dma0_skip0_r DMA0_SKIP0
Definition ethosu65_interface.h:16489
STRUCT weight1_base_r WEIGHT1_BASE
Definition ethosu65_interface.h:16500
STRUCT weight1_length_r WEIGHT1_LENGTH
Definition ethosu65_interface.h:16501
STRUCT dma0_skip1_r DMA0_SKIP1
Definition ethosu65_interface.h:16490
Definition ethosu55_interface.h:12439
Definition ethosu55_interface.h:12253
Definition ethosu55_interface.h:12191
Definition ethosu55_interface.h:12129
Definition ethosu55_interface.h:5243
Definition ethosu55_interface.h:4006
Definition ethosu55_interface.h:4139
Definition ethosu55_interface.h:4272
Definition ethosu55_interface.h:4405
Definition ethosu55_interface.h:4539
uint32_t offset_HI
Definition ethosu65_interface.h:4543
uint32_t offset_LO
Definition ethosu65_interface.h:4542
Definition ethosu55_interface.h:12501
Definition ethosu55_interface.h:15638
Definition ethosu55_interface.h:15700
Definition ethosu55_interface.h:15762
Definition ethosu55_interface.h:15824
Definition ethosu55_interface.h:6739
Definition ethosu55_interface.h:2980
Definition ethosu55_interface.h:3564
Definition ethosu55_interface.h:9958
Definition ethosu55_interface.h:10082
Definition ethosu55_interface.h:10020
Definition ethosu55_interface.h:9846
Definition ethosu55_interface.h:6907
Definition ethosu55_interface.h:7032
Definition ethosu55_interface.h:6969
Definition ethosu65_interface.h:7029
uint32_t word
Definition ethosu65_interface.h:7037
uint32_t core
Definition ethosu65_interface.h:7035
Definition ethosu55_interface.h:14629
Definition ethosu55_interface.h:12625
Definition ethosu55_interface.h:14679
Definition ethosu55_interface.h:12687
Definition ethosu55_interface.h:12749
Definition ethosu65_interface.h:14858
uint32_t value_LO
Definition ethosu65_interface.h:14864
uint32_t value_HI
Definition ethosu65_interface.h:14865
Definition ethosu65_interface.h:14908
uint32_t value_HI
Definition ethosu65_interface.h:14915
uint32_t value_LO
Definition ethosu65_interface.h:14914
Definition ethosu55_interface.h:14579
Definition ethosu55_interface.h:12563
Definition ethosu55_interface.h:9684
Definition ethosu55_interface.h:9634
uint32_t offset_HI
Definition ethosu65_interface.h:9704
uint32_t offset_LO
Definition ethosu65_interface.h:9703
Definition ethosu55_interface.h:9410
Definition ethosu55_interface.h:9360
uint32_t offset_LO
Definition ethosu65_interface.h:9426
uint32_t offset_HI
Definition ethosu65_interface.h:9427
Definition ethosu55_interface.h:9796
uint32_t offset_HI
Definition ethosu65_interface.h:9868
uint32_t offset_LO
Definition ethosu65_interface.h:9867
Definition ethosu55_interface.h:9746
uint32_t offset_HI
Definition ethosu65_interface.h:9817
uint32_t offset_LO
Definition ethosu65_interface.h:9816
Definition ethosu55_interface.h:9534
uint32_t offset_HI
Definition ethosu65_interface.h:9602
uint32_t offset_LO
Definition ethosu65_interface.h:9601
Definition ethosu55_interface.h:9472
Definition ethosu55_interface.h:9908
uint32_t offset_LO
Definition ethosu65_interface.h:9980
uint32_t offset_HI
Definition ethosu65_interface.h:9981
Definition ethosu55_interface.h:5475
Definition ethosu55_interface.h:6191
Definition ethosu55_interface.h:9584
uint32_t offset_HI
Definition ethosu65_interface.h:9653
uint32_t offset_LO
Definition ethosu65_interface.h:9652
Definition ethosu55_interface.h:2486
Definition ethosu55_interface.h:14729
Definition ethosu55_interface.h:14779
Definition ethosu55_interface.h:14829
Definition ethosu55_interface.h:14879
Definition ethosu55_interface.h:12811
Definition ethosu55_interface.h:13121
Definition ethosu55_interface.h:13183
Definition ethosu55_interface.h:13245
Definition ethosu55_interface.h:12935
Definition ethosu55_interface.h:13307
Definition ethosu55_interface.h:12873
Definition ethosu55_interface.h:15029
Definition ethosu55_interface.h:14929
Definition ethosu55_interface.h:14979
Definition ethosu55_interface.h:13059
Definition ethosu55_interface.h:12997
Definition ethosu55_interface.h:13369
Definition ethosu55_interface.h:13419
Definition ethosu55_interface.h:13469
Definition ethosu55_interface.h:13519
Definition ethosu55_interface.h:8802
Definition ethosu55_interface.h:9298
Definition ethosu55_interface.h:9236
Definition ethosu55_interface.h:10579
Definition ethosu55_interface.h:10889
Definition ethosu55_interface.h:10951
Definition ethosu55_interface.h:11013
Definition ethosu55_interface.h:10517
Definition ethosu55_interface.h:10393
Definition ethosu55_interface.h:10455
Definition ethosu55_interface.h:10331
Definition ethosu55_interface.h:10641
Definition ethosu55_interface.h:11075
Definition ethosu55_interface.h:13669
Definition ethosu55_interface.h:13569
Definition ethosu55_interface.h:13619
Definition ethosu55_interface.h:10703
Definition ethosu55_interface.h:10827
Definition ethosu55_interface.h:9050
Definition ethosu55_interface.h:10765
Definition ethosu55_interface.h:8554
Definition ethosu55_interface.h:11943
Definition ethosu55_interface.h:12005
Definition ethosu55_interface.h:8492
Definition ethosu55_interface.h:11881
Definition ethosu55_interface.h:8368
Definition ethosu55_interface.h:8430
Definition ethosu55_interface.h:3734
Definition ethosu55_interface.h:4864
Definition ethosu55_interface.h:18112
Definition ethosu55_interface.h:18168
Definition ethosu55_interface.h:18382
Definition ethosu55_interface.h:18438
Definition ethosu55_interface.h:18303
Definition ethosu55_interface.h:18039
Definition ethosu55_interface.h:18512
Definition ethosu55_interface.h:18586
Definition ethosu55_interface.h:18224
Definition ethosu55_interface.h:17966
Definition ethosu55_interface.h:21524
Definition ethosu55_interface.h:21270
Definition ethosu55_interface.h:21196
Definition ethosu55_interface.h:21098
Definition ethosu55_interface.h:21599
Definition ethosu55_interface.h:21802
Definition ethosu55_interface.h:24549
uint32_t addr_lo
Definition ethosu65_interface.h:24737
uint32_t addr_hi
Definition ethosu65_interface.h:24735
Definition ethosu55_interface.h:24625
uint32_t addr_hi
Definition ethosu65_interface.h:24797
uint32_t addr_lo
Definition ethosu65_interface.h:24799
Definition ethosu55_interface.h:21931
Definition ethosu55_interface.h:22004
Definition ethosu65_interface.h:24852
uint32_t addr_lo
Definition ethosu65_interface.h:24861
uint32_t reserved0
Definition ethosu65_interface.h:24857
uint32_t addr_hi
Definition ethosu65_interface.h:24859
uint32_t control
Definition ethosu65_interface.h:24858
uint32_t reserved1
Definition ethosu65_interface.h:24860
uint32_t opcode
Definition ethosu65_interface.h:24856
Definition ethosu65_interface.h:24914
uint32_t control
Definition ethosu65_interface.h:24920
uint32_t opcode
Definition ethosu65_interface.h:24918
uint32_t reserved0
Definition ethosu65_interface.h:24919
uint32_t addr_lo
Definition ethosu65_interface.h:24923
uint32_t reserved1
Definition ethosu65_interface.h:24922
uint32_t addr_hi
Definition ethosu65_interface.h:24921
Definition ethosu55_interface.h:21674
Definition ethosu55_interface.h:24473
uint32_t addr_lo
Definition ethosu65_interface.h:24675
uint32_t addr_hi
Definition ethosu65_interface.h:24673
Definition ethosu55_interface.h:24701
uint32_t addr_hi
Definition ethosu65_interface.h:24983
uint32_t addr_lo
Definition ethosu65_interface.h:24985
Definition ethosu55_interface.h:24777
uint32_t addr_hi
Definition ethosu65_interface.h:25045
uint32_t addr_lo
Definition ethosu65_interface.h:25047
Definition ethosu55_interface.h:24853
uint32_t addr_lo
Definition ethosu65_interface.h:25109
uint32_t addr_hi
Definition ethosu65_interface.h:25107
Definition ethosu55_interface.h:24929
uint32_t addr_hi
Definition ethosu65_interface.h:25169
uint32_t addr_lo
Definition ethosu65_interface.h:25171
Definition ethosu55_interface.h:22077
Definition ethosu55_interface.h:22563
Definition ethosu55_interface.h:22636
Definition ethosu55_interface.h:22709
Definition ethosu55_interface.h:22300
Definition ethosu55_interface.h:22784
Definition ethosu55_interface.h:22227
Definition ethosu55_interface.h:25157
uint32_t addr_hi
Definition ethosu65_interface.h:25355
uint32_t addr_lo
Definition ethosu65_interface.h:25357
Definition ethosu55_interface.h:25005
uint32_t addr_lo
Definition ethosu65_interface.h:25233
uint32_t addr_hi
Definition ethosu65_interface.h:25231
Definition ethosu55_interface.h:25081
uint32_t addr_hi
Definition ethosu65_interface.h:25293
uint32_t addr_lo
Definition ethosu65_interface.h:25295
Definition ethosu55_interface.h:22490
Definition ethosu55_interface.h:22416
Definition ethosu55_interface.h:22859
uint32_t addr_hi
Definition ethosu65_interface.h:23283
uint32_t addr_lo
Definition ethosu65_interface.h:23285
Definition ethosu55_interface.h:22935
uint32_t addr_lo
Definition ethosu65_interface.h:23347
uint32_t addr_hi
Definition ethosu65_interface.h:23345
Definition ethosu55_interface.h:23011
uint32_t addr_lo
Definition ethosu65_interface.h:23409
uint32_t addr_hi
Definition ethosu65_interface.h:23407
Definition ethosu55_interface.h:23087
uint32_t addr_hi
Definition ethosu65_interface.h:23469
uint32_t addr_lo
Definition ethosu65_interface.h:23471
Definition ethosu55_interface.h:18957
Definition ethosu55_interface.h:19404
Definition ethosu55_interface.h:19477
Definition ethosu55_interface.h:19550
Definition ethosu55_interface.h:18883
Definition ethosu55_interface.h:18735
Definition ethosu55_interface.h:18809
Definition ethosu55_interface.h:18661
Definition ethosu55_interface.h:19030
Definition ethosu55_interface.h:19625
Definition ethosu55_interface.h:23315
uint32_t addr_lo
Definition ethosu65_interface.h:23657
uint32_t addr_hi
Definition ethosu65_interface.h:23655
Definition ethosu55_interface.h:23163
uint32_t addr_hi
Definition ethosu65_interface.h:23531
uint32_t addr_lo
Definition ethosu65_interface.h:23533
Definition ethosu55_interface.h:23239
uint32_t addr_hi
Definition ethosu65_interface.h:23593
uint32_t addr_lo
Definition ethosu65_interface.h:23595
Definition ethosu55_interface.h:19179
Definition ethosu55_interface.h:19331
Definition ethosu55_interface.h:19257
Definition ethosu55_interface.h:20763
Definition ethosu55_interface.h:20836
Definition ethosu55_interface.h:20690
Definition ethosu55_interface.h:23391
uint32_t addr_hi
Definition ethosu65_interface.h:23717
uint32_t addr_lo
Definition ethosu65_interface.h:23719
Definition ethosu55_interface.h:23467
uint32_t addr_hi
Definition ethosu65_interface.h:23779
uint32_t addr_lo
Definition ethosu65_interface.h:23781
Definition ethosu55_interface.h:23543
uint32_t addr_lo
Definition ethosu65_interface.h:23843
uint32_t addr_hi
Definition ethosu65_interface.h:23841
Definition ethosu55_interface.h:23619
uint32_t addr_hi
Definition ethosu65_interface.h:23903
uint32_t addr_lo
Definition ethosu65_interface.h:23905
Definition ethosu55_interface.h:20232
Definition ethosu55_interface.h:20157
Definition ethosu55_interface.h:20082
Definition ethosu55_interface.h:19861
Definition ethosu55_interface.h:20454
Definition ethosu55_interface.h:20527
Definition ethosu55_interface.h:19788
Definition ethosu55_interface.h:19934
Definition ethosu55_interface.h:20600
Definition ethosu55_interface.h:24225
Definition ethosu55_interface.h:23847
uint32_t addr_lo
Definition ethosu65_interface.h:24091
uint32_t addr_hi
Definition ethosu65_interface.h:24089
Definition ethosu55_interface.h:23695
uint32_t addr_lo
Definition ethosu65_interface.h:23967
uint32_t addr_hi
Definition ethosu65_interface.h:23965
Definition ethosu55_interface.h:23771
uint32_t addr_hi
Definition ethosu65_interface.h:24027
uint32_t addr_lo
Definition ethosu65_interface.h:24029
Definition ethosu55_interface.h:20381
Definition ethosu55_interface.h:19715
Definition ethosu55_interface.h:20307
Definition ethosu55_interface.h:24311
Definition ethosu55_interface.h:24397
Definition ethosu65_interface.h:21422
uint32_t parallel_mode
Definition ethosu65_interface.h:21429
uint32_t reserved1
Definition ethosu65_interface.h:21430
uint32_t opcode
Definition ethosu65_interface.h:21426
uint32_t control
Definition ethosu65_interface.h:21428
uint32_t reserved0
Definition ethosu65_interface.h:21427
Definition ethosu65_interface.h:25546
uint32_t addr_lo
Definition ethosu65_interface.h:25555
uint32_t control
Definition ethosu65_interface.h:25552
uint32_t reserved1
Definition ethosu65_interface.h:25554
uint32_t addr_hi
Definition ethosu65_interface.h:25553
uint32_t reserved0
Definition ethosu65_interface.h:25551
uint32_t opcode
Definition ethosu65_interface.h:25550
Definition ethosu65_interface.h:25608
uint32_t reserved0
Definition ethosu65_interface.h:25613
uint32_t length
Definition ethosu65_interface.h:25616
uint32_t control
Definition ethosu65_interface.h:25614
uint32_t reserved2
Definition ethosu65_interface.h:25617
uint32_t reserved1
Definition ethosu65_interface.h:25615
uint32_t opcode
Definition ethosu65_interface.h:25612
Definition ethosu55_interface.h:24073
uint32_t addr_lo
Definition ethosu65_interface.h:24289
uint32_t addr_hi
Definition ethosu65_interface.h:24287
Definition ethosu55_interface.h:24149
Definition ethosu55_interface.h:21434
Definition ethosu65_interface.h:25410
uint32_t control
Definition ethosu65_interface.h:25416
uint32_t addr_hi
Definition ethosu65_interface.h:25417
uint32_t reserved0
Definition ethosu65_interface.h:25415
uint32_t reserved1
Definition ethosu65_interface.h:25418
uint32_t addr_lo
Definition ethosu65_interface.h:25419
uint32_t opcode
Definition ethosu65_interface.h:25414
Definition ethosu65_interface.h:25472
uint32_t reserved0
Definition ethosu65_interface.h:25477
uint32_t reserved1
Definition ethosu65_interface.h:25479
uint32_t length
Definition ethosu65_interface.h:25480
uint32_t control
Definition ethosu65_interface.h:25478
uint32_t opcode
Definition ethosu65_interface.h:25476
Definition ethosu55_interface.h:23923
uint32_t addr_lo
Definition ethosu65_interface.h:24153
uint32_t addr_hi
Definition ethosu65_interface.h:24151
Definition ethosu55_interface.h:23999
Definition ethosu55_interface.h:21344
Definition ethosu55_interface.h:13719
Definition ethosu55_interface.h:13769
Definition ethosu55_interface.h:13819
Definition ethosu55_interface.h:13869
Definition ethosu55_interface.h:11509
Definition ethosu55_interface.h:11447
Definition ethosu55_interface.h:11385
Definition ethosu55_interface.h:8740
Definition ethosu55_interface.h:8678
Definition ethosu55_interface.h:8616
Definition ethosu55_interface.h:11261
Definition ethosu55_interface.h:11695
Definition ethosu55_interface.h:11757
Definition ethosu55_interface.h:11199
Definition ethosu55_interface.h:11323
Definition ethosu55_interface.h:11819
Definition ethosu55_interface.h:14269
Definition ethosu55_interface.h:14331
Definition ethosu55_interface.h:14019
Definition ethosu55_interface.h:13919
Definition ethosu55_interface.h:13969
Definition ethosu55_interface.h:11633
Definition ethosu55_interface.h:11137
Definition ethosu55_interface.h:8864
Definition ethosu55_interface.h:8926
Definition ethosu55_interface.h:8988
Definition ethosu55_interface.h:11571
Definition ethosu55_interface.h:14393
Definition ethosu55_interface.h:14455
Definition ethosu55_interface.h:14517
Definition ethosu55_interface.h:9174
Definition ethosu55_interface.h:9112
Definition ethosu65_interface.h:12134
uint32_t value
Definition ethosu65_interface.h:12140
uint32_t word
Definition ethosu65_interface.h:12142
Definition ethosu55_interface.h:15389
Definition ethosu55_interface.h:15452
Definition ethosu55_interface.h:15514
Definition ethosu55_interface.h:15576
Definition ethosu55_interface.h:15141
Definition ethosu55_interface.h:15203
Definition ethosu55_interface.h:15265
Definition ethosu55_interface.h:15327
Definition ethosu55_interface.h:8260
Definition ethosu55_interface.h:8175
Definition ethosu55_interface.h:8124
Definition ethosu55_interface.h:7389
Definition ethosu55_interface.h:7242
Definition ethosu55_interface.h:7094
Definition ethosu55_interface.h:10144
Definition ethosu55_interface.h:10206
Definition ethosu55_interface.h:7977
Definition ethosu55_interface.h:7830
Definition ethosu55_interface.h:7683
Definition ethosu55_interface.h:7536
Definition ethosu55_interface.h:3476
Definition ethosu55_interface.h:3239
uint32_t offset_LO
Definition ethosu65_interface.h:3241
uint32_t offset_HI
Definition ethosu65_interface.h:3242
Definition ethosu55_interface.h:3351
Definition ethosu55_interface.h:3289
Definition ethosu55_interface.h:3414
Definition ethosu55_interface.h:3796
Definition ethosu55_interface.h:3151
Definition ethosu55_interface.h:15079
Definition ethosu65_interface.h:15408
uint32_t value_LO
Definition ethosu65_interface.h:15414
uint32_t value_HI
Definition ethosu65_interface.h:15415
Definition ethosu65_interface.h:15458
uint32_t value_HI
Definition ethosu65_interface.h:15465
uint32_t value_LO
Definition ethosu65_interface.h:15464
Definition ethosu55_interface.h:14169
Definition ethosu55_interface.h:14219
Definition ethosu55_interface.h:12377
Definition ethosu55_interface.h:10269
Definition ethosu55_interface.h:2676
Definition ethosu55_interface.h:4589
Definition ethosu65_interface.h:15308
uint32_t value_LO
Definition ethosu65_interface.h:15314
uint32_t value_HI
Definition ethosu65_interface.h:15315
Definition ethosu65_interface.h:15358
uint32_t value_LO
Definition ethosu65_interface.h:15364
uint32_t value_HI
Definition ethosu65_interface.h:15365
Definition ethosu55_interface.h:14069
Definition ethosu55_interface.h:14119
Definition ethosu55_interface.h:12315
uint8_t value
Definition wm8960_regs.h:134
const uint16_t mask
Definition wm8960_regs.h:94
const uint8_t shift
Definition wm8960_regs.h:95